CN101839962B - Method for sieving frequency of processor chip - Google Patents
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Abstract
The invention relates to a method for sieving the frequency of a processor chip, which comprises the following four steps of: obtaining an instruction level function testing vector used for sieving the frequency according to the optimization of the coverage rate of a physical critical path; writing the instruction level function testing vector used for sieving the frequency into a high-speed buffer memory of the processor chip by a scan chain device; and configuring a phase lock ring high-speed clock for the processor chip on an automatic testing instrument, executing the instruction level function testing vector in the high-speed buffer memory to sieve the frequency and evaluating the frequency grade of the processor chip. The method can also comprise the following steps of: obtaining a frequency deviation by sampling the processor chip and carrying out plate level function testing, correcting and calibrating the final frequency of the processor chip. The invention has simple method, low cost and accurate and effective result.
Description
Technical field
The present invention relates to a kind of frequency of processor chip treatment technology, particularly, be specifically related to a kind of utilize scan chain device input instruction level function testing vector carry out the frequency of processor chip method for screening.
Background technology
The process that highest frequency when the frequency test of chip is meant and normally moves according to chip self function is classified to chip product.Along with the development of dark Ya Nami manufacturing process, the caused chip performance deviation of defective is increasing by manufacturing.In general, high performance chips (like processor chips etc.) is after producing; Before in user's hand; All need screen,, chip evaluated and divided into groups promptly according to different chip functions frequencies to the frequency of chip; And chip price divided: frequency is high, and the market price is also high; Frequency is low, and price is also low.From the above mentioned, frequency screening will be demarcated the different working frequency to chip, select the chip of corresponding frequencies to different running environment, thereby reduce chip cost.
Different frequency appears in chip, is had under actual production environment by the wire delay of chip and gate delay normally that slightly difference causes.On the classic method; The evaluation and the grouping of chip frequency are accomplished on board level system; But utilize board level test method more complicated; And need the stable of special and reliable test macro (like handling procedure and testing jack etc.), in addition, the cost when this method is used for the monster chip frequency screening is very high.
In addition; Scientific research academia proposition at present some utilize structured testing vector (scan test vector) to carry out the chip frequency method for screening; But because the instruction of structured testing vector sum actual motion and inequality; Therefore need constantly carry out frequency correction, and need the various structure test vector to different processes.Even the structured testing vector after proofreading and correct can not reflect the running frequency of chip completely, so the prematurity still of this method, the chip frequency that draws also lacks accuracy.
Summary of the invention
One of the object of the invention is to provide a kind of frequency of processor chip method for screening, and it is a kind of method of testing of instruction-level, and its method is simple, reduces cost again, and is more accurate and effective than structured testing method.
To achieve these goals, the invention provides a kind of screening technique of frequency of processor chip, may further comprise the steps:
Step S001 obtains being used to carry out the instruction level function testing vector of frequency screening according to the optimization of physics critical path coverage rate;
Step S002 writes said processor chips high-speed cache through scan chain device with the said instruction level function testing vector that is used for frequency screening;
Step S003 is said processor chip configuration phase-locked loop high-frequency clock on Automatic Test Equipment, and the instruction level function testing vector of carrying out in the said high-speed cache is carried out frequency screening, evaluates the frequency class of said processor chips.
More excellent ground, frequency of processor chip screening technique of the present invention, further comprising the steps of:
Step S004 through andante level functional test that said processor chips sampling is gone forward side by side, obtains frequency departure, proofreaies and correct and demarcate the final frequency of said processor chips.。
In the screening technique of frequency of processor chip of the present invention; Utilize the optimization of physics critical path coverage rate to obtain in the instruction level function testing vector that is used to carry out frequency screening; Through scan chain device the instruction and data that test vector needs is filled in one-level instruction cache, one-level data cache and the second level cache of processor chips; (Phase Locked Loop, PLL) high-frequency clock pass through Automatic Test Equipment (Automatic Test Equipment under real fast state to start phase-locked loop subsequently; ATE) operating instruction level functional test program; Finally through the operation result of routine analyzer, can the assessment chip run on this frequency, thereby realized the frequency screening of processor chips.It is a kind of accurate and effective, simply, chip frequency screening technique cheaply, simpler than traditional ATE high-speed functions method of testing, more much lower than frequency test cost based on board level system, more accurate and effective than structured testing method.
Description of drawings
Fig. 1 is the process flow diagram of the chip frequency screening technique of the specific embodiment of the invention;
Fig. 2 is the method flow diagram of the path coverage rate of the specific embodiment of the invention to the optimization of instruction level function testing vector;
Fig. 3 is the scan chain of the specific embodiment of the invention and the graph of a relation between the high-speed cache;
Fig. 4 writes the internally cached method flow diagram of processor for the scan chain that passes through of the specific embodiment of the invention with instruction level function testing vector;
Fig. 5 carries out the method flow diagram of frequency screening for the execution processor chips of the specific embodiment of the invention instruction level function testing vector in internally cached;
Fig. 6 carries out the method for correcting process flow diagram for the chip frequency of Fig. 5 evaluation of the specific embodiment of the invention.
Embodiment
To combine each accompanying drawing below, the practical implementation method of the chip frequency screening technique of the present invention among Fig. 1 done describing in further detail successively.
One, step S001: optimize the instruction level function testing vector that obtains being used to carry out frequency screening
Optimizing the instruction level function testing vector obtain being used for carrying out frequency screening is the very important step of the inventive method.The test chip frequency because instruction level function testing vector will be filled in the high-speed cache of processor, therefore, the instruction level function testing vector that is used to carry out frequency screening has the restriction and the requirement of following five aspects:
(1) instruction level function testing vector is custom-designed to each key feature of processor.For example for floating-point calculation component, need instruction, comprise floating-point plus-minus, FML, floating divide etc., and these computings not only will comprise the situation of normal input, and comprise the situation of various borders computing to various computing situation design floating-point operations.
(2) instruction level function testing vector comprises and tests out misinterpretation.When processor operates under the current frequency, if occur mistake in the test process, the test result signal of this chip will be set.
(3) volume of instruction level function testing vector can not be too big.In order to realize real fast test processor; Instruction level function testing vector all leaves in the inner cache memory of processor; Like the one-level Instructions Cache in the processor, one-level metadata cache and L2 cache etc., therefore, the volume of test vector receives the restriction of cache memory sizes.
The address of (4) quoting in the instruction level function testing vector all is the real address in the buffer memory.In order to let chip real speed move, necessarily require in test process, no longer to read test data outside the sheet, and only from buffer memory, read, the address space that therefore requires to quote in the test procedure is limited in the buffer memory scope, and is effective to guarantee the address.
(5) instruction level function testing vector does not comprise instructions such as exception, interruption.Because frequency test needs speed test in fact in the hope of chip frequency, so can not occur in the instruction level function testing vector operational process interrupting or the exception processing.That for example visits internal memory is written into instruction (load), and storage instruction (store) etc. should not appear in the instruction level function testing vector.
In sum, the design and the factor that generative process need be considered of instruction level function testing vector that is used to carry out frequency screening is a lot, and design difficulty is very big.In order to obtain being used to carry out the instruction level function testing vector of frequency screening, reduce the error of chip frequency screening, this method is optimized according to physics critical path coverage rate.Wherein, The physics critical path is to choose a tightest set of paths of sequential according to the physical location of each circuit devcie unit in the chip; Foundation and feedback that physics critical path coverage rate will be optimized as instruction level function testing vector; If the coverage rate of critical path is high more, explain that the resultant error of frequency screening will be littler.Therefore, physics critical path coverage rate is to optimize the important evidence of instruction level function testing vector.
The process flow diagram that obtains being used to carrying out the instruction level function testing vector of frequency screening according to this specific embodiment explanation according to the optimization of physics critical path coverage rate shown in Figure 2.This process is shown to accomplish under the grade simulated environment at net, and its step is following:
Step S101, processor chips get into normal mode of operation, normal instruction level function testing vector are write in the high-speed cache of said processor chips.
Normal instruction level function testing vector normal function instruction set (being instruction level function testing vector) is written to current test instruction and data in the cache memory of processor chips through scan chain; Phaselocked loop through chip starts high-frequency clock; Configuration control signal; Chip resetted makes chip get into functional mode, configuring chip internal control trigger, and get into step S102.
Step S102, execution command level function testing vector, and assessment physics critical path coverage rate.
Carry out the instruction level function testing vector in the chip high speed buffer memory, and according to the information of physics critical path, analyze and the path coverage rate of assessment present instruction level function testing vector, its computing method are following:
Wherein, total number of paths is meant the total number of select physics critical path from the physical layout of chip.Overlay path is meant that upset has all taken place the logical value of every line on this path of a certain moment simultaneously, promptly jumps to 1 by 0, or jumps to 0 by 1.The overlay path number is meant in the function testing vector operational process total number of overlay path.
Judge whether physics critical path coverage rate meets the demands.If the path coverage rate is crossed low and do not reached requirement, get into step S104 so; If the path coverage rate reaches requirement, get into step S105 so.
Step S104, the adjustment instruction level function testing vector.
Testing result according to the path coverage rate is adjusted functional test, adjusts the function command test vector targetedly to cover more physics critical path, improves the accuracy of frequency screening, gets into step S102 subsequently.
Step S105, the instruction level function testing vector that is used to carry out frequency screening after being optimized, optimization finishes.
In sum, for optimization obtains the high-quality method that is used to carry out the instruction level function testing vector of frequency screening according to the specific embodiment of the invention.
Two, step S002: the said instruction level function testing vector that is used for frequency screening is write said processor chips high-speed cache through scan chain device
Through scan chain device, instruction level function testing vector is filled in each high-speed cache of chip, thereby is that chip frequency screening operation on the ATE is ready.Below will combine Fig. 3 and Fig. 4 to specify this filling process.
Shown in Figure 3 is interconnected graph of a relation between scan chain and the high-speed cache of the specific embodiment of the invention.Scan chain in this specific embodiment can be from the direct access processor high-speed cache of chip exterior, like one-level Instructions Cache, one-level metadata cache, L2 cache etc.The implementation method of this scan chain is:
(1) trigger in the scan chain multiplex processor memory built in self test of sram circuit.The memory built in self test of sram circuit is the dedicated logic circuit that is used to test cache memory in the Testability Design; This circuit has been contained the all-access control port of storer, comprising: chip select line, read-write enable, address wire, data input, data output etc.
(2) trigger is all interconnected successively with the access port of storer.Scan chain has comprised port controlling triggers all in the memory built in self test of sram circuit, and with each trigger of test clock control, interconnected successively chaining.
(3) trigger type is a sweep trigger.Sweep trigger can obtain the scanning input from the upper level trigger, also can from storer, catch the memory read port value to transmit output.For example, a kind of sweep trigger type commonly used is for being equipped with the trigger of selector switch.
(4) input end of scan chain and output terminal all are the external terminals of chip.Through writing instruction level function testing vector to scan chain, to realize the purpose of initialization chip internal high-speed cache from the chip exterior pin.
(5) input through scan enable signals gated sweep trigger.When scan enable signals is effective, with the output numerical value of selecting the previous trigger in the scan chain as input; When the scan enable port is invalid, with the numerical value of selecting the flip-flop data port as input.
In sum, when the scan enable line is effective value, in the input pin input data of scan chain, under the control of test clock, data will be advanced along scan chain successively.When arriving the proper port of storer, it is invalid that scan enable will be changed to, and starts the chip select line of storer, and storer will read or write storer according to the sequence of operation of scan chain design.After once visit executes; The scan enable port will be changed to effectively once more; Under the control of test clock, the instruction sequence of reference-to storage will be delivered to the corresponding port of storer along scan chain next time, and such operation lasts till that always initializes memory finishes.
In addition; Because the scan control clock that scan chain uses is a clock at a slow speed, be generally 30MHZ between the 50MHZ, and scan chain is longer; Article one, scan chain comprises 800～1500 triggers usually, so the process of the cache memory of initialization processor is very slowly.For example; For the Instructions Cache of initialization 64K, the metadata cache of 64K and the L2 cache of 512K; Approximately need the test clock of millions of bats, promptly need a few tens of milliseconds to accomplish, the instruction and data in the operation high-speed cache then only needs the time of millisecond magnitude to accomplish.
Shown in Figure 4 for according to the process flow diagram that scan chain device writes the said instruction level function testing vector that is used for frequency screening said processor chips high-speed cache that passes through of the specific embodiment of the invention.Not only can be used for the high-speed cache in the initialization chip through scan chain, and can the error message in the test process be outputed to the reason that chip exterior is used for profiling error, its process such as following steps:
Step S201 writes the cache access instruction in scan chain.
Whether configuring chip: it is ready to detect test instruction and data if being the scan chain transfer mode; If be not ready to complete as yet at present; Then prepare current test instruction that will transmit and data,, then start test clock if be ready to complete; And under test clock control, in scan chain, transmit data one by one.
Step S202 judges read-write operation.
After scan chain was all write and expired, judgement was read operation or write operation: if write operation then gets into step S203; If read operation then gets into S204.
Step S203 carries out write operation to storer.
The sheet choosing that moves into storer through scan chain enables, writes enable signal, writes address etc.; Scan enable is set to invalid; And then according to the control signal in the scan chain; Storer is carried out write operation, under the appropriate address with the input writing data into memory in the scan chain, and then change step S205 over to.
Step S204 carries out read operation to storer.
The sheet choosing that moves into storer through scan chain enables, reads enable signal, reads address etc.; Scan enable is set to invalid; Storer is carried out read operation, and scan chain will be caught the output valve of the data-out port of storer, and be saved in the trigger of scan chain.
Step S205 also need to judge whether cache access.
If also need access cache, then get into step S201, continue next time visit to storer; If no longer need cache access, then get into step S206.
Step S206 accomplishes the visit internally cached to chip.
For the write operation of buffer memory, the chip high speed buffer memory has been written into instruction level function testing vector, can setting up procedure S003; For read operation, the content in the chip high speed buffer memory is all read, can be used for sheet outer analysis and error diagnosis.
In sum, be the method that scan chain device writes the said instruction level function testing vector that is used for frequency screening said processor chips high-speed cache of passing through according to the specific embodiment of the invention.
Three, step S003: be said processor chip configuration phase-locked loop high-frequency clock on Automatic Test Equipment, the instruction level function testing vector of carrying out in the said high-speed cache is carried out frequency screening, evaluates the frequency class of said processor chips
In producing chip processes, use and said chip is carried out frequency screening according to the method for this specific embodiment.This method is simpler than traditional board level system method of testing, cost is lower, and is more accurate and effective than structured testing method.
Shown in Figure 5 is the process flow diagram of the instruction level function testing vector method in internally cached according to the execution processor chips of the specific embodiment of the invention.The principle of the specific embodiment of the invention is that chip frequency is set to several rough class, 600MHZ for example, three frequency class of 800MHZ and 1GHz.On ATE, chip is carried out the instruction-level test according to the frequency class; If through the detection this frequency class under then this chip frequency obtain the affirmation; If then should not reduce the frequency class successively through the detection under this frequency class; Proceed to detect, until the frequency class that draws through detection under the chip.This method comprises following each step:
Step S301, chip reset.
Chip is set to the normal function pattern, the chip that resets, and get into step S302.
Step S302, according to the processor frequencies class of estimating, configuration also starts the current high-frequency clock of chip.
(Phase Locked Loop, PLL) high-frequency clock if test this chip first, then are set to highest frequency to the phase-locked loop of configuring chip; Otherwise, because the test errors marking signal of tester table is wrong among the step S305, so chip frequency is made as the frequency that is lower than a class of current frequency.Subsequently, start the phase-locked loop high-frequency clock, and get into step S303.
Step S303, chip set.
After the phase-locked loop high-frequency clock starts,, get into step S304 subsequently with processor set.
Step S304, configuring chip internal control trigger.
Through the control trigger in the chip is carried out initial configuration, processor will get into the normal function operational mode, and get into step S305.
Step S305, the instruction level function testing vector of carrying out in the cache memory is carried out frequency screening.
Chip according to the frequency of real speed operation, is carried out the instruction in the cache memory, thereby is carried out the test of frequency screening under the test pattern of normal function, gets into step S306 subsequently.
Step S306 judges test result.
The tester table probe detects testing end signal and test errors marking signal constantly; Wait for its variation: when testing end signal is set; If the test errors marking signal is no mismark, explain that then this chip may operate under the current frequency, so get into step S307; If the test errors marking signal, explains then that this chip not may operate under the current frequency for mismark is arranged, so change step S302 over to, the configuring chip clock is the frequency of a low class, proceeds test.
Step S307, the frequency class of record chip.
S306 is said like step, and after judging, the test errors marking signal is no mismark, when testing end signal is set, explains that this chip may operate under the frequency of current class, then writes down the affiliated frequency class of this chip.
In sum; For being said processor chip configuration phase-locked loop high-frequency clock on Automatic Test Equipment according to the specific embodiment of the invention; The instruction level function testing vector of carrying out in the said high-speed cache is carried out frequency screening, evaluates the method for the frequency class of said processor chips.
Four, step S004: through andante level functional test that said processor chips sampling is gone forward side by side, obtain frequency departure, proofread and correct and demarcate the final frequency of said processor chips
Shown in Figure 6 is the process flow diagram to the bearing calibration of instruction level function testing gained chip frequency according to the specific embodiment of the invention.In order to improve the accuracy of chip frequency screening, after carrying out the chip frequency screening, be necessary chip is implemented frequency correction; Simultaneously, in order to save cost, this trimming process is only carried out to the part sample drawn of chip.This process basic principle is; The chip of picked at random some; It is carried out the functional test of plate level, obtain the practical frequency of chip, and use the chip frequency that instruction level function testing write down to compare, analyze with step S003; Add up the chip frequency deviation, and chip frequency is proofreaied and correct.Its detailed step is following:
Step S401 randomly draws the processor chips after step S003 instruction level function testing of some.
Extract randomly the said processor chips of some after step S003 instruction level function testing as the calibrating frequency rate with positive sample, be used for the functional test of plate level, and get into step S402.
Step S402 places the said processor chips of step S401 the functional test plate of customization.
The said processor chips of step S401 are placed the functional test step of customization, and get into step S403.
Step S403, the current running frequency of configuring chip.
If current, then be set to highest frequency for testing this chip first; Otherwise be since the testing result of step S404 in the faults signal for mismark is arranged, then the chip clock is made as the frequency that is lower than a class of current frequency.Subsequently, get into step S404.
Step S404, operation function test, and faults.
Under the present clock frequency, operation function test, as start the operating system, various application programs etc.; Chip is carried out the functional test of plate level, simultaneously, the rub-out signal of measuring ability test; If mistake appears in functional test, show that then this chip can not be operated under the current frequency, then changes step S403; Reconfigure new one grade running frequency, and further new one takes turns test; If functional test is correct, show that then this chip can be operated under the current frequency, then changes step S405.
Step S405 demarcates chip board level test frequency.
Demarcate the chip frequency of the plate level functional test gained of this chip.The frequency of being tried to achieve when this board level test frequency is the normal operation of chip system, application software and test procedure, so this frequency is the actual operating frequency of chip; And the chip frequency of being tried to achieve on the ATE is merely a rough frequency class division (600MHZ; Three frequency class of 800MHZ and 1GHz); Therefore the chip frequency of board level test gained is more accurately than the chip frequency numerical value of the last gained of ATE, and the present invention utilizes deviation between the two to proofread and correct the chip frequency numerical value that ATE goes up gained.After accomplishing, this step gets into step S406.
Step S406 judges whether all sampling chips have all been tested and finished.
Judge whether all sampling chips have all been tested and finished.If still have the not test of sampling chip, then get into step S402, choose the sampling chip that does not have test, continue test; If all sampling chips have all been tested and finished, then get into step S407.
Step S407, calculated rate is proofreaied and correct mean value.
The plate level functional test frequency and the ATE that add up all sampling chips go up the mean deviation between the instruction level function testing frequency, and the calculated rate adjusted mean gets into step S408 subsequently.Gained frequency correction mean value have both positive and negative maybe, when plate level functional test averaging of income frequency is higher than instruction-level test average frequency, frequency correction mean value be on the occasion of; When plate level functional test averaging of income frequency was lower than instruction-level test average frequency, frequency correction mean value was negative value.
Step S408 implements chip frequency and proofreaies and correct.
Chip frequency according to step S407 is calculated is proofreaied and correct mean value, and instruction level function testing gained chip frequency is carried out frequency correction, obtains the final frequency numerical value of chip frequency screening.For example the last instruction level function testing demarcation of ATE processor chips running frequency is 600MHZ, three class of 800MHZ and 1GHz.When frequency correction mean value is correct time, the frequency of the instruction level function testing of chip (600MHZ, 800MHZ or 1GHZ) adds that the frequency that needs to proofread and correct is as final chip screening frequency.When frequency correction mean value when negative, the frequency of the instruction level function testing of chip (600M, 800M or 1GHZ) should cut the frequency that needs to proofread and correct as final chip screening frequency.
In sum, for according to the specific embodiment of the invention through the sampling andante level functional test of going forward side by side to said processor chips, obtain frequency departure, proofread and correct and demarcate the method for the final frequency of said processor chips.
The present invention relates to the screening technique of chip frequency; Through utilizing the optimization of physics critical path coverage rate to obtain being used to carry out the instruction level function testing vector of frequency, being used in the real fast operation processor carried out the instruction level function testing vector evaluation chip frequency of frequency screening; Further, use the method for plate level functional test to proofread and correct the processor frequencies class of being evaluated.It screens chip frequency, and is simple to operate, with low cost, and the effect accurate and effective.
Should be noted that at last that obviously those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification.
Claims (5)
1. the screening technique of a frequency of processor chip is characterized in that, may further comprise the steps:
Step S001 obtains being used to carry out the instruction level function testing vector of frequency screening according to the optimization of physics critical path coverage rate;
Step S002 writes said processor chips high-speed cache through scan chain device with the said instruction level function testing vector that is used for frequency screening;
Step S003 is said processor chip configuration phase-locked loop high-frequency clock on Automatic Test Equipment, and the instruction level function testing vector of carrying out in the said high-speed cache is carried out frequency screening, evaluates the frequency class of said processor chips;
Step S004 through andante level functional test that said processor chips sampling is gone forward side by side, obtains frequency departure, proofreaies and correct and demarcate the final frequency of said processor chips.
2. the screening technique of chip frequency as claimed in claim 1 is characterized in that, among the said step S001, obtains instruction level function testing vector according to the optimization of physics critical path coverage rate, may further comprise the steps:
Step S101, processor chips get into normal mode of operation, normal instruction level function testing vector are write in the high-speed cache of said processor chips;
Step S102 carries out the instruction level function testing vector in the chip high speed buffer memory, and assessment physics critical path coverage rate;
Step S103, whether the path coverage rate that detects this test meets the demands: if the path coverage rate is too low, do not reach requirement, then get into step S104; If the path coverage rate meets the demands, then get into step S105;
Step S104, the adjustment instruction level function testing vector, and get into step S102;
Step S105, the instruction level function testing vector that is used to carry out frequency screening after being optimized, optimization finishes.
3. the screening technique of chip frequency as claimed in claim 1 is characterized in that, among the said step S002, through scan chain device said instruction level function testing vector is write in the said processor chips high-speed cache, comprises the steps:
Step S201, the access instruction of write cache in the scan chain of said processor chips;
Step S202 judges the operational attribute that cache access instructs: if present instruction is that write operation then gets into step S203; If present instruction is that read operation then gets into S204;
Step S203 carries out write operation to storer, gets into step S205;
Step S204 carries out read operation to storer, gets into step S205;
Step S205 also need to judge whether access cache: if also need visit, then get into step S201; If no longer need visit, then accomplish.
4. the screening technique of chip frequency as claimed in claim 1; It is characterized in that; In said step S003, on Automatic Test Equipment said processor chip configuration phase-locked loop high-frequency clock, carry out the instruction level function testing vector of said high-speed cache and carry out frequency screening; Evaluate the frequency class of said processor chips, may further comprise the steps:
Step S301 resets said processor chips;
Step S302 according to the processor frequencies class of estimating, disposes and starts the phase-locked loop high-frequency clock of said processor chips, and gets into step S303;
Step S303, said processor chips set;
Step S304 disposes said processor chips internal control trigger;
Step S305, the instruction level function testing vector of carrying out in the chip high speed memory buffer is carried out frequency screening;
Step S306, judge test result: normal if test result shows, then get into step S307; Make mistakes if test result shows, then change the processor frequencies class of estimating, get into step S302 and proceed screening;
Step S307, class under the record chip frequency.
5. the screening technique of chip frequency as claimed in claim 1 is characterized in that, in said step S004; Through andante level functional test that said processor chips sampling is gone forward side by side; Obtain frequency departure, proofread and correct and demarcate the final frequency of said processor chips, may further comprise the steps:
Step S401 randomly draws the said processor chips after step S003 instruction level function testing of some;
Step S402 places the said processor chips of step S401 on the functional test plate of customization;
Step S403 disposes the current running frequency of said processor chips;
Step S404, operation function test and faults: if mistake occurs, then get into step S403, reconfigure new one grade running frequency, proceed functional test; If do not make mistakes, then get into step S405;
Step S405 demarcates chip board level test frequency;
All whether step S406, sampling chip test finish, if the chip of sampling in addition needs test, then get into step S402; If all sampling chips are all tested finish, then get into step S407;
Step S407, according to plate level chip testing frequency, calculated rate is proofreaied and correct mean value;
Step S408 according to frequency correction mean value, proofreaies and correct the frequency class numerical value of the said processor chips of step S003 evaluation, obtains the final frequency result of said frequency of processor chip screening.
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