CN101826514A - Compact type electric inductance power electronic device encapsulation - Google Patents
Compact type electric inductance power electronic device encapsulation Download PDFInfo
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- CN101826514A CN101826514A CN200910202889A CN200910202889A CN101826514A CN 101826514 A CN101826514 A CN 101826514A CN 200910202889 A CN200910202889 A CN 200910202889A CN 200910202889 A CN200910202889 A CN 200910202889A CN 101826514 A CN101826514 A CN 101826514A
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
The invention discloses a compact type electric inductance power electronic device encapsulation, which comprises one circuit substrate on which a power electric inductance is adhered. The power electric inductance comprises an electric inductance chip which has a closed magnet circuit and is provided with a window in the center. The closed magnet circuit can include air gaps for adjusting the electric inductance induction coefficient. The circuit substrate includes bottom semi-coil elements positioned below the electric inductance chip to compose a bottom semi-coil. The top semi-coil elements are connected with the bottom semi-coil elements to compose an electric inductance coil surrounding the electric inductance chip. Internal interconnect chips can be added in an internal window of the electric inductance chip for connecting the bottom semi-coil elements and the top semi-coil elements. External interconnect chips can be likewise added outside the electric inductance chips for connecting the bottom semi-coil elements and the top semi-coil elements positioned outside the electric inductance chips. One power integrated circuit is likewise adhered above the circuit substrate.
Description
Technical field
The present invention relates generally to the electronic system encapsulation field, more specifically, the physical level encapsulation that the present invention carries out with semiconductor chip corresponding to separate type power inductance (or power inductance).
Background technology
Because the market demand of sustainable development, when obtaining higher power stage, power semiconductor package constantly tend to smaller szie and (or) littler pin.A kind of common power semiconductor package that is applied to multiple transducer (boost and step-down controller etc.), this encapsulation relates to the encapsulation of inductance component and semiconductor integrated circuit (IC) chip, exists in the existing a large amount of prior aries of association area.One of them prior art is called " microminiature power converter " (United States Patent (USP) 6,930,584), waits people's invention by dust more, obtains the authorization on August 16th, 2005, hereinafter to be referred as " the many patents of dust ".Fig. 1 and Fig. 2 have illustrated the many patents of dust.Figure 1 shows that a thin film inductor.Thin film inductor 1 comprises a Chiral Materials of Ferrite Substrate 7, and its part is surrounded by a large amount of electromagnet coil conductors.Chiral Materials of Ferrite Substrate 7 is electrical insulators.As shown in Figure 1, the first of electromagnet coil conductor comprises the some top winding conductors 4 that are formed on Chiral Materials of Ferrite Substrate 7 top major surface, and the second portion of electromagnet coil conductor comprises some bottom coil conductors 5 that are formed on the Chiral Materials of Ferrite Substrate 7 bottom primary flats.A large amount of bonding conductors 3 are formed in the middle of the hole that passes Chiral Materials of Ferrite Substrate 7, are used for connecting the first 4 and the second portion 5 of electromagnet coil conductor, thereby have formed with the solenoid type inductance of Chiral Materials of Ferrite Substrate 7 as its inductance sense core.Extra perforation 6c forms and along the peripheral metalization of Chiral Materials of Ferrite Substrate 7, top electrodes 6a and bottom electrode 6b is coupled together, and is used for constituting the external contact of thin film inductor, and allows the signal of telecommunication to pass Chiral Materials of Ferrite Substrate 7.Fig. 2 is a cross sectional representation with the microminiature power converter of chip size modular form encapsulation.This chip size module comprises a semiconducter IC (integrated circuit) 8, and described semiconducter IC 8 is bonded to the top of thin film inductor 1 as shown in Figure 1 by the some stud bumps 9 on the electrode on the semiconductor integrated circuit (clearly not drawing) and some top electrodes 6a that is positioned on the thin film inductor.The cross section of thin film inductor 1 part of chip size module is that the X-X axle intercepts in Fig. 1.One bottom filler (not shown) also is applied between thin film inductor 1 and the semiconducter IC 8, thereby the chip size module is carried out passivation.It should be noted that because the Chiral Materials of Ferrite Substrate 7 on the thin film inductor 1 has by center and periphery perforation 3,6c, the three-dimensional feature that electromagnet coil conductor 4,5 and electrode 6a, 6b are constituted, complex structure, thus processing cost is high.Another shortcoming is that this fragile ferrite chip is directly exposed, and the outside is without any protection.
Another prior art is that title is the United States Patent (USP) of " lead frame that includes inductance or other similar magnetic elements ", the patent No. 5,428,245, and the inventor is people such as Lin, obtains the authorization June 27 nineteen ninety-five, hereinafter to be referred as " Lin patent ".Fig. 3 has briefly described the Lin patent.A kind of lead frame with a large amount of conductive lead wires is applied in the integrated circuit encapsulation shown in the figure.This lead frame also comprises the center integration first inductance winding.Other coil windings also can become an integration part of lead frame, and they are enclosed in elementary winding outside, form the magnetic element winding of a multilayer with this.In the middle of an embodiment, be coated with the last layer magnetic material outside the winding based on lead frame, formed inductance based on lead frame.Although it should be noted that the lead frame inductance winding of being announced can be used as the signal inductance and uses, under the situation that does not have actual core material, perhaps can't the satisfy the demand power application of high inductance value and low winding resistance of this lead frame inductance.
Therefore, the present invention desired target that reaches is a kind of compactness, the electric inductance power electronic device encapsulation that is easy to make, and this encapsulation can provide high inductance grade, comprises inductance value and saturation current.
Summary of the invention
The invention discloses a kind of electric inductance power electronic device encapsulation of compactness, this encapsulation has high inductance grade, and it comprises:
A circuitry substrate.
A power inductance is attached on the circuitry substrate.This power inductance has the inductance sense core of the closed magnet circuit that an inside has window.At one more specifically in the middle of the embodiment, inductance sense core is an annular.As a selection, this inductance sense core also can include an air gap, so that when keeping closed magnet circuit, can regulate induction coefficient.
This circuitry substrate comprises the composed component of a large amount of bottom half coils, constitutes the bottom half coil that is positioned at inductance sense core below.
A large amount of tops half coil element links to each other with bottom half coil element, has formed the complete inductance coil that is enclosed in outside the inductance sense core jointly.
In the middle of a relevant embodiment, the top half coil forms element and can be connected with the adjacent bottom half coil formation component terminals that is positioned at outside the inductance sense core being exposed to the central bottom half coil formation component terminals of inductance sense in-core portion window, forms whole inductance coil with this.In other words, one end of the composed component of each top half coil can link to each other with an end of the bottom half coil composed component of inner window inside, the other end links to each other with the adjacent bottom half coil composed component of inductance sense core outside, forms the inductance coil that is looped around outside the inductance sense core with this.Terminals of most of bottoms half coil composed component are positioned in the middle of the inductance sense in-core portion window, and another terminals are positioned at inductance sense core outside.
In the middle of a relevant embodiment, the inner chip that connects is added in the central window of inductance sense core, is used for connecting in inner window top half coil and bottom half coil composed component.In the middle of another related embodiment, add one and be looped around inductance sense core outside connection chip all around, be used for outside inductance sense core, connecting top half coil and bottom half coil composed component.
A power integrated circuit (IC) can make an addition in the middle of this encapsulation, and interconnects with power inductance.At one more specifically in the middle of the embodiment, Power IC is attached to the top of circuitry substrate, is used to connect Power IC and power inductance by the circuit interconnection device that circuitry substrate provided in addition.Power IC can be arranged at inductance sense core top or next door.Power IC even can be arranged in the window in the middle of the inductance sense core, in order to save the pin and the thickness of encapsulation.Power IC comprises that a power transistor and one are used for this transistorized control IC of control.
Circuitry substrate promptly is a lead frame more specifically in the middle of the embodiment at one, and bottom half coil element is a large amount of leadframe leads, and constitutes the bottom half coil thus.Top half coil element can be used as a large amount of top lead frameworks lead-in wire, and these lead-in wires that are looped around inductance sense core top further link to each other with specific bottom lead framework lead-in wire, and have constituted inductance coil.Select as second, top half coil element also can be a large amount of top key zygonemas, and every bonding line is looped around on the inductance sense core, further link to each other with specific bottom lead framework lead-in wire, and the formation inductance coil.Select as the 3rd, top half coil element can be made of 3 D stereo top interconnect plate, and every interconnection plate is looped around on the inductance sense core, further link to each other with specific bottom lead framework lead-in wire, and the formation inductance coil.
More specifically in the middle of the embodiment, circuitry substrate is a multilayer circuit board (MCL) at another, and for example printed circuit board (PCB) (PCB) has a top conductive line layer, and wherein a large amount of half coil pattern conductive circuits has constituted bottom half coil element.
Correspondingly, be similar to the embodiment of leadframe substrate, top half coil element can be a large amount of leadframe leads, bonding line or 3 D stereo interconnection plate.Perhaps, the MCL plate also can be bismaleimides-cyanate resin (BT) substrate.
It is evident that for those skilled in the art top half coil element can be made (for example bonding line, top lead framework, interconnection plate) by any conductor material, and is connected to specific bottom half coil element.Equally, the circuitry substrate that contains bottom half coil element can be made of any suitable material, lead frame for example, PCB or BT resin substrates.
A kind of method of making above-mentioned electric inductance power electronic device encapsulation, this method comprises:
A circuitry substrate is provided, contains a large amount of bottoms half coil element on it;
On circuitry substrate, adhere to a power inductance by the following method:
● an inductance sense core with closed magnet circuit is set on the half coil element of bottom, and there is a window in these sense core central authorities.
● adhere to a large amount of top half coil elements, make them link to each other, can form the inductance coil that inductance sense core is surrounded jointly like this with bottom half coil element.
As extra a selection, can on circuitry substrate, adhere to a Power IC.
Additionally select as another one, electric inductance power electronic device can be encapsulated the top and encapsulate, comprise that sense core and top half coil form element and encapsulate.
The method of adhering to a large amount of tops half coil composed component comprises, each top half coil element is linked to each other with an adjacent bottom half coil component terminals that is positioned at outside the inductance sense core with terminals that are positioned at the bottom half coil element of window.
These characteristics of the present invention and relevant embodiment are further described by of the present invention, for those those skilled in the art, will be more clear and clear and definite.
Description of drawings
For more complete description a large amount of embodiment of the present invention, the spy provides accompanying drawing with for referencial use.Yet these accompanying drawings should not be considered to the restriction on scope to the present invention, and only are indicative explainations.
Fig. 1 and Fig. 2 are a kind of microminiature transducers of prior art, and this transducer has used a kind of electromagnet coil thin film inductor;
Fig. 3 shows a kind of planar coil inductance based on the prior art lead frame;
Fig. 4 to Fig. 8 takes passages from U.S. Patent application 12/011,489;
Fig. 9 to Figure 10 takes passages from U.S. Patent application 11/986,673;
Figure 11 to Figure 16 has illustrated first kind of embodiment of compact type electric inductance power electronic device encapsulation provided by the invention, and this wrapper contains a closed magnet circuit power inductance and is positioned at a Power IC chip on 2 layers of pcb board; And
Figure 17 has illustrated second kind of embodiment of compact type electric inductance power electronic device encapsulation provided by the invention, and this wrapper contains one and is positioned at closed magnet circuit power inductance on the lead frame.
Figure 18 to Figure 21 illustrated the another kind of embodiment of compact type electric inductance power electronic device provided by the invention encapsulation, and this wrapper contains a separate type, has closed magnet circuit, and is positioned at a power inductance on the pcb board.
Figure 22 to Figure 24 has illustrated the another kind of embodiment of compact type electric inductance power electronic device encapsulation provided by the invention, this wrapper contains a separate type, has closed magnet circuit, and be positioned at a power inductance on the lead frame, and adopted interconnection plate to form element as the top half coil.
Embodiment
More than and following description content to accompanying drawing, at this only at the current mentioned embodiment of one or several the present invention, and also described simultaneously some representational have optional feature and (or) alternative embodiment.These are described and accompanying drawing is to provide to be illustrated as order, and itself should not be considered to limitation of the present invention.Therefore, those skilled in the art can be easy to recognize their modification, modification or substitute.These modification, modification and alternative being appreciated that within the scope that still is included in claims of the present invention.
For the ease of understanding and understanding the present invention, the whole accompanying drawings of Fig. 4 to Fig. 8 comprise that U.S. Patent application 12/011,489 is selected from their explanation and through renumbeing, it thes contents are as follows:
Fig. 4 is the vertical view of an embodiment of the separate type power inductance based on lead frame of the present invention.Fig. 5 is the vertical view of top lead framework of the present invention.Fig. 6 is a power inductance side-looking schematic diagram shown in Fig. 4 works as.Fig. 7 is the vertical view of interconnect die of the present invention.Fig. 8 is the cutaway view of interconnect die shown in Fig. 7 works as.
As shown in Figure 4, in the middle of an embodiment, be numbered 300 based on the separate type power inductance of lead frame, wherein the part of bottom lead framework 260 lead-in wire shows with dotted line in the drawings.Power inductance 300 comprises 260, one top lead frameworks 320 of smooth bottom lead framework, interconnected lead-in wire around magnetic core 110.Interconnect die 330 is arranged on (as shown in Figure 6) in the middle of the window 115, makes top interior contact region and bottom lead framework be connected to become possibility between going between.
With reference to Fig. 5, top lead framework 320 comprises first group of lead-in wire 320a, 320b and 320c on first side that is arranged on top lead framework 320. Top lead 320a, 320b and 320c have a nonlinear step-like structure, so that connect the lead-in wire of bottom lead framework 260, are used for constituting the complete coil that is described after a while.Top lead 320a, 320b and 320c comprise and are separately positioned on top lead 320a, 320b and 320c along zone 321a, 321b of the inner contact on the A-A gained cross section and 321c. Top lead 320a, 320b and 320c also comprise and are separately positioned on top lead 320a, 320b and 320c along zone 323a, 323b of the external contact on B-B (under the A-A plane, being parallel to the A-A plane) the gained cross section and 323c.
As Fig. 7 and Fig. 8 when as shown in interconnect die 330 comprise 6 conduction perforation 330a, 330b, 330c, 330d, 330e and 330f (shown in dotted line in the middle of Fig. 4), connection between the inner contact zone that is used to provide top lead framework 320 and bottom lead framework 260 lead-in wires is also set in described perforation space.Soldering projection 340 two surfaces up and down that are formed on interconnected chip 330 preferably are so that connect.
Be looped around around the magnetic core 110 coil as Fig. 4 when as shown in.Lead-in wire inner contact zone 260a, 260b, 260c, 260d, 260f and the 260g of bottom lead framework 260 is coupled to inner contact zone 321a, 321b, 321c, 321d, 321e and the 321f of top lead framework 320 respectively by interconnect die 330.Lead-in wire external contact zone 260b, 260c, 260d, 260e, 260f and the 260g of bottom lead framework 260 is looped around external contact zone 323a, 323b, 323c, 323d, 323e and the 323f coupling at magnetic core 110 edges respectively with top lead framework 320.
The inner contact zone 261a of lead-in wire 260a is coupled to the inner contact zone 321a of lead-in wire 320a by perforation 330a.The external contact zone 263b coupling of the external contact zone 323a of lead-in wire 320a and adjacent legs 260b.The inner contact zone 321b of the inner contact zone 261b of lead-in wire 260b and lead-in wire 320b is coupled by perforation 330b.The external contact zone 263c coupling of the external contact zone 323b of lead-in wire 320b and adjacent legs 260c.The inner contact zone 261c of lead-in wire 260c is by the inner contact zone 321c coupling of perforation 330c with lead-in wire 320c.The external contact zone 263d coupling of the external contact zone 322c of lead-in wire 320c and adjacent legs 260d.The inner contact zone 321f of the inner contact zone 261d of lead-in wire 260d and lead-in wire 320f is coupled by perforation 330f.The external contact zone 263g coupling of the external contact zone 323f of lead-in wire 320f and adjacent legs 260g.The inner contact zone 261g of lead-in wire 260g is by the inner contact zone 321e coupling of perforation 330e with lead-in wire 320e.The external contact zone 263f coupling of the external contact zone 323e of lead-in wire 320e and adjacent legs 260f.The inner contact zone 261f of lead-in wire 260f is by the inner contact zone 321d coupling of perforation 330d with lead-in wire 320d.The external contact zone 263e coupling of the external contact zone 323d of lead-in wire 320d and adjacent legs 260e.As first and second embodiment when described in, the nonlinear step-like structure of top and bottom lead framework lead-in wire is aimed at and at interval for inside and outside contact region provides.
Separate type power inductance 300 comprises binding post 260a and 260e, by the connection of interconnect die 330, has constituted the complete coil that is looped around outside the magnetic core 110 between top and bottom lead framework 320 and 260 lead-in wires.
After separate type power inductance 300 uses encapsulant to encapsulate, form the encapsulation (not shown).Encapsulant comprises conventional encapsulating material.As one of selection, encapsulant also comprises the material that is added with magnetic, and for example ferrite particle provides shielding and improves magnetic with this.
At Fig. 4 (based on separate type power inductance 300 of lead frame) to the embodiment shown in Figure 8, the circuitry substrate that includes bottom half coil element is a bottom lead framework 260.Top half coil element is a top lead framework 320.The inductance sense core that inside has window is the magnetic core 110 with window 115.Interconnect package 330 in the window 115 make between top half coil element 320 and the bottom half coil element 260 be connected more convenient.Power inductance 300 is a discrete component, and it is not packaged together with Power IC.
For the ease of understanding and understanding the present invention, U.S. Patent application 11/986,673 is selected from Fig. 9 to Figure 10 and explanation thereof, and through renumbeing, it thes contents are as follows:
Fig. 9 is the vertical view of the embodiment of another semiconductor power device encapsulation of the present invention, and this semiconductor packages comprises an integrated inductor based on lead frame.Figure 10 is the vertical view of the 6th embodiment bottom of a kind of semiconductor power device encapsulation of the present invention, and this semiconductor packages comprises an integrated inductor based on lead frame.
An embodiment of described invention as shown in Figure 9, it comprises semiconductor power device encapsulation 1900, this encapsulation comprises an integrated inductor 1950 based on lead frame.This inductance 1950 is by ferrite sheet 1800, and a plurality of adjacent legs on the lead frame 100 and bonding line 1920e, 1920f, 1920i, 1920j, 1920k and 1920m form.Connecting chip 500 provides conduction to connect by the perforation 510a to 510f that forms thereon.On the upper surface 150 of ferrite sheet 1800 attached to lead frame 100, and by big liner 120 and 130 supports of little liner.Ferrite sheet 1800 is arranged on lead frame 100 upper surfaces 150, makes that lead end 140d to 140f is easy to be connected with 140j to 140m by window 1810.A Power IC 1930 also is easy to connect by window 1810.
The size and the structure that connect chip 500 are suitable for being contained in the window 1810.Perforation 510a to 510f forms and is positioned at and connects in the encapsulation 500, and they cover on the lead end 140d to 140f and 140j to 140m of the lead frame 100 with conductive epoxy resin or welding compound like this, and are electrically connected with it.Power IC 1930 is arranged on the next door that connects chip 500 in the window 1810.
Bonding line is with the adjacent legs coupling of lead frame 100, and forming with ferrite sheet 1800 is a closed magnetic circuit of magnetic core.Bonding line 1920e is coupled by will a go between end 140d and the adjacent legs 110e of 110d of perforation 510a, and bonding line 1920e and adjacent legs 110d and 110e together constitute and be looped around ferrite sheet 1800 loop outward.Bonding line 1920f is coupled by will a go between end 140e and the adjacent legs 110f of 110e of perforation 510b, and bonding line 1920f and adjacent legs 110e and 110f together constitute and be looped around ferrite sheet 1800 loop outward.Bonding line 1920m is coupled by will a go between end 140f and the adjacent legs 110m of 110f of perforation 510c, and bonding line 1920m and adjacent legs 110f and 110m together constitute and be looped around ferrite sheet 1800 loop outward.Bonding line 1920k is coupled by will a go between end 140m and the adjacent legs 110k of 110m of perforation 510f, and bonding line 1920k and adjacent legs 110m and 110k together constitute and be looped around ferrite sheet 1800 loop outward.Bonding line is coupled with adjacent legs 110j by will the go between end 140k of 110k of perforation 510e 1920j, and bonding line 1920j and adjacent legs 110k and 110j together constitute and be looped around ferrite sheet 1800 loop outward.Bonding line is coupled with adjacent legs 110i by will the go between end 140j of 110j of perforation 510d 1920i, and bonding line 1920i and adjacent legs 110j and 110i together constitute and be looped around ferrite sheet 1800 loop outward.Lead-in wire 110d and 110i have formed the lead-in wire of inductance 1950.
Power IC 1930 is attached on the big liner 120 of lead frame 100.Bonding line 1920d is Power IC 1930 and lead-in wire 110d coupling, thus with integrated inductor 1950 couplings based on lead frame.Bonding line 1920a, 1920b and 1920c are coupled Power IC 1930 respectively with lead-in wire 110a, 110b and 110c.Bonding line 1920g and 1920h are coupled Power IC 1930 respectively with lead-in wire 110g and 110h.
Owing to connect the application of chip 500, no longer need use special bonding tool (K﹠amp for example; SClose Center Bond bottleneck bonding tool), the bonding tool of a standard just can meet the demands.
A kind of encapsulant is used to finish semiconductor power device encapsulation 1900, and this kind encapsulant is filled in the half-etched regions of lead-in wire 110a to 110m, and in order to anchor leg framework 100, so lead-in wire just unlikely separates with encapsulation.The exterior contour of encapsulant is illustrated by the broken lines in the drawings.
In the middle of Fig. 9 and embodiment shown in Figure 10 (semiconductor power device encapsulation 1900), the circuitry substrate that contains bottom half coil element is lead frame 100.The top half coil forms element and is bonding line 1920d to 1920f and 1920i to 1920m.Inductance sense core is the ferrite sheet 1800 with window 1810.This semiconductor power device encapsulation 1900 comprises and being arranged within the window 1810, connects the Power IC 1930 on chip 500 next doors.
Figure 11 to Figure 16 has illustrated compact type electric inductance power electronic device encapsulation 300 of the present invention, comprises a power inductance 12 and a Power IC chip 11, and the two all is positioned on the MCL plate (in the middle of the present embodiment being 2 layers of pcb board 61).Power inductance 12 has a straight-flanked ring ferrite sheet 15 with closed magnet circuit as inductance sense core, and its central authorities have window 16.It will be apparent to one skilled in the art that, in order to realize having the higher induction coefficient of compact inductive size, ferrite sheet 15 is made closed loop shape so that most of magnetic flux is constrained in wherein, and this point is very important, and it is less important that the concrete shape of this closed loop then shows slightly.Therefore, for example, this closed loop shape can have following selection, and is square, and polygon is oval or circular.But, it has been generally acknowledged that circle can provide the magnetic confinement of peak efficiency.The path of closed magnet circuit is around inner window 16.These 2 layers of pcb boards 61 have 62, one bottom conductive line layers of a top conductive line layer 64 and make two conducting wire layers 62 and 64 intermediate insulating layers 65 insulated from each other.Figure 11 is the vertical view of this electric inductance power electronic device encapsulation 300, and in order to observe internal components more clearly, encapsulant is removed.Figure 12 and Figure 13 are the top section and the side cross-sectional view of ferrite sheet 15, and this ferrite 15 is a part of power inductance 12.Figure 14 is the vertical view of Power IC chip 11, and this chip has some contact pad designed 11g of IC that are positioned at its top.Figure 15 is the vertical view of top conductive line layer 62.Figure 16 is the upward view of bottom conductive line layer 64.
Next, top conductive line layer 62 comprises first group of half coil pattern conductive circuit 62a to 62d that is arranged on inductance sense core (ferrite sheet 15) below, 62f and 62A to 62D.In fact, 62a to 62d, 62f and 62A to 62D have together formed the bottom half coil of power inductance 12.Correspondingly, second group of top half coil bonding line 19a to 192d and 19A to 19D are positioned on the ferrite sheet 15, every bonding line from the top around ferrite sheet 15.And the two ends of each bar top half coil bonding line all link to each other with relative bottom half coil conducting wire, have together constituted the induction coil that ferrite sheet 15 is surrounded wherein.So, for example, the end of top half coil bonding line 19a and the half coil conducting wire 62a bonding that is positioned at ferrite sheet 15 outsides, the other end and the adjacent half coil conducting wire 62b bonding that is positioned at ferrite sheet 15 inner window 16 inside.The two ends of top half coil bonding line 19b are also with similarly mode and half coil conducting wire 62b and 62c bonding.The two ends of top half coil bonding line 19c also respectively with half coil conducting wire 62c and 62d bonding ... or the like.Finally, the two ends of top half coil bonding line 19D respectively with half coil conducting wire 62D and 62f bonding.The result is, the half coil conducting wire 62f of top conductive line layer 62 and 62a become two device binding posts of power inductance 12, be used for being connected, for instance, carry out circuit with Power IC chip 11 by other bonding line and be connected with other devices of induced power device package 300.Other bond pads 63a to 63e of top conductive line layer 62 (being bonded to the contact pad designed 11g of IC of Power IC chip 11) can be used for being connected with induced power device package 300 outsides by through hole 65a (can be described after a while).Although fail to mention for fear of excessive description details, accurately to adjust for the ease of induction coefficient power inductance 12, ferrite sheet 15 can leave one or more air gap during fabrication along the magnet ring direction.
Though the bottom conductive line layer 64 of pcb board 61 and top conductive line layer 62 can utilize various conducting wire geometric figure to add many conductive interconnection through holes that pass insulating barrier 65 by patterning independently, leave a large amount of bottom conductive circuit 64a to 64g and a large amount of conduction perforation 65a as shown in the figure on the bottom conductive line layer 64.Correspondingly, top conductive line layer 62 also includes a large amount of conductions perforation 65a, and corresponding one by one with conduction punch position on bottom conductive line layer 64.This allows bottom conductive circuit 64a-g to carry out the outside connection, and their are connected with each other simultaneously and between top conductive circuit 63a-e on the other side and 62a and the 62f (bottom conductive circuit 64f and 64g link to each other with half coil conducting wire 62f and 62a respectively).The special case of a bottom conductive circuit 64a is that the bottom ground plane 64m of expansion is used to carry out carry out signal shielding and carry out heat conduction at EMI/RFI (electromagnetic interference/radio frequency interference) usually.At one more specifically in the middle of the embodiment, pcb board 61 is made by the MCL plate of bismaleimides-cyanate resin (BT) substrate or other types.When shown in Power IC chip 11 next-door neighbour ferrite sheets 15 place, under the suitable situation of the relative dimensions of Power IC chip 11, ferrite sheet 15 and the inner window on it 16, Power IC chip 11 can be positioned within the inner window 16, and inner bottom part half coil conducting wire can be connected in window with top half coil bonding line like this.If desired, this Power IC chip 11 even can be placed on the ferrite sheet 15 can further reduce the pin area of electric inductance power electronic device encapsulation 300 like this on the basis that increases package thickness.This Power IC chip 11 comprises a power transistor and the control circuit that is used for controlling this power transistor that integrates.
In the middle of compact type electric inductance power electronic device encapsulation 300, circuitry substrate is a pcb board 61, and bottom half coil element is half coil conducting wire 62a to 62d, 62f and 62A to 62D.Now, clearly, generally speaking a pcb board or the MLC plate more than 2 layers can be applied to the compact type electric inductance power electronic device encapsulation, and the corresponding flexibility that increases encapsulation.In fact, pcb board 61 can be substituted the bottom lead framework shown in for example Fig. 4 to Fig. 5, and Fig. 9 to Figure 10 works as by any circuitry substrate that includes suitable bottom half coil element.Top half coil element is a bonding line 19.Bonding line 19 can be replaced top lead frame frame or interconnection plate shown in for example Fig. 4 to Fig. 6 works as by any suitable top half coil element.The electric inductance power electronic device encapsulation comprises a separate type power inductance, and is extremely shown in Figure 6 as Fig. 4; Perhaps comprise a power inductance that is packaged together with Power IC, as shown in figure 11.As Figure 11 to Figure 24 when as shown in, more embodiment has proved absolutely the flexibility of the present invention's design.
Figure 17 has illustrated second embodiment of this compact type electric inductance power electronic device encapsulation 350, and the power inductance 12 that wherein has closed magnet circuit is positioned on the lead frame.See through encapsulant 101, each part shows with dotted line in the drawings.Similar with Figure 11, power inductance 12 has the inside of a rectangle to have the ferrite sheet 15 of window 16 as the sense core.Lead frame comprises some and is positioned at bottom half coil lead 17a to 17g under the ferrite sheet 15.In fact, bottom half coil lead 17a to 17g has constituted the bottom half coil of power inductance 12 jointly.Relatively, other tops half coil bonding line 19a to 19f is positioned on the ferrite sheet 15, and each bar bonding line is all walked around from ferrite sheet 15.And the two ends of every top half coil lead all are connected with specific adjacent base half coil lead, have constituted the inductance coil around ferrite sheet 15 jointly.For example, the two ends of top half coil bonding line 19a respectively with bottom half coil lead 17a and 17b bonding mutually.The two ends of top half coil bonding line 19b respectively with bottom half coil lead 17b and 17c bonding mutually.The two ends of top half coil bonding line 19c respectively with bottom half coil lead 17c and 17d bonding mutually ... or the like.At last, the two ends of top half coil bonding line 19f respectively with bottom half coil lead 17f and 17g bonding mutually.As a result, lead frame bottom half coil lead 17a and 17g become two device binding posts of power inductance 12, are used for encapsulating 350 outsides with electric inductance power electronic device and are connected.
Figure 18 to Figure 21 has illustrated another embodiment of separate type power inductance 70, and except the bottom lead framework being changed to (for example 2 layers of pcb board 71) the MCL plate, remainder is all similar to previous embodiment.These 2 layers of pcb boards 71 comprise 72, one bottom conductive line layers 74 of a top conductive line layer and the insulating barrier 75 between the two, are used for two conducting wire layers 72 and 74 insulated from each other.Figure 18 is the cross-sectional side view of this separate type power inductance 70.Figure 19 is the vertical view of top conductive line layer 72.Figure 20 is the upward view of pcb board 71, has demonstrated bottom conductive line layer 74.Figure 21 is the vertical view of this separate type power inductance 70, and in order to observe internal components more clearly, encapsulant 101 has been removed.Half coil conducting wire 72a to 72g in the middle of the top conductive line layer 72 will be patterned, and play with Figure 11 to Figure 14 in the middle of half coil conducting wire 62a-62d, the function that 62f and 62A-62D are similar.
The bottom conductive line layer 74 of pcb board 71 and top conductive line layer 72 can utilize various conducting wire geometric figure, add many conductive interconnection through holes that pass insulating barrier 75 by patterning independently, as shown in the figure, leave a large amount of bottom conductive circuit 74a-74c and 74f-74g on the bottom conductive line layer 74, add conduction perforation 75a and 75b.Conduction perforation 75a and 75b are connected to the bottom of pcb board 71 (circuit 74f and 74g) with inductance ( circuit 72f and 72g), with regard to permission inductance are connected with the outside like this.
Figure 18 to Figure 21 (separate type power inductance 70) when shown in embodiment in, the circuitry substrate that contains bottom half coil element is the pcb board 71 that comprises top conductive line layer 72.Top half coil element is bonding line 79a to 79f.Inductance sense core 15 (normally ferrite sheet) has a window 16.
Figure 22 to Figure 24 has illustrated another embodiment of separate type power inductance 40, and wherein power inductance 40 has used a large amount of peripheral frame projections (for example being positioned at the 43b and the 43c of lead frame 41 bottoms) and position top half coil interconnection plate (42a to 42h) thereon.Figure 22 has removed encapsulant 101 vertical view afterwards in order to observe internal components more clearly.Figure 23 is lead frame 41 vertical view alone.Figure 24 is the end view of separate type power inductance 40.Different with use bonding line in the middle of Figure 11, a large amount of three-dimensional top half coil interconnection plate 42a to 42h (each piece all also further is connected on the specific bottom half coil conductive lead wire 41a to 41j around inductance sense core 15 tops) are used to constitute inductance coil.For example, the two ends of top half coil interconnection plate 42a respectively with bottom half coil conductive lead wire 41a and 41b bonding.The two ends of top half coil interconnection plate 42b respectively with bottom half coil conductive lead wire 41b and 41c bonding.The two ends of top half coil interconnection plate 42c respectively with bottom half coil conductive lead wire 41c and 41d bonding ... or the like.At last, the two ends of top half coil interconnection plate 42h respectively with bottom half coil conductive lead wire 41h and 41i bonding.As a result, bottom half coil conductive lead wire 41a and 41i just become power inductance be used for carry out two device binding posts that circuit is connected with outside.Compare with bonding line, the advantage of the inductance coil that is made of top half coil interconnection plate is to have lower coil resistance.
Plurality of peripheral support projection 43b and 43c are attached to the bottom of bottom half coil conductive lead wire 41d and 41f.In order to obtain stability, have three peripheral frame projections at least, be connected although only need wherein two to constitute with the conduction of inductance.
Generally speaking, encapsulant can all surround the top of inductance encapsulation, comprises that inductance sense core and top half coil form element.Encapsulant plays the effect of protection and its embracing element of electrical isolation.When frangible ferrite sheet was used as inductance sense core and uses, when bonding line or interconnection plate were used as top half coil element, this characteristic was very favourable.For example, encapsulant can be the moulding compound of standard.At one more specifically in the middle of the embodiment, encapsulant contains embedded magnetic particle, is used for improving the inductance value of power inductance.
It will be apparent to one skilled in the art that, a large amount of top half coil bonding line 19a to 19f can replace with top lead framework lead-in wire, these lead-in wires also further link to each other with the specific bottom half coil conductive lead wire 17a to 17g of below from the top around ferrite sheet 15, and have constituted inductance coil thus.Select as another one, top half coil bonding line 19a to 19f can replace with three-dimensional top interconnection plate, these interconnection plates link to each other from the top around ferrite sheet 15 and the further bottom half coil conductive lead wire 17a to 17g that connects, and have constituted inductance coil thus equally.Compare with using bonding line, the advantage of the inductance coil that is made of the top interconnect plate is to have lower coil resistance.
Referring again to Figure 11 to Figure 16, a corresponding method of making electric inductance power electronic device encapsulation 300 should comprise:
A pcb board 61 is provided, and the conducting wire that a large amount of half coil patternings are arranged on it is 62a to 62D for example.
By ferrite sheet 15 being arranged on the conducting wire of half coil patterning, power inductance 12 is sticked on the pcb board 61.As additional a selection, Power IC chip 11 also can be sticked on the pcb board 61.
Adhere to a large amount of tops half coil bonding line again, for example 19a to 19D makes them be connected with a large amount of half coil pattern conductive circuits of below, and constitutes an inductance coil around ferrite sheet 15 jointly.
At one more specifically in the middle of the embodiment, the method of pasting the top half coil further comprises: an end that each top half coil is formed element links to each other with the end that a bottom half coil that is positioned within the inner window forms element, and the other end that the top half coil is formed element links to each other with a end of adjacent bottom half coil formation element outside being positioned at ferrite sheet.
This aspect further comprises a step that the top of electric inductance power electronic device encapsulation is encapsulated with encapsulant.
Up till now, it will be apparent to one skilled in the art that clearly that above-mentioned a large amount of embodiment also can be easy to be carried out improvement, with the application that is applicable to that other are specific.Describe although comprised a lot of concrete properties in the middle of the foregoing description, these characteristics should not be regarded as the restriction to interest field of the present invention, and only are some examples in the middle of a large amount of embodiment of the present invention.
By these descriptions and picture, many exemplary embodiments that include concrete configuration have been provided.For existing one of ordinary skilled in the art, the present invention can be implemented by a large amount of other embodiments, these personnel do not need more experiment also can implementation of class like other embodiment.With regard to the purpose of present patent application, protection scope of the present invention is not limited in aforesaid these concrete exemplary embodiments, but as claimed in claim.Any or all with claim content of the present invention quite or the modification on similar methods or the scope, all should be regarded as comprising within the spirit and scope of the present invention being protected.
Claims (21)
1. a compact type electric inductance power electronic device encapsulation is characterized in that, comprising:
A circuitry substrate;
A power inductance that is attached on the circuitry substrate, it comprises an inductance sense core with closed magnet circuit, and described inductance sense in-core portion has window;
Described circuitry substrate also comprises one and is positioned at bottom half coil under the inductance sense core by what the bottom half coil formed that element forms; And
One forms element with the bottom half coil and interconnects mutually and constitute one with it jointly and complete be enclosed in that the top half coil of inductance coil forms element around the inductance sense core;
So promptly realized a compact type electric inductance power electronic device encapsulation with high inductance grade.
2. electric inductance power electronic device encapsulation as claimed in claim 1 is characterized in that, an end of described top half coil formation element forms element with the bottom half coil within being positioned at inductance sense core window and links to each other; The other end forms element with adjacent another bottom half coil that is positioned at outside the inductance sense core and links to each other, and has constituted described inductance coil like this.
3. electric inductance power electronic device encapsulation as claimed in claim 1 is characterized in that described inductance sense core is a ring-type.
4. electric inductance power electronic device encapsulation as claimed in claim 1, it is characterized in that, described encapsulation also comprises an intraconnection chip, and it is positioned within the inductance sense in-core portion window, forms element interconnection in order to the top half coil that the bottom half coil is formed element and be positioned within the inner window.
5. electric inductance power electronic device encapsulation as claimed in claim 1, it is characterized in that, described encapsulation also comprises an external interconnect chip that is positioned at inductance sense core next door, forms element interconnection in order to the top half coil that the bottom half coil is formed element and be positioned at outside the inductance sense core.
6. electric inductance power electronic device encapsulation as claimed in claim 1 is characterized in that described closed magnet circuit also comprises an air gap.
7. electric inductance power electronic device encapsulation as claimed in claim 1 also comprises a power integrated circuit and a circuit Connection Element that this Power IC is connected with power inductance.
8. electric inductance power electronic device encapsulation as claimed in claim 1 is characterized in that described Power IC is positioned at the circuitry substrate top side.
9. electric inductance power electronic device encapsulation as claimed in claim 1 is characterized in that described circuitry substrate is a lead frame, and wherein said bottom half coil forms element and also comprises some lead frame circuits and constitute the bottom half coil thus.
10. electric inductance power electronic device encapsulation as claimed in claim 1, it is characterized in that, described top half coil forms element and also comprises some leadframe leads, each bar lead-in wire links to each other from the top around inductance sense core and with special neighbourhood bottom half coil formation element, and constitutes inductance coil thus.
11. electric inductance power electronic device encapsulation as claimed in claim 1, it is characterized in that, described top half coil forms element and also comprises some top key zygonemas, each bar bonding line links to each other from the top around inductance sense core and with special neighbourhood bottom half coil formation element, and constitutes inductance coil thus.
12. electric inductance power electronic device encapsulation as claimed in claim 1, it is characterized in that, described top half coil forms element and also comprises some three-dimensional tops interconnection plate, each piece interconnection plate links to each other from the top around inductance sense core and with special neighbourhood bottom half coil formation element, and constitutes inductance coil thus.
13. electric inductance power electronic device encapsulation as claimed in claim 1, it is characterized in that, described circuitry substrate is a multilayer circuit board MCL, this circuit board further comprises a top conductive line layer, the half coil conducting wire that a plurality of patternings are arranged on it, and form element as the bottom half coil with this.
14. electric inductance power electronic device encapsulation as claimed in claim 1 is characterized in that described encapsulation also comprises a bottom conductive line layer, top conductive line layer circuit wherein links to each other with bottom conductive line layer circuit.
15. electric inductance power electronic device encapsulation as claimed in claim 13 is characterized in that described MCL plate is a printed circuit board PCB.
16. electric inductance power electronic device encapsulation as claimed in claim 13 is characterized in that described MCL plate is a bismaleimides-cyanate resin BT substrate.
17. electric inductance power electronic device as claimed in claim 1 encapsulation is characterized in that described encapsulation also comprises encapsulant, is used for top encapsulation with the electric inductance power electronic device encapsulation.
18. a method of making the electric inductance power electronic device encapsulation is characterized in that, comprising:
A circuitry substrate is provided, comprises on it that bottom half coil forms element;
A power inductance is sticked on the circuitry substrate, and the process that adheres to this power inductance comprises that having inductance sense core that closed magnet circuit and central authorities have a window with one sticks to the bottom half coil and form on the element; And
Adhesion top half coil forms element, and these elements and bottom half coil formation element are linked to each other, and is looped around inductance sense core inductance coil on every side with this common formation.
19. the method for manufacturing electric inductance power electronic device encapsulation as claimed in claim 18, it is characterized in that, described adhesion top half coil forms element and comprises that also each top half coil is formed element one end to link to each other with the end that the bottom half coil that is positioned at inner window forms element, and the other end that this top half coil is formed element be positioned at ferrite sheet outside an end of adjacent base half coil formation element link to each other.
20. the method for manufacturing electric inductance power electronic device encapsulation as claimed in claim 18 is characterized in that, also comprises:
A power integrated circuit IC is sticked on the circuitry substrate.
21. the method for manufacturing electric inductance power electronic device encapsulation as claimed in claim 18 is characterized in that, also comprises with the top of encapsulant with the electric inductance power electronic device encapsulation encapsulating.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/397,473 | 2009-03-04 | ||
| US12/397,473 US8217748B2 (en) | 2007-11-23 | 2009-03-04 | Compact inductive power electronics package |
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| CN101826514A true CN101826514A (en) | 2010-09-08 |
| CN101826514B CN101826514B (en) | 2012-09-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024764A (en) * | 2015-03-25 | 2016-10-12 | 英飞凌科技美国公司 | Semiconductor Package with Integrated Output Inductor on a Printed Circuit Board |
| CN109390127A (en) * | 2018-11-12 | 2019-02-26 | 矽力杰半导体技术(杭州)有限公司 | Sustainable formula packaging and package assembling |
| CN111295748A (en) * | 2017-10-05 | 2020-06-16 | 德州仪器公司 | Lead frame in semiconductor device |
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| US4103267A (en) * | 1977-06-13 | 1978-07-25 | Burr-Brown Research Corporation | Hybrid transformer device |
| US5469334A (en) * | 1991-09-09 | 1995-11-21 | Power Integrations, Inc. | Plastic quad-packaged switched-mode integrated circuit with integrated transformer windings and mouldings for transformer core pieces |
| JP4030028B2 (en) * | 1996-12-26 | 2008-01-09 | シチズン電子株式会社 | SMD type circuit device and manufacturing method thereof |
| US7140092B2 (en) * | 2003-01-16 | 2006-11-28 | Georgia Tech Research Corporation | Methods for manufacturing inductor cores |
| CN100536043C (en) * | 2006-02-16 | 2009-09-02 | 上海交通大学 | Amorphous FeCuNbCrSiB magnetic thin film solenoid micro-inducer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024764A (en) * | 2015-03-25 | 2016-10-12 | 英飞凌科技美国公司 | Semiconductor Package with Integrated Output Inductor on a Printed Circuit Board |
| CN111295748A (en) * | 2017-10-05 | 2020-06-16 | 德州仪器公司 | Lead frame in semiconductor device |
| CN109390127A (en) * | 2018-11-12 | 2019-02-26 | 矽力杰半导体技术(杭州)有限公司 | Sustainable formula packaging and package assembling |
| CN109390127B (en) * | 2018-11-12 | 2024-01-30 | 矽力杰半导体技术(杭州)有限公司 | Supportable package device and package assembly |
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| TW201034534A (en) | 2010-09-16 |
| TWI386119B (en) | 2013-02-11 |
| CN101826514B (en) | 2012-09-05 |
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Denomination of invention: Compact type electric inductance power electronic device encapsulation Effective date of registration: 20191210 Granted publication date: 20120905 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20120905 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |