TWI386119B - Compact inductive power electronics package - Google Patents

Description

Compact Inductor Power Electronics Package

The present invention relates generally to the field of electronic system packaging, and more particularly to physical level packaging of discrete power inductors (or power inductors) with semiconductor wafers.

Due to the growing market demand, power semiconductor packages continue to trend toward smaller sizes and/or smaller pins while achieving higher power levels. A common power semiconductor package for a variety of converters (boost and step-down converters, etc.), which involves the packaging of inductive devices and semiconductor integrated circuit (IC) chips, and a large number of existing technologies exist in related fields. . One of the prior art names is "Ultra-Subminiature Power Converters" (U.S. Patent No. 6,930,584), invented by Edo et al., which was issued on August 16, 2005, hereinafter referred to as "Edo Patent". Figures A1 and A2 illustrate the Edo patent. Figure A1 shows a thin film inductor. The thin film inductor 1 comprises a ferrite substrate 7 which is partially surrounded by a plurality of electromagnet coil conductors. The ferrite substrate 7 is an electrical insulator. As shown in FIG. A1, the first portion of the electromagnet coil conductor includes a plurality of top coil conductors 4 formed on a top main plane of the ferrite substrate 7, and the second portion of the electromagnet coil conductor includes a plurality of ferrite linings formed thereon. The bottom coil conductor 5 on the bottom main plane of the bottom 7. A large number of connecting conductors 3 are formed in the holes passing through the ferrite substrate 7 for connecting the first portion 4 and the second portion 5 of the electromagnet coil conductor, thereby forming a ferrite substrate 7 as its inductance Core solenoid type inductor. An additional through hole 6c is formed and metallized along the periphery of the ferrite substrate 7, and the top electrode 6a and the bottom electrode 6b are connected to form a thin film inductor. Contacts and allow electrical signals to pass through the ferrite substrate 7. Figure A2 is a schematic cross-sectional view of an ultra-small power converter packaged in the form of a chip size module. The chip size module includes a semiconductor IC (integrated circuit) 8 which passes through a plurality of stud bumps 9 on electrodes (not explicitly shown) on the semiconductor integrated circuit and a plurality of thin film inductors The top electrode 6a is bonded to the top of the thin film inductor 1 as shown in FIG. 1A. The cross section of the thin film inductor 1 portion of the wafer size module is taken along the X-X axis of the A1 diagram. An underfill (not shown) is also applied between the thin film inductor 1 and the semiconductor IC 8 to passivate the wafer size module. It is worth noting that since the ferrite substrate 7 on the thin film inductor 1 has three-dimensional features consisting of the center and peripheral perforations 3, 6c, the electromagnet coil conductors 4, 5 and the electrodes 6a, 6b, the structure is complicated and thus processed. The cost is high. Another disadvantage is that this fragile ferrite wafer is barely exposed and there is no protection outside.

Another prior art is U.S. Patent No. 5,428,245, entitled "Lead Frames Containing Inductors or Other Similar Magnetic Elements", invented by Lin et al., issued on June 27, 1995, hereinafter referred to as "Lin Patent ". Figure B briefly describes the Lin patent. A lead frame having a large number of conductive leads is applied to the integrated circuit package shown in the drawing. The leadframe also includes a centrally integrated first inductive winding. The other coil windings also become an integral component of the leadframe that surrounds the primary winding to form a multilayered magnetic component winding. In one embodiment, the lead frame based winding is coated with a layer of magnetic material to form an inductor based on the lead frame. It is worth noting that although the published lead frame inductor windings can be used as signal inductors, such lead frame inductors may not be able to meet the power requirements of high inductance and low winding resistance without the actual core material. application.

Accordingly, what is desired in the present invention is a compact, easy to manufacture inductive power electronics package that provides a high level of inductance, including inductance values and saturation current.

The present invention discloses a compact inductive power electronics package having a high inductance rating comprising: a circuit substrate.

A power inductor is attached to the circuit substrate. The power inductor has an inductive core with a closed magnetic circuit with a window inside. In a more specific embodiment, the inductive core is annular. Alternatively, the inductive core may also include an air gap to adjust the inductance while maintaining the closed magnetic circuit.

The circuit substrate contains a plurality of constituent elements of the bottom half coil, and constitutes a bottom half coil located below the inductor core.

A plurality of top half-coil elements are connected to the bottom half-coil elements to form a complete inductive coil that surrounds the inductive core.

In a related embodiment, the top half coil forming component can connect the bottom half coil forming component terminal exposed to the inner window of the inductor core and the adjacent bottom half coil forming component terminal outside the inductor core In order to form an integral inductor coil. In other words, one end of each of the constituent elements of the top half coil may be connected to one end of the bottom half coil constituent element inside the inner window, and the other end may be connected to an adjacent bottom half coil constituent element outside the inductor core. Forming an inductive coil that surrounds the inductive core. Most of the terminals of the bottom half-coil component are located inside the inductor core In the mouth, the other terminal is located outside the inductor core.

In a related embodiment, an internal connection wafer is added to the window in the inductive core for connecting the top half and bottom half coil constituent elements in the internal window. In another related embodiment, an external connection wafer surrounding the inductor core is added to connect the top half coil and the bottom half coil to form the component outside the inductor core.

A power integrated circuit (IC) can be added to the package and interconnected with the power inductor. In a more specific embodiment, the power IC is attached to the top of the circuit substrate, and the circuit interconnection device provided by the circuit substrate is used to connect the power IC and the power inductor. The power IC can be placed on top of or next to the inductor core. The power IC can even be placed in a window in the inductor core to save the package pins and thickness. The power IC includes a power transistor and a control IC for controlling the transistor.

In a more specific embodiment, the circuit substrate is the lead frame and the bottom half-coil component is a large number of lead frame leads and thus constitutes the bottom half-coil. The top half-coil component acts as a bulky top leadframe lead, and the leads that surround the upper portion of the inductive core are further connected to a particular bottom leadframe lead and form an inductive coil. As a second option, the top half-coil element can also be a plurality of top bond wires, each of which is wrapped around the inductive core, further connected to a particular bottom leadframe lead, and constitutes an inductive coil. As a third option, the top half-coil element may be constructed of three-dimensional top interconnecting boards, each of which surrounds the inductive core, further connected to a particular bottom leadframe lead, and constitutes an inductive coil.

In another more specific embodiment, the circuit substrate is a multilayer circuit board (MCL), such as a printed circuit board (PCB), having a top conductive line The road layer, in which a large number of half-coil patterned conductive lines constitute the bottom half-coil element.

Accordingly, similar to the embodiment of the lead frame substrate, the top half coil element can be a large number of lead frame leads, bond wires or three dimensional interconnect plates. Alternatively, the MCL plate can also be a bismaleimide-triazine resin (BT) substrate.

It will be apparent to those skilled in the art that the top half coil element can be made of any conductor material (eg, bond wires, top lead frames, interconnect boards) and connected to a particular bottom half coil element. Likewise, the circuit substrate containing the bottom half-coil component can be constructed of any suitable material, such as a leadframe, PCB or BT resin substrate.

A method of fabricating the above described inductive power electronics package, the method comprising: providing a circuit substrate having a plurality of bottom half coil elements thereon; attaching a power inductor to the circuit substrate by:

- An inductive core having a closed magnetic circuit is disposed above the bottom half coil element, the center of the core having a window.

• A large number of top half-coil components are attached so that they are connected to the bottom half-coil component, which together form an inductive coil that encloses the inductive core.

As an additional option, a power IC can be attached to the circuit substrate.

As an additional option, the top of the inductive power electronics package can be packaged, including the core and top half coil forming components.

A method of attaching a plurality of top half coil constituent elements includes connecting each top half coil element to a terminal of a bottom half coil element located within the window and an adjacent bottom half coil element terminal located outside the inductive core .

These features and related embodiments of the present invention are further described by the present invention It will be clearer and clearer to those skilled in the art.

The above and below description of the figures is only for one or several of the presently mentioned embodiments of the invention, and also describes some representative embodiments with additional components and/or alternatives. . The description and drawings are provided for the purpose of illustration and should not be construed as limiting the invention. Thus, those skilled in the art can readily recognize variations, modifications, or substitutions thereof. Such variations, modifications, and alterations are to be understood as being included within the scope of the appended claims.

In order to facilitate the understanding and understanding of the present invention, the entire drawings of Figures C1 through C5, including their descriptions, are taken from U.S. Patent Application Serial No. 12/011,489, the entire disclosure of which is hereby incorporated by A top view of one embodiment of a power inductor. Figure C2 is a top plan view of the top lead frame of the present invention.

Figure C3 is a side view of the power inductor shown in Figure C1. Figure C4 is a top plan view of the interconnect wafer of the present invention. Figure C5 is a cross-sectional view of the interconnect wafer shown in Figure C4.

As shown in FIG. C1, in one embodiment, the lead frame based split power inductor number is 300, with a portion of the leads of the bottom lead frame 260 being shown in dashed lines in the figure. Power inductor 300 includes a flat bottom leadframe 260, a top leadframe 320, and leads that are interconnected around core 110. An interconnect wafer 330 is disposed in the window 115 (as shown in Figure C3), making it possible to connect the top internal contact area to the bottom leadframe lead. Referring to FIG. C2, the top lead frame 320 includes a top lead frame 320 disposed at the top. The first set of leads 320a, 320b and 320c on the first side.

The top leads 320a, 320b, and 320c have a non-linear stepped structure to facilitate connection of the leads of the bottom lead frame 260 to form a complete coil to be described later. The top leads 320a, 320b, and 320c include internal contact regions 321a, 321b, and 321c that are respectively disposed on the cross sections of the top leads 320a, 320b, and 320c along A-A. The top leads 320a, 320b, and 320c further include external contact regions 323a, 323b, and 323c disposed on the cross sections of the top leads 320a, 320b, and 320c, respectively, along B-B (below the A-A plane, parallel to the A-A plane). The top leadframe 320 also includes a second set of leads 320d, 320e, and 320f disposed on a second side of the top leadframe 320. The top leads 320d, 320e, and 320f have a non-linear stepped structure to facilitate connection of the leads of the bottom lead frame 260 to form a complete coil to be described later. The top leads 320d, 320e, and 320f include contact regions 321d, 321e, and 321f respectively disposed inside the section A-A, and further include external contact regions 323d, 323e, and 323f respectively disposed in the section B-B. The top and bottom lead frames 320 and 260, which are respectively wrapped around the core 110, are wire-bonded to form a complete coil.

The interconnect wafer 330 as shown in Figures C4 and C5 includes six conductive vias 330a, 330b, 330c, 330d, 330e, and 330f (as indicated by the dashed lines in Figure C1), the vias being spaced apart from each other A connection is provided between the internal contact areas for providing the leads of the top lead frame 320 and the bottom lead frame 260. Solder bumps 340 are preferably formed on the upper and lower surfaces of interconnect wafer 330 to facilitate connection.

The coil surrounding the core 110 is as shown in Fig. C1. Lead internal contact regions 260a, 260b, 260c, 260d, 260f of bottom lead frame 260 And 260g are respectively coupled to the inner contact regions 321a, 321b, 321c, 321d, 321e, and 321f of the top lead frame 320 through the interconnect wafer 330. The lead outer contact regions 260b, 260c, 260d, 260e, 260f, and 260g of the bottom lead frame 260 are coupled to the outer contact regions 323a, 323b, 323c, 323d, 323e, and 323f of the top lead frame 320 around the edge of the magnetic core 110, respectively. .

The inner contact region 261a of the lead 260a is coupled to the inner contact region 321a of the lead 320a by a via 330a. The outer contact region 323a of the lead 320a is coupled to the outer contact region 263b of the adjacent lead 260b. The inner contact region 261b of the lead 260b and the inner contact region 321b of the lead 320b are coupled by a through hole 330b. The outer contact region 323b of the lead 320b is coupled to the outer contact region 263c of the adjacent lead 260c. The inner contact region 261c of the lead 260c is coupled to the inner contact region 321c of the lead 320c through the through hole 330c. The outer contact region 322c of the lead 320c is coupled to the outer contact region 263d of the adjacent lead 260d. The inner contact region 261d of the lead 260d and the inner contact region 321f of the lead 320f are coupled by a through hole 330f. The outer contact region 323f of the lead 320f is coupled to the outer contact region 263g of the adjacent lead 260g. The inner contact region 261g of the lead 260g is coupled to the inner contact region 321e of the lead 320e through the through hole 330e. The outer contact region 323e of the lead 320e is coupled to the outer contact region 263f of the adjacent lead 260f. The inner contact region 261f of the lead 260f is coupled to the inner contact region 321d of the lead 320d through the through hole 330d. The outer contact region 323d of the lead 320d is coupled to the outer contact region 263e of the adjacent lead 260e. As described in the first and second embodiments, the non-linear stepped structure of the top and bottom leadframe leads provides alignment and spacing for the inner and outer contact regions.

The split power inductor 300 includes terminals 260a and 260e, top and bottom leads The connection between the wire frames 320 and 260 leads through the interconnect wafer 330 constitutes a complete coil that surrounds the core 110.

The split power inductor 300 is packaged using a package to form a package (not shown). The package includes conventional packaging materials. Alternatively, the package also includes a material to which magnetic powder is added, such as ferrite particles, to provide a mask and improve magnetic properties.

In the embodiment shown in FIGS. C1 to C5 (separate power inductor 300 based on lead frame), the circuit substrate including the bottom half coil element is the bottom lead frame 260. The top half coil element is the top lead frame 320. The inductive core with the window inside is the core 110 having the window 115. The interconnect package 330 within the window 115 facilitates the connection between the top half coil element 320 and the bottom half coil element 260. Power inductor 300 is a discrete component that is not packaged with a power IC.

In order to facilitate the understanding and understanding of the present invention, FIGS. D1 through D2 and their description are taken from U.S. Patent Application Serial No. 11/986,673, the entire disclosure of which is hereby incorporated by In a top view, the semiconductor package includes an integrated inductor based on a leadframe.

Figure D2 is a top plan view of the bottom of a sixth embodiment of a semiconductor power device package of the present invention comprising a leadframe based integrated inductor.

One embodiment of the invention, as shown in FIG. D1, includes a semiconductor power device package 1900 that includes a leadframe-based integrated inductor 1950. The inductor 1950 is comprised of a ferrite sheet 1800, a plurality of adjacent leads on the leadframe 100, and bond wires 1920e, 1920f, 1920i, 1920j, 1920k, and 1920m. The connection wafer 500 is provided by the through holes 510a to 510f formed thereon Conductive connection. The ferrite sheet 1800 is attached over the upper surface 150 of the lead frame 100 and is supported by the large liner 120 and the small liner 130. The ferrite sheet 1800 is disposed over the upper surface 150 of the lead frame 100 such that the lead ends 140d to 140f are easily connected through the windows 1810 and 140j to 140m. A power IC 1930 is also easily connected through window 1810.

The connection wafer 500 is sized and configured to fit within the window 1810. The through holes 510a to 510f are formed and positioned on the connection package 500 such that they are over and electrically connected to the lead terminals 140d to 140f and 140j to 140m of the lead frame 100 having a conductive epoxy or solder. Power IC 1930 is disposed adjacent to wafer 500 in window 1810.

The bonding wires couple adjacent leads of the lead frame 100 to form a closed magnetic path with the ferrite sheet 1800 as a magnetic core. The bonding wire 1920e couples one end 140d of the lead 110d to the adjacent lead 110e through the through hole 510a, and the bonding wire 1920e together with the adjacent leads 110d and 110e constitute a loop surrounding the ferrite sheet 1800. The bonding wire 1920f couples one end 140e of the lead 110e to the adjacent lead 110f through the through hole 510b, and the bonding wire 1920f together with the adjacent leads 110e and 110f constitute a loop surrounding the ferrite sheet 1800. The bonding wire 1920m couples one end 140f of the lead 110f to the adjacent lead 110m through the through hole 510c, and the bonding wire 1920m forms a loop around the ferrite sheet 1800 together with the adjacent leads 110f and 110m. The bonding wire 1920k couples one end 140m of the lead 110m to the adjacent lead 110k through the through hole 510f, and the bonding wire 1920k together with the adjacent leads 110m and 110k constitute a loop surrounding the ferrite sheet 1800. The bonding wires couple one end 140k of the lead 110k to the adjacent lead 110j through the through holes 510e 1920j, and the bonding wires 1920j together with the adjacent leads 110k and 110j constitute a loop surrounding the ferrite sheet 1800. Bond wire through perforation 510d 1920i couples one end 140j of lead 110j to adjacent lead 110i, and bond line 1920i, together with adjacent leads 110j and 110i, forms a loop that surrounds ferrite sheet 1800. Leads 110d and 110i make up the leads of inductor 1950.

The power IC 1930 is attached to the large pad 120 of the lead frame 100. Bond wire 1920d couples power IC 1930 to lead 110d to couple with lead frame based integrated inductor 1950. Bond wires 1920a, 1920b, and 1920c couple power IC 1930 to leads 110a, 110b, and 110c, respectively. Bond wires 1920g and 1920h couple power IC 1930 to leads 110g and 110h, respectively.

Due to the application of the wafer 500, it is no longer necessary to use special bonding tools (such as the K&S Close Center Bond), and a standard bonding tool can meet the requirements.

A package is used to complete the semiconductor power device package 1900, which is filled in the semi-etched regions of the leads 110a through 110m for securing the leadframe 100 such that the leads are less likely to be separated from the package. The outer contour of the package is indicated by a dashed line in the figure.

In the embodiment shown in FIGS. D1 and D2 (semiconductor power device package 1900), the circuit substrate including the bottom half coil element is the lead frame 100. The top half coil forming elements are the bonding wires 1920d to 1920f, and 1920i to 1920m. The inductive core is a ferrite sheet 1800 having a window 1810. The semiconductor power device package 1900 includes a power IC 1930 disposed within the window 1810 adjacent to the wafer 500.

1A through 1F illustrate a compact inductive power electronics package 300 of the present invention comprising a power inductor 12 and a power IC die 11, both located in an MCL board (in this embodiment, a 2 layer) PCB board 61) Above. The power inductor 12 has a rectangular ring ferrite sheet 15 having a closed magnetic circuit as an inductive core with a window 16 in the center. It is very important for those skilled in the art to make the ferrite sheet 15 into a closed loop shape in order to achieve a high inductance with a compact inductor size in order to confine most of the magnetic flux therein, and this is very important. The specific shape of the closed loop is slightly less important. Thus, for example, the closed loop shape can have the following choices, square, polygonal, elliptical or circular. However, it is generally believed that a circle can provide the most efficient magnetic constraint. The path of the closed magnetic circuit surrounds the inner window 16. The 2-layer PCB board 61 has a top conductive wiring layer 62, a bottom conductive wiring layer 64, and an intermediate insulating layer 65 which insulates the two conductive wiring layers 62 and 64 from each other. Figure 1A is a top plan view of the inductive power electronics package 300 with the package removed for a clearer view of the internal components. FIGS. 1B and 1C are top and side cross-sectional views of the ferrite sheet 15, which is a component of the power inductor 12. Figure 1D is a top plan view of a power IC die 11 having a plurality of IC contact pads 11g on top of it. Figure 1E is a top plan view of the top conductive trace layer 62. FIG. 1F is a bottom view of the bottom conductive wiring layer 64.

Next, the top conductive wiring layer 62 includes a first group of half-coil patterned conductive traces 62a to 62d, 62f and 62A to 62D disposed under the inductor core (ferrite sheet 15). In fact, 62a to 62d, 62f and 62A to 62D together form the bottom half coil of power inductor 12. Accordingly, the second set of top half-coil bonding wires 19a to 192d and 19A to 19D are located above the ferrite sheet 15, and each of the bonding wires surrounds the ferrite sheet 15 from above. Moreover, both ends of each of the top half-coil bonding wires are connected to the corresponding bottom half-coil conductive lines to form an induction coil surrounded by the ferrite sheets 15. Thus, for example, one end of the top half coil wire 19a and the half coil located outside the ferrite sheet 15 The conductive line 62a is bonded and the other end is bonded to an adjacent half-coil conductive line 62b located inside the window 16 inside the ferrite sheet 15. Both ends of the top half-coil bonding wire 19b are also bonded to the half-coil conductive lines 62b and 62c in a similar manner. Both ends of the top half-coil bonding wire 19c are also bonded to the half-coil conductive lines 62c and 62d, respectively, and the like. Finally, both ends of the top half-coil bonding wire 19D are bonded to the half-coil conductive lines 62D and 62f, respectively. As a result, the half coil conductive traces 62f and 62a of the top conductive trace layer 62 become the two device terminals of the power inductor 12 for connection to other devices of the inductive power device package 300, for example, with the power IC wafer 11 The circuit is connected by another bonding wire. Other bonding pads 63a to 63e of the top conductive wiring layer 62 (bonded to the IC contact point 11g of the power IC wafer 11) may be used to be external to the inductive power device package 300 through via holes 65a (described later). Make a connection. Although not mentioned in order to avoid excessive description of the details, in order to facilitate precise adjustment of the inductance of the power inductor 12, the ferrite sheet 15 can be left with one or more air gaps in the direction of the magnetic ring at the time of manufacture.

Although the bottom conductive trace layer 64 and the top conductive trace layer 62 of the PCB board 61 can be independently patterned using a variety of different conductive trace geometries plus a plurality of conductive interconnect vias through the insulating layer 65, as shown at the bottom. A large number of bottom conductive traces 64a to 64g and a large number of conductive vias 65a remain on the conductive wiring layer 64. Correspondingly, the top conductive wiring layer 62 also includes a plurality of conductive vias 65a in one-to-one correspondence with the conductive via locations on the bottom conductive trace layer 64. This allows the bottom conductive traces 64a-g to be externally connected to each other and to the opposite top conductive traces 63a-e and 62a and 62f (the bottom conductive traces 64f and 64g are respectively connected to the half coil conductive traces 62f and 62a) Connected. A special case of a bottom conductive line 64a is an extended bottom ground plane 64m. It is often used for signal masking and heat transfer for EMI/RFI (electromagnetic interference/radio frequency interference). In a more specific embodiment, PCB board 61 is fabricated from a bismaleimide-triazine resin (BT) substrate or other type of MCL plate. When the power IC wafer 11 is placed in close proximity to the ferrite sheet 15, the power IC wafer 11 can be placed in the internal window in the case where the relevant dimensions of the power IC wafer 11, the ferrite sheet 15, and the internal window 16 thereon are appropriate. Within 16 so that the inner bottom half coil conductive line and the top half coil bond line can be connected within the window. If desired, the power IC wafer 11 can even be placed over the ferrite sheet 15, which further reduces the pin area of the inductive power electronics package 300 based on increased package thickness. The power IC die 11 includes a power transistor and control circuitry integrated to control the power transistor.

In the compact inductive power electronics package 300, the circuit substrate is a PCB board 61 and the bottom half coil elements are half coil conductive lines 62a to 62d, 62f and 62A to 62D. Now, it is clear that in general, a PCB or MLC board with more than 2 layers can be applied to a compact inductive power electronics package and correspondingly increase the flexibility of the package. In fact, the PCB board 61 can be replaced by any circuit substrate including a suitable bottom half coil element, such as the C1 to C2 diagrams, and the bottom lead frame shown in FIGS. D1 to D2. The top half coil element is a bond wire 19. Bond wire 19 can be replaced by any suitable top half coil component, such as the top leadframe or interconnect plate shown in Figures C1 through C3. The inductive power electronics package contains a separate power inductor as shown in Figures C1 through C3; or a power inductor packaged with a power IC, as shown in Figure 1A. As shown in Figures 1 to 4, more embodiments fully illustrate the flexibility of the design of the present invention. Sex.

Figure 2 illustrates a second embodiment of the present compact inductive power electronics package 350 in which the power inductor 12 having a closed magnetic loop is positioned over a leadframe. Through the package 101, the various components are shown in dashed lines in the figure. Similar to Fig. 1A, the power inductor 12 has a rectangular ferrite sheet 15 having a window 16 inside as a core. The lead frame includes a plurality of bottom half coil wires 17a to 17g located below the ferrite sheet 15. In fact, the bottom half coil wires 17a to 17g together constitute the bottom half coil of the power inductor 12. In contrast, other top half-coil bonding wires 19a to 19f are located above the ferrite sheet 15, and each of the bonding wires is bypassed from the ferrite sheet 15. Moreover, both ends of each of the top half coil wires are connected to a specific adjacent bottom half coil wire to collectively constitute an inductor coil surrounding the ferrite sheet 15. For example, both ends of the top half-coil bonding wire 19a are bonded to the bottom half-coil wires 17a and 17b, respectively. Both ends of the top half-coil bonding wire 19b are bonded to the bottom half-coil wires 17b and 17c, respectively. Both ends of the top half-coil bonding wire 19c are bonded to the bottom half-coil wires 17c and 17d, respectively, and the like. Finally, both ends of the top half-coil bonding wire 19f are bonded to the bottom half-coil wires 17f and 17g, respectively. As a result, the lead frame bottom half coil wires 17a and 17g become the two device terminals of the power inductor 12 for connection to the outside of the inductive power electronics package 350.

3A through 3D illustrate another embodiment of a split power inductor 70, except that the bottom lead frame is replaced by an MCL board (eg, a 2-layer PCB board 71), with the remainder being the same as in the previous embodiment. similar. The 2-layer PCB board 71 includes a top conductive wiring layer 72, a bottom conductive wiring layer 74 and an insulating layer 75 therebetween for insulating the two conductive wiring layers 72 and 74 from each other. Figure 3A is a cross-sectional side of the split power inductor 70 view. Figure 3B is a top plan view of the top conductive trace layer 72. Figure 3C is a bottom plan view of the PCB board 71 showing the bottom conductive trace layer 74. Figure 3D is a top plan view of the split power inductor 70 with the package 101 removed for a clearer view of the internal components. The half coil conductive lines 72a to 72g among the top conductive wiring layers 72 will be patterned and function similarly to the half coil conductive lines 62a-62d, 62f and 62A-62D in Figs. 1A to 1D. Both the bottom conductive trace layer 74 and the top conductive trace layer 72 of the PCB board 71 can be independently patterned using a variety of different conductive trace geometries, plus a plurality of conductive interconnect vias through the insulating layer 75, as shown, A plurality of bottom conductive traces 74a-74c and 74f-74g are left on the bottom conductive trace layer 74, plus conductive vias 75a and 75b. Conductive vias 75a and 75b connect the inductors (lines 72f and 72g) to the bottom of PCB board 71 (lines 74f and 74g), which allows the inductor to be connected to the outside.

The PCB board 71 also includes a plurality of peripheral contact bumps (e.g., 115e and 115a for connecting to the outside of the PCB board 71) in contact with the bottom conductive traces 74a-74c, 74f-74g. These bumps are placed below the bottom traces 74a to 74c to ensure stability, while the bumps under the bottom traces 74f and 74g are also used for conductive connection to the outside. In a more specific embodiment, the PCB board 71 is composed of a BT resin substrate. As shown in FIG. 3A, the package 101 protects the top of the split power inductor 70 (including the ferrite sheets 15, the bond wires 79a-79f and the top conductive trace layer 72).

In the embodiment shown in Figures 3A through 3D (separate power inductor 70), the circuit substrate containing the bottom half coil component is a PCB board 71 comprising a top conductive trace layer 72. The top half coil elements are bonding wires 79a to 79f. The inductive core 15 (typically a ferrite sheet) has a window 16.

4A through 4C illustrate another embodiment of a split power inductor 40 in which the power inductor 40 uses a plurality of peripheral bracket bumps (e.g., 43b and 43c at the bottom of the lead frame 41) and a top half located thereon. Coil interconnect boards (42a to 42h). Figure 4A is a top view for a clearer view of the internal device after the package 101 has been removed. Fig. 4B is a top plan view of the lead frame 41 alone. Figure 4C is a side view of the split power inductor 40. Unlike the bonding wires used in FIG. 1A, a large number of three-dimensional top half-coil interconnecting plates 42a to 42h (each of which surrounds the inductive core 15 and further connected to the specific bottom half-coil conductive leads 41a to 41j) are Used to form an inductor. For example, both ends of the top half-coil interconnecting plate 42a are bonded to the bottom half-coil conductive leads 41a and 41b, respectively. Both ends of the top half-coil interconnecting plate 42b are respectively bonded to the bottom half-coil conductive leads 41b and 41c. Both ends of the top half-coil interconnection board 42c are respectively bonded to the bottom half-coil conductive leads 41c and 41d, and the like. Finally, both ends of the top half-coil interconnecting plate 42h are respectively bonded to the bottom half-coil conductive leads 41h and 41i. As a result, the bottom half coil conductive leads 41a and 41i become the two device terminals of the power inductor for circuit connection with the outside. The advantage of an inductor consisting of a top half-coil interconnect plate is that it has a lower coil resistance than a bond wire.

A plurality of peripheral bracket projections 43b and 43c are attached to the bottom of the bottom half coil conductive leads 41d and 41f. In order to achieve stability, there are at least three peripheral bracket bumps, although only two of them are required to form an electrically conductive connection with the inductor.

In general, the package can completely enclose the top of the inductive package, including the inductive core and the top half coil forming component. The package acts to protect and electrically isolate the components it surrounds. When a fragile ferrite sheet is used as an inductive core, when a bond wire or interconnect is used as the top half coil component This feature is extremely beneficial. For example, the package can be a standard molded plastic. In a more specific embodiment, the package contains embedded magnetic particles for increasing the inductance of the power inductor.

For those skilled in the art, a large number of top half-coil bond wires 19a through 19f can be replaced with top leadframe leads that surround the ferrite sheet 15 from above and further with a specific bottom half-coil conductive lead below. 17a to 17g are connected and thus constitute an inductive coil. Alternatively, the top half-coil bonding wires 19a to 19f may be replaced with a three-dimensional top interconnecting plate that surrounds the ferrite sheet 15 from above and is further connected to the bottom half-coil conductive leads 17a to 17g, and is connected by This also constitutes an inductive coil. The advantage of an inductor consisting of a top interconnect board is that it has a lower coil resistance than using a bond wire.

Referring again to Figures 1A through 1F, a corresponding method of fabricating an inductive power electronics package 300 should include providing a PCB board 61 having a plurality of semi-coil patterned conductive traces such as 62a through 62D.

The power inductor 12 is adhered to the PCB board 61 by placing the ferrite sheet 15 over the semi-coil patterned conductive line. As an additional option, the power IC wafer 11 can also be adhered to the PCB board 61.

A plurality of top half-coil bond wires, such as 19a through 19D, are then adhered such that they are connected to a plurality of half-coil patterned conductive traces below and together form an inductive coil surrounding the ferrite sheet 15.

In a more specific embodiment, the method of pasting the top half coil further comprises: connecting one end of each top half coil forming element to one end of a bottom half coil forming element located within the inner window, and the top Half coil The other end of the forming element is connected to one end of an adjacent bottom half coil forming element located outside the ferrite sheet.

The aspect further includes the step of packaging the top of the inductive power electronics package with a package.

Up to now, it will be apparent to those skilled in the art that a large number of the above embodiments can be easily modified to suit other specific applications. While the above-described embodiments are not to be construed as limiting the scope of the invention,

Through these descriptions and pictures, a number of exemplary embodiments including specific configurations are given. The present invention may be embodied in a number of other specific embodiments, which may be practiced by those skilled in the art without departing from the scope of the invention. For the purposes of this patent application, the scope of protection of the present invention is not limited to the specific exemplary embodiments described above, but rather the claims.

Any and all modifications or equivalents of the method or scope of the present invention should be construed as being included within the spirit and scope of the invention.

300‧‧‧Separate power inductors based on lead frames

12‧‧‧Power Inductors

15‧‧‧Rectangular ring ferrite sheets

16, 1810‧‧‧ window

19a, 19b, 19c, 19d, 19e, 19f, 19A, 19B, 19C, 19D‧‧‧ top half coil bonding wires

61, 71‧‧‧PCB board

PCB‧‧‧Printed circuit board

62a, 62b, 62c, 62d, 62f, 62A, 62B, 62C, 62D, 72a, 72b, 72c, 72d, 72e, 72f, 72g‧‧‧ half-coil conductive lines

63a, 63b, 63c, 63d, 63e, 63f‧‧‧ top conductive lines

1‧‧‧thin film inductance

7‧‧‧ Ferrite substrate

4‧‧‧Top coil conductor

5‧‧‧Bottom coil conductor

3‧‧‧Connecting conductor

6a‧‧‧Top electrode

6b‧‧‧ bottom electrode

6c, 330c, 510a, 510b, 510c, 510d, 510e, 510f‧‧‧ perforation

8‧‧‧Integrated circuit

9‧‧‧Cylindrical bumps

110‧‧‧ magnetic core

115, 1810‧‧‧ window

260‧‧‧Bottom lead frame

260b, 260c, 260d, 260e, 260f, 260g‧‧‧ cited Line external contact area

320‧‧‧Top lead frame

320a, 320b, 320c, 320d, 320e, 320f‧‧‧ top leads

321a, 321b, 321c, 321d, 321e, 321f‧‧‧ internal contact area

323a, 323b, 323c, 323d, 323e, 323f‧‧‧ external contact area

330‧‧‧Interconnect wafer

330a, 330b, 330c, 330d, 330e, 330f‧‧‧ conductive perforation

340‧‧‧welding bumps

1900‧‧‧Semiconductor Power Device Package

100‧‧‧ lead frame

1800‧‧‧ Ferrite tablets

1950‧‧‧Integrated inductance based on lead frame

150‧‧‧ surface

500‧‧‧Connected wafer

1930‧‧‧Power IC

IC‧‧‧ integrated circuit

120‧‧‧ large pad

130‧‧‧Small pad

110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j, 110k, 110m‧‧‧ lead

1920a, 1920b, 1920c, 1920d, 1920e, 1920f, 1920g, 1920h, 1920i, 1920j, 1920k, 1920m, 79a, 79b, 79c, 79d, 79e, 79f‧‧‧ bond wires

11‧‧‧Power IC chip

11g‧‧‧Contact pads

65, 75‧‧‧ insulation

65a‧‧‧through hole

64, 74‧‧‧ bottom conductive layer

64a, 64b, 64c, 64d, 64e, 64f, 64g, 74a, 74b, 74c, 74f, 74g‧‧‧ bottom conductive lines

64m‧‧‧Bottom ground plane

350‧‧‧Inductor Power Electronics Package

101‧‧‧Package

17a, 17b, 17c, 17d, 17e, 17f, 17g, 41a, 41b, 41c, 41d, 41e, 41f, 41g, 41h, 41i, 41j‧‧‧ bottom half coil conductive leads

70, 40‧‧‧Separate power inductors

72‧‧‧Top conductive circuit layer

115a, 115e‧‧‧ peripheral contact bumps

75a, 75b‧‧‧ conductive perforations

42a, 42b, 42c, 42d, 42e, 42f, 42g, 42h‧‧‧3D top half coil interconnection board

43b, 43c‧‧‧ peripheral bracket bumps

For a more complete description of the numerous embodiments of the invention, reference is made to the drawings. However, the drawings are not to be considered as limiting the scope of the invention, but are merely illustrative.

Figures A1 and A2 are prior art ultra-small converters using an electromagnet coil film inductor; Figure B shows a planar coil inductor based on a prior art lead frame; Figures C1 through C5 are extracted from U.S. Patent Application Serial No. 12/011,489; and Figures D1 through D2 are from U.S. Patent. Appendix 1/986, 673; FIG. 1A to FIG. 1F illustrate a first embodiment of a compact inductive power electronics package provided by the present invention, the package including a closed magnetic loop power inductor and located at a 2 A power IC chip over a layer PCB board; and Figure 2 illustrates a second embodiment of the compact inductive power electronics package provided by the present invention, the package including a closed magnetic loop power inductor located above the lead frame.

3A through 3D illustrate another embodiment of a compact inductive power electronics package provided by the present invention, the package including a separate power inductor having a closed magnetic circuit and located on a PCB board .

4A through 4C illustrate another embodiment of a compact inductive power electronics package provided by the present invention, the package including a separate power inductor having a closed magnetic circuit and being placed over a lead frame And an interconnecting plate is used as the top half coil forming element.

300‧‧‧Separate power inductors based on lead frames

12‧‧‧Power Inductors

15‧‧‧Rectangular ring ferrite sheets

16, 1810‧‧‧ window

19a, 19b, 19c, 19d, 19e, 19f, 19A, 19B, 19C, 19D‧‧‧ top half coil bonding wires

61, 71‧‧‧PCB board

PCB‧‧‧Printed circuit board

62a, 62b, 62c, 62d, 62f, 62A, 62B, 62C, 62D, 72a, 72b, 72c, 72d, 72e, 72f, 72g‧‧‧ half-coil conductive lines

63a, 63b, 63c, 63d, 63e, 63f‧‧‧ top conductive lines

Claims (21)

A compact inductive power electronic device package, comprising: a circuit substrate; a power inductor attached to the circuit substrate, comprising an inductive core having a closed magnetic circuit, and the inductance a window is formed inside the core; the circuit substrate further comprises a bottom half coil formed by the bottom half coil forming component under the inductance core; and a bottom half coil forming component is interconnected and formed together to form a complete a top half coil forming component surrounding the inductor core around the inductive core; an internal interconnect wafer having a top plane and a bottom plane located within the inner window of the inductive core for forming the bottom half coil component and The top half coils located within the inner window form element interconnections; and the top half coil forming element has an inner contact region disposed on the top plane and an outer contact region disposed on the bottom plane; A compact inductive power electronics package with high inductance levels is implemented. The inductive power electronic device package of claim 1, wherein one end of the top half coil forming element is connected to a bottom half coil forming element located inside the inductive core window; the other end is adjacent to The other bottom half coil forming element outside the inductive core is connected to form the inductive coil. The inductor power electronic device package according to claim 1, wherein the inductive core is annular. The inductive power electronic device package of claim 1, wherein the internal interconnect wafer further comprises a plurality of conductive vias, The conductive perforations are respectively spaced apart from each other corresponding to the bottom half coil forming element and the top half coil forming element, and are used to provide an internal connection. The inductor power electronic device package of claim 1, wherein the package further comprises an external interconnect wafer located beside the inductor core for forming the bottom half coil forming component and the sense of inductance The top half coils outside the core form component interconnections. The inductive power electronic device package of claim 1, wherein the closed magnetic circuit further comprises an air gap. The inductive power electronic device package of claim 1, further comprising a power integrated circuit and a circuit connecting component connecting the power IC to the power inductor. The inductive power electronic device package of claim 7, wherein the power IC is located on a top side of the circuit substrate. The inductor power electronic device package of claim 1, wherein the circuit substrate is a lead frame, wherein the bottom half coil forming component further comprises a plurality of lead frame lines and thereby forms a bottom half Coil. The inductive power electronic device package of claim 1, wherein the top half coil forming component further comprises a plurality of lead frame leads, each lead surrounding the inductor core from above and passing through the interconnect chip It is connected to a specific adjacent bottom half coil forming element and thus constitutes an inductive coil. The inductor power electronic device package of claim 1, wherein the top half coil forming component further comprises a plurality of top bonding wires, each of the bonding wires surrounding the inductor core from above and passing through the interior Interconnect wafer It is connected to a specific adjacent bottom half coil forming element and thus constitutes an inductive coil. The inductor power electronic device package of claim 1, wherein the top half coil forming component further comprises a plurality of three-dimensional top interconnect boards, each of the interconnecting boards surrounding the inductor core from above and passing through the The internal interconnect wafer is connected to a particular adjacent bottom half coil forming element and thereby constitutes an inductive coil. The inductor power electronic device package of claim 1, wherein the circuit substrate is a multilayer circuit board MCL, the circuit board further comprising a top conductive circuit layer having a plurality of patterns thereon The half-coil conductive line is used as the bottom half-coil forming element. The inductive power electronic device package of claim 1, wherein the package further comprises a bottom conductive circuit layer, wherein the top conductive circuit layer line is connected to the bottom conductive circuit layer line. The inductor power electronic device package of claim 13, wherein the MCL board is a printed circuit board PCB. The inductor power electronic device package of claim 13, wherein the MCL board is a double maleimide-triazine resin BT substrate. The inductive power electronic device package of claim 1, wherein the package further comprises a package for encapsulating the top of the inductive power electronics package. A method of fabricating an inductor power electronic device package, comprising: providing a circuit substrate including a bottom half coil forming component; attaching a power inductor to the circuit substrate and adhering the power inductor Over The method includes attaching an inductive core having a closed magnetic circuit and having a window in the center to the bottom half coil forming component; and providing an internal interconnect wafer having an upper plane and an inner window of the inductive core a bottom plane for interconnecting the bottom half coil forming element with the top half coil forming element located within the inner window; and adhering the top half coil forming element having the top half coil forming element disposed on the top An internal contact area on the plane and an external contact area disposed on the bottom plane, the elements are connected to the bottom half-coil forming element through the internal interconnect wafer within the internal window, thereby forming a surrounding inductance Inductor coil around the core. The method of manufacturing an inductor power electronic device package according to claim 18, wherein the adhering top half coil forming component further comprises passing one end of each top half coil forming component through the internal interconnect wafer Connected to one end of the bottom half coil forming element at the inner window and the other end of the top half coil forming element to an end of the adjacent bottom half coil forming element outside the inductive core. The method of manufacturing an inductor power electronic device package according to claim 18, further comprising: attaching a power integrated circuit IC to the circuit substrate. The method of fabricating an inductor power electronic device package of claim 18, further comprising packaging the top of the inductive power electronics package with the package.