CN101826310A - High reliability grid drive circuit - Google Patents
High reliability grid drive circuit Download PDFInfo
- Publication number
- CN101826310A CN101826310A CN200910118908A CN200910118908A CN101826310A CN 101826310 A CN101826310 A CN 101826310A CN 200910118908 A CN200910118908 A CN 200910118908A CN 200910118908 A CN200910118908 A CN 200910118908A CN 101826310 A CN101826310 A CN 101826310A
- Authority
- CN
- China
- Prior art keywords
- electrically connected
- signal
- order
- frequency
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a high reliability grid drive circuit used for supplying a plurality of grid signals and respectively feeding the grid signals to a plurality of grid lines. The grid drive circuit comprises a plurality of levels of shift registers, and each level of shift register comprises an upward pulling unit, an energy storage unit, a buffer unit, a discharge unit, a first downward pulling unit, a second downward pulling unit and a control unit, wherein the upward pulling unit pulls grid signals upwards based on drive control voltage and a first frequency, the buffer unit is used for receiving input signals, the energy storage unit executes a charge program based on the input signals to supply the drive control voltage, the discharge unit pulls the drive control voltage downwards based on control signals, the first downward pulling unit pulls the grid signals downwards based on the control signals, the second downward pulling unit pulls the grid signals downwards based on a second frequency of opposite phase to the first frequency, and the control unit generates control signals based on the grid signals.
Description
Technical field
The invention relates to a kind of gate driver circuit, refer to that especially a kind of tool descends the grid drive circuit with high reliability of pull mechanism alternately.
Background technology
Liquid crystal indicator (Liquid Crystal Display; LCD) be present widely used a kind of flat-panel screens, it has, and external form is frivolous, power saving and advantage such as radiationless.The principle of work of liquid crystal indicator is the ordered state that the voltage difference that utilize to change the liquid crystal layer two ends changes the liquid crystal molecule in the liquid crystal layer, in order to change the light transmission of liquid crystal layer, to cooperate module backlight again the light source that provided with show image.Generally speaking, liquid crystal indicator includes a plurality of pixel cells, gate driver circuit and source electrode drive circuit.Source electrode drive circuit is in order to provide the plurality of data signal.Gate driver circuit comprises plural number level offset buffer, is used to provide a plurality of gate drive signals and writes to a plurality of pixel cells with control plurality of data signal.Therefore, gate driver circuit is the critical components of control data signal write operation.
Fig. 1 is the synoptic diagram of known gate driver circuit.As shown in Figure 1, for convenience of description, 100 of gate driver circuits show (N-1) level offset buffer 111, N level offset buffer 112 and (N+1) level offset buffer 113, wherein have only N level offset buffer 112 to show the built-in function unit structure.N level offset buffer 112 is in order to produce signal SGn according to first frequency CK1, second frequency CK2 and gate signal SGn-1.Signal SGn is fed into the respective pixel unit of pel array 101 via gate lines G Ln, in order to the write operation of the data-signal of control data line DLi.In addition, signal SGn is transferred to (N+1) level offset buffer 113 in addition, in order to as activation (N+1) level offset buffer 113 required open the beginning frequency signal.N level offset buffer 112 comprises pull-up unit 120, energy-storage units 135, buffer cell 140, drop-down unit 150, discharge cell 155 and control module 160.Energy-storage units 135 is to be used for carrying out charging procedure according to the signal SGn-1 that buffer cell 140 is received, and then produces drive control voltage VQn.Pull-up unit 120 is promptly according to drive control voltage VQn and draw the signal SGn of gate lines G Ln more than the first frequency CK1.Control module 160 comprises plurality of transistors, in order to produce control signal SCn according to signal SGn-1 and anti-phase second frequency CK2 in first frequency CK1.Discharge cell 155 promptly is used for according to control signal SCn, to energy-storage units 135 carry out discharge procedures with drop-down drive control voltage VQn to low supply voltage Vss.150 of drop-down unit according to control signal SCn with drop-down signal SGn to low supply voltage Vss.
Yet, in the running of gate driver circuit 100, except N level offset buffer 112 was triggered with the period of the signal SGn that produces the accurate position of high voltage, all the other time control signal SCn all in the accurate position of high voltage with drop-down unit 150 of activation and discharge cell 155.That is the transistor 151,156th of drop-down unit 150 and discharge cell 155 maintains conducting state for a long time, thus cause threshold voltage shift easily, and then reduce the fiduciary level and the serviceable life of gate driver circuit 100.
Summary of the invention
According to embodiments of the invention, it discloses a kind of grid drive circuit with high reliability, in order to provide a plurality of signals to a plurality of gate lines.This kind gate driver circuit comprises plural number level offset buffer, and N level offset buffer comprises pull-up unit, buffer cell, energy-storage units, discharge cell, the first drop-down unit, second drop-down unit and the control module.
Pull-up unit is electrically connected on the N gate line, in order to according to drive control voltage and first frequency the N signal is pulled to high levle voltage.Buffer cell is in order to receiving inputted signal.Energy-storage units is electrically connected on pull-up unit and buffer cell, is used for carrying out charging procedure according to input signal, to provide drive control voltage the supreme unit that draws.Discharge cell is electrically connected on energy-storage units, in order to according to control signal drive control voltage is pulled down to low supply voltage.The first drop-down unit is electrically connected on the N gate line in order to according to control signal the N signal is pulled down to low supply voltage.The second drop-down unit is electrically connected on the N gate line, in order to according to anti-phase second frequency in first frequency the N signal is pulled down to low supply voltage.Control module is electrically connected on the discharge cell and the first drop-down unit, in order to produce control signal according to the N signal.
According to embodiments of the invention, it also discloses a kind of grid drive circuit with high reliability, in order to provide a plurality of signals to a plurality of gate lines.This kind gate driver circuit comprises plural number level offset buffer, and N level offset buffer comprises pull-up unit, buffer cell, energy-storage units, first discharge cell, second discharge cell, the first drop-down unit and the second drop-down unit.
Pull-up unit is electrically connected on the N gate line, in order to according to drive control voltage and first frequency the N signal is pulled to high levle voltage.Buffer cell is in order to receiving inputted signal.Energy-storage units is electrically connected on pull-up unit and buffer cell, is used for carrying out charging procedure according to input signal, to provide drive control voltage the supreme unit that draws.First discharge cell is electrically connected on energy-storage units, is used for according to first frequency and N signal with drop-down drive control voltage.Second discharge cell is electrically connected on energy-storage units, in order to according to (N+1) signal drive control voltage is pulled down to low supply voltage.The first drop-down unit is electrically connected on the N gate line, in order to according to anti-phase second frequency in first frequency the N signal is pulled down to low supply voltage.The second drop-down unit is electrically connected on the N gate line, in order to according to (N+1) signal the N signal is pulled down to low supply voltage.
Description of drawings
Fig. 1 is the synoptic diagram of known gate driver circuit.
Fig. 2 is the synoptic diagram of the gate driver circuit of first embodiment of the invention.
Fig. 3 is the work coherent signal waveform synoptic diagram of the gate driver circuit of Fig. 2, and wherein transverse axis is a time shaft.
Fig. 4 is the synoptic diagram of the gate driver circuit of second embodiment of the invention.
Fig. 5 is the synoptic diagram of the gate driver circuit of third embodiment of the invention.
Fig. 6 is the synoptic diagram of the gate driver circuit of fourth embodiment of the invention.
Fig. 7 is the work coherent signal oscillogram of the gate driver circuit of Fig. 6, and wherein transverse axis is a time shaft.
Fig. 8 is the synoptic diagram of the gate driver circuit of fifth embodiment of the invention.
[primary clustering symbol description]
100,200,300,400,500,600 gate driver circuits
101,201 pel arrays
111,211,311,411,511,611 (N-1) level offset buffer
112,212,312,412,512,612 N level offset buffers
113,213,313,413,513,613 (N+1) level offset buffer
120,220,520 pull-up units, 135,235,535 energy-storage units
140,240,540 buffer cells, 150 drop-down unit
151,156 transistors, 155,255 discharge cells
160,260 control modules, 205,305,405 pixel cells
221,521 first switches, 236,536 electric capacity
241 diodes, 242,542 buffer transistors
256,551 second switches 261 and door
262 phase inverters, 263 rejection gates
265,560 first drop-down unit, 266,556 the 3rd switches
270,565 second drop-down unit, 271,561 the 4th switches
280,580 carry unit, 281,566 the 5th switches
550 first discharge cells, 555 second discharge cells
570 auxiliary units 571 the 6th switch
581 minions are closed the CK1 first frequency
CK2 second frequency DLi data line
GLn-1, GLn, GLn+1 gate line SCn control signal
SCn1, SCn2, SCn3, SCn4, SCn5 switch controlling signal
SGn-2, SGn-1, SGn, SGn+1, SGn+2 signal
STn-2, STn-1, STn, STn+1 open the beginning frequency signal
T1, T2, T3, T4, T5 period
The Vh1 first high voltage Vh2 second high voltage
VQn drive control voltage Vss low supply voltage
Embodiment
For making the present invention more apparent and understandable, hereinafter, cooperate appended graphic elaborating, but the embodiment that is provided not is the scope that contains in order to restriction the present invention especially exemplified by embodiment according to grid drive circuit with high reliability of the present invention.
Fig. 2 is the synoptic diagram of the gate driver circuit of first embodiment of the invention.As shown in Figure 2, gate driver circuit 200 comprises plural number level offset buffer, for convenience of description, 200 of gate driver circuits show (N-1) level offset buffer 211, N level offset buffer 212 and (N+1) level offset buffer 213, wherein have only N level offset buffer 212 to show the built-in function unit structure, all the other grades offset buffer system is analogous to N level offset buffer 212, so do not give unnecessary details in addition.(N-1) level offset buffer 211 is in order to provide signal SGn-1, and N level offset buffer 212 is in order to provide signal SGn, and (N+1) level offset buffer 213 is in order to provide signal SGn+1.Signal SGn-1 is fed into the pixel cell 205 of pel array 201 via gate lines G Ln-1, writes to pixel cell 205 in order to the data-signal of control data line DLi.Signal SGn is fed into the pixel cell 305 of pel array 201 via gate lines G Ln, writes to pixel cell 305 in order to the data-signal of control data line DLi.Signal SGn+1 is fed into the pixel cell 405 of pel array 201 via gate lines G Ln+1, writes to pixel cell 405 in order to the data-signal of control data line DLi.
N level offset buffer 212 comprises pull-up unit 220, energy-storage units 235, buffer cell 240, discharge cell 255, control module 260, the first drop-down unit 265 and the second drop-down unit 270.Pull-up unit 220 is electrically connected on gate lines G Ln, in order to according to drive control voltage VQn and draw the signal SGn of gate lines G Ln more than the first frequency CK1.Buffer cell 240 is electrically connected on (N-1) level offset buffer 211 receiving signal SGn-1, that is, N level offset buffer 212 with signal SGn-1 as activation required open the beginning frequency signal.Energy-storage units 235 is electrically connected on pull-up unit 220 and buffer cell 240, is used for carrying out charging procedure according to signal SGn-1, and drive control voltage VQn is provided the supreme unit 220 that draws according to this.Control module 260 is electrically connected on the discharge cell 255 and the first drop-down unit 265, in order to produce control signal SCn according to first frequency CK1 and gate signal SGn.Discharge cell 255 is electrically connected on energy-storage units 235, be used for according to control signal SCn carry out discharge procedures with drop-down drive control voltage VQn to low supply voltage Vss.The first drop-down unit 265 is electrically connected on gate lines G Ln, is used for according to control signal SCn with drop-down signal SGn to low supply voltage Vss.In addition, the second drop-down unit 270 also is electrically connected on gate lines G Ln, is used for according to anti-phase second frequency CK2 in first frequency CK1 with drop-down signal SGn to low supply voltage Vss.
In the embodiment of Fig. 2, buffer cell 240 comprises diode 241, pull-up unit 220 comprises first switch 221, energy-storage units 235 comprises electric capacity 236, discharge cell 255 comprises second switch 256, the first drop-down unit 265 comprises the 3rd switch 266, the second drop-down unit 270 and comprises the 4th switch 271, and control module 260 comprises and door (AND Gate) 261 and phase inverter (Inverter) 262.Diode 241 comprises positive terminal and negative pole end, and wherein positive terminal is electrically connected on (N-1) level offset buffer 211 to receive signal SGn-1, and negative pole end is electrically connected on electric capacity 236.First switch 221 comprises first end, second end and gate pole end, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on the negative pole end of diode 241, and second end is electrically connected on gate lines G Ln.Electric capacity 236 comprises first end and second end, and wherein first end is electrically connected on the gate terminal of first switch 221, and second end is electrically connected on second end of first switch 221.
Fig. 3 is the work coherent signal waveform synoptic diagram of the gate driver circuit of Fig. 2, and wherein transverse axis is a time shaft.In Fig. 3, basipetal signal is respectively first frequency CK1, second frequency CK2, signal SGn-1, signal SGn, signal SGn+1, drive control voltage VQn and control signal SCn.
As shown in Figure 3, in period T1, signal SGn-1 rises to high levle by low level, diode 241 thereby forward conducting make electric capacity 236 charging, in order to promote drive control voltage VQn to the first high voltage Vh1.At this moment, CK1 switches to low level because of first frequency, so control signal SCn also switches to low level, in order to end second switch 256 and the 3rd switch 266.In period T2, signal SGn-1 reduces to low level by high levle, diode 241 backward stops, making drive control voltage VQn is suspension joint voltage, switch to high levle because of first frequency CK1 this moment, so can drive control voltage VQn be pulled to the second high voltage Vh2 by the first high voltage Vh1 by the assembly electric capacity coupling of first switch 221, and first switch 221 of conducting according to this, SGn is pulled to high levle by low level with signal.Though first frequency CK1 is high levle in period T2, this moment, signal SGn was a high levle, so control signal SCn still maintains low level, and second switch 256 and the 3rd switch 266 also just continue in cut-off state.
In period T3, second frequency CK2 switches to high levle, and signal SGn is drop-down to be low level so 271 conductings of the 4th switch make, and then utilizes the coupling of electric capacity 236 that drive control voltage VQn is pulled down to low level.At this moment, though signal SGn is a low level, CK1 switches to low level because of first frequency, so control signal SCn still maintains low level, and second switch 256 and the 3rd switch 266 also just continue in cut-off state.In addition, 213 of offset buffers of (N+1) level utilize signal SGn as activation required open the beginning frequency signal, and in period T3, produce the signal SGn+1 of high levle.
In period T4, second frequency CK2 switches to low level ends the 4th switch 271.At this moment, first frequency CK1 switches to high levle, the signal SGn that cooperates low level, make control signal SCn switch to high levle, in order to conducting second switch 256 and the 3rd switch 266, and then drop-down drive control voltage VQn is to low supply voltage Vss, and drop-down signal SGn is to low supply voltage Vss.In period T5, first frequency CK1 switches to low level makes control signal SCn switch to low level, and then second switch 256 and the 3rd switch 266 are ended.At this moment, second frequency CK2 switches to high levle, and in order to conducting the 4th switch 271, and then drop-down signal SGn is to low supply voltage Vss.Thereafter, continuing at signal SGn under the state of low level, be periodically to carry out the circuit operation that is set forth in period T4 and the T5, that is the 3rd switch 266 and the 271 mutual conductings of the 4th switch is to keep signal SGn at low level.So the mutual conducting mode of operation by the 3rd switch 266 and the 4th switch 271 can significantly reduce threshold voltage shift, and then the fiduciary level and the serviceable life of improving gate driver circuit 200.Please note, though in period T5, second switch 256 is a suspension joint voltage by making drive control voltage VQn, but because drive control voltage VQn periodically is pulled down to low supply voltage Vss, so this moment, drive control voltage VQn can't surpass critical voltage, thereby did not influence the circuit operate as normal.
Fig. 4 is the synoptic diagram of the gate driver circuit of second embodiment of the invention.As shown in Figure 4, gate driver circuit 300 comprises plural number level offset buffer, and for convenience of description, gate driver circuit 300 still only shows (N-1) level offset buffer 311, N level offset buffer 312 and (N+1) level offset buffer 313.In N level offset buffer 312, buffer cell 240 comprises buffer transistor 242, and control module 260 comprises rejection gate (NOR Gate) 263.Buffer transistor 242 comprises first end, second end and gate pole end, and wherein first end is electrically connected on (N-1) level offset buffer 311 to receive signal SGn-1, and gate terminal is electrically connected on first end, and second end is electrically connected on first end of electric capacity 236.Buffer transistor 242 is to be thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor.Rejection gate 263 comprises first input end, second input end and output terminal, wherein first input end is in order to receive second frequency CK2, second input end is electrically connected on second end of first switch 221, output terminal is electrically connected on the gate terminal of second switch 256 and the 3rd switch 266, in order to output control signal SCn.All the other grades offset buffer is in like manner analogized, except above-mentioned points, the internal electrical annexation of each grade offset buffer all is analogous to N level offset buffer 212 shown in Figure 2 basically, and the work coherent signal waveform of gate driver circuit 300 also is same as signal waveform shown in Figure 3, so repeat no more.
Fig. 5 is the synoptic diagram of the gate driver circuit of third embodiment of the invention.As shown in Figure 5, gate driver circuit 400 comprises plural number level offset buffer, and for convenience of description, gate driver circuit 400 still only shows (N-1) level offset buffer 411, N level offset buffer 412 and (N+1) level offset buffer 413.Compared to gate driver circuit shown in Figure 4 300, (N-1) level offset buffer 411 opens beginning frequency signal STn-1 in order to provide in addition, N level offset buffer 412 opens beginning frequency signal STn in order to provide in addition, and (N+1) level offset buffer 413 opens beginning frequency signal STn+1 in order to provide in addition.The waveform that opens beginning frequency signal STn-1 comes down to be same as the waveform of signal SGn-1, the waveform that opens beginning frequency signal STn comes down to be same as the waveform of signal SGn, and the waveform that opens beginning frequency signal STn+1 comes down to be same as the waveform of signal SGn+1.Also comprise carry unit 280 compared to N level offset buffer shown in Figure 4 312, the N level offset buffers 412.Carry unit 280 comprises the 5th switch 281, is to be used for producing according to drive control voltage VQn and first frequency CK1 opening beginning frequency signal STn and being fed into (N+1) level offset buffer 413.The 5th switch 281 comprises first end, second end and gate terminal, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on first end of electric capacity 236, and second end opens beginning frequency signal STn to the (N+1) level offset buffer 413 in order to output.The 5th switch 281 is to be thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor.In addition, first end of buffer transistor 242 then is electrically connected on (N-1) level offset buffer 411 and opens beginning frequency signal STn-1 with reception.All the other grades offset buffer is in like manner analogized, except above-mentioned points, the internal electrical annexation of each grade offset buffer all is analogous to N level offset buffer 312 shown in Figure 4 basically, and the work coherent signal waveform of gate driver circuit 400 also is same as signal waveform shown in Figure 3, so repeat no more.
Fig. 6 is the synoptic diagram of the gate driver circuit of fourth embodiment of the invention.As shown in Figure 6, gate driver circuit 500 comprises plural number level offset buffer, for convenience of description, gate driver circuit 500 still only shows (N-1) level offset buffer 511, N level offset buffer 512 and (N+1) level offset buffer 513, wherein have only N level offset buffer 512 to show the built-in function unit structure, all the other grades offset buffer is to be analogous to N level offset buffer 512, so do not give unnecessary details in addition.(N-1) level offset buffer 511 is in order to provide signal SGn-1, and N level offset buffer 512 is in order to provide signal SGn, and (N+1) level offset buffer 513 is in order to provide signal SGn+1.
N level offset buffer 512 comprises pull-up unit 520, energy-storage units 535, buffer cell 540, first discharge cell 550, second discharge cell 555, auxiliary unit 570, the first drop-down unit 560 and the second drop-down unit 565.Pull-up unit 520 is electrically connected on gate lines G Ln, in order to according to drive control voltage VQn and draw the signal SGn of gate lines G Ln more than the first frequency CK1.Buffer cell 540 is electrically connected on (N-1) level offset buffer 511 receiving signal SGn-1, that is, N level offset buffer 512 be with signal SGn-1 as activation required open the beginning frequency signal.Energy-storage units 535 is electrically connected on pull-up unit 520 and buffer cell 540, is used for carrying out charging procedure according to signal SGn-1, and drive control voltage VQn is provided the supreme unit 520 that draws according to this.First discharge cell 550 is electrically connected on energy-storage units 535, is used for carrying out discharge procedures with drop-down drive control voltage VQn according to first frequency CK1 and gate signal SGn.Second discharge cell 555 also is electrically connected on energy-storage units 535, be used for according to signal SGn+1 carry out discharge procedures with drop-down drive control voltage VQn to low supply voltage Vss.
The first drop-down unit 560 is electrically connected on gate lines G Ln, is used for according to anti-phase second frequency CK2 in first frequency CK1 with drop-down signal SGn to low supply voltage Vss.The second drop-down unit 565 also is electrically connected on gate lines G Ln, is used for according to signal SGn+1 with drop-down signal SGn to low supply voltage Vss.Auxiliary unit 570 is electrically connected between the gate lines G Ln and first discharge cell 550, is used for according to the auxiliary electrically connect between the first frequency CK1 control gate line GLn and first discharge cell 550.
In the embodiment of Fig. 6, buffer cell 540 comprises buffer transistor 542, pull-up unit 520 comprises first switch 521, energy-storage units 535 comprises electric capacity 536, first discharge cell 550 comprises second switch 551, the second discharge cells 555 and comprises the 3rd switch 556, the first drop-down unit 560 and comprise the 4th switch 561, the second drop-down unit 565 comprises the 5th switch 566, and auxiliary unit 570 comprises the 6th switch 571.Buffer transistor 542 comprises first end, second end and gate pole end, and wherein first end is electrically connected on (N-1) level offset buffer 511 to receive signal SGn-1, and gate terminal is electrically connected on first end, and second end is electrically connected on electric capacity 536.Buffer transistor 542 is thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor.In another embodiment, buffer cell 540 is to comprise diode, and the positive terminal of diode is electrically connected on (N-1) level offset buffer 511 with reception signal SGn-1, and the negative pole end of diode is electrically connected on electric capacity 536.
The 4th switch 561 comprises first end, second end and gate pole end, and wherein first end is electrically connected on second end of first switch 521, and gate terminal is in order to receive second frequency CK2 as switch controlling signal SCn3, and second end is in order to receive low supply voltage Vss.The 5th switch 566 comprises first end, second end and gate pole end, wherein first end is electrically connected on second end of first switch 521, gate terminal is electrically connected on gate lines G Ln+1 to receive signal SGn+1 as switch controlling signal SCn4, and second end is in order to receive low supply voltage Vss.The 6th switch 571 comprises first end, second end and gate pole end, and wherein first end is electrically connected on second end of first switch 521, and gate terminal is in order to receive first frequency CK1 as switch controlling signal SCn5, and second end is electrically connected on second end of second switch 551.First switch, 521 to the 6th switches 571 are to be thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor.
Fig. 7 is the work coherent signal oscillogram of the gate driver circuit of Fig. 6, and wherein transverse axis is a time shaft.In Fig. 7, basipetal signal is respectively first frequency CK1, second frequency CK2, signal SGn-1, signal SGn, signal SGn+1, drive control voltage VQn, switch controlling signal SCn1, switch controlling signal SCn2, switch controlling signal SCn3, switch controlling signal SCn4 and switch controlling signal SCn5.
As shown in Figure 7, in period T1, SGn-1 rises to high levle by low level because of signal, and buffer transistor 542 switches to conducting state and makes electric capacity 536 chargings, in order to promote drive control voltage VQn to the first high voltage Vh1.At this moment, switch to low level because of first frequency CK1 again, and second frequency CK2 switches to high levle, that is switch controlling signal SCn1 and SCn5 all switch to low level, switch controlling signal SCn3 then switches to high levle, so second switch 551 and the 6th switch 571 all switch to cut-off state, the 4th switch 561 then switches to conducting state to keep the low level of signal SGn.In addition, because signal SGn+1 maintains low level, so switch controlling signal SCn2 and SCn4 still maintain low level, with so that the 3rd switch 556 and the 5th switch 566 remain on cut-off state.
In period T2, SGn-1 reduces to low level by high levle because of signal, buffer transistor 542 switches to cut-off state, making drive control voltage VQn is suspension joint voltage, again because of first frequency CK1 switches to high levle, so can drive control voltage VQn be pulled to the second high voltage Vh2 by the first high voltage Vh1 by the assembly electric capacity coupling of first switch 521, and first switch 521 of conducting according to this, SGn is pulled to high levle by low level with signal.At this moment, second frequency CK2 switches to low level and signal SGn+1 maintains low level, that is switch controlling signal SCn3 switches to low level, and switch controlling signal SCn2 and SCn4 maintain low level, and therefore the 3rd switch 556, the 4th switch 561 and the 5th switch 566 are all in cut-off state.In addition, though switch controlling signal SCn1 and SCn5 all switch to high levle with first frequency CK1, because drive control voltage VQn and gate signal SGn are high levle, so second switch 551 and the 6th switch 571 all maintain cut-off state.
In period T3,513 of offset buffers of (N+1) level utilize signal SGn as activation required open the beginning frequency signal, and produce the signal SGn+1 of high levle.At this moment, CK2 switches to high levle because of second frequency, and promptly switch controlling signal SCn3 switches to high levle, so 561 conductings of the 4th switch make signal SGn be pulled down to low supply voltage Vss.Switch to high levle because of signal SGn+1 again, that is switch controlling signal SCn2 and SCn4 all switch to high levle, so 556 conductings of the 3rd switch make drive control voltage VQn be pulled down to low supply voltage Vss, and 566 conductings of the 5th switch make signal SGn be pulled down to low supply voltage Vss.In addition, first frequency CK1 switches to low level, and promptly switch controlling signal SCn1 and SCn5 all switch to low level, so second switch 551 and the 6th switch 571 still maintain cut-off state.
In period T4, CK2 switches to low level because of second frequency, and promptly switch controlling signal SCn3 switches to low level, so the 4th switch 561 switches to cut-off state.Again because of signal SGn+1 switches to low level, that is switch controlling signal SCn2 and SCn4 all switch to low level, so the 3rd switch 556 and the 5th switch 566 all switch to cut-off state.In addition, first frequency CK1 switches to high levle, and promptly switch controlling signal SCn1 and SCn5 all switch to high levle, so second switch 551 and the 6th switch 571 all switch to conducting state, in order to keep drive control voltage VQn in low level.Note that the 6th switch 571 is to be used for providing between second end of second switch 551 and gate line SGn auxiliary electrically connect to improve fiduciary level, omitting the 6th switch 571 can't influence the circuit operate as normal.
In period T5, CK1 switches to low level because of first frequency, so second switch 551 and the 6th switch 571 all switch to cut-off state.Again because of signal SGn+1 maintains low level, that is switch controlling signal SCn2 and SCn4 all maintain low level, so the 3rd switch 556 and the 5th switch 566 all maintain cut-off state.In addition, second frequency CK2 switches to high levle, and promptly switch controlling signal SCn3 switches most high levle, so 561 conductings of the 4th switch make signal SGn be pulled down to low supply voltage Vss.Thereafter, continuing at signal SGn under the state of low level, be periodically to carry out the circuit operation that is set forth in period T4 and the T5, that is the 4th switch 561 and second switch 551 mutual conductings is with drop-down signal SGn and drive control voltage VQn.So the mutual conducting mode of operation by the 4th switch 561 and second switch 551 can significantly reduce threshold voltage shift, and then the fiduciary level and the serviceable life of improving gate driver circuit 500.
Fig. 8 is the synoptic diagram of the gate driver circuit of fifth embodiment of the invention.As shown in Figure 8, gate driver circuit 600 comprises plural number level offset buffer, and for convenience of description, gate driver circuit 600 still only shows (N-1) level offset buffer 611, N level offset buffer 612 and (N+1) level offset buffer 613.Compared to gate driver circuit shown in Figure 6 500, (N-1) level offset buffer 611 opens beginning frequency signal STn-1 in order to provide in addition, N level offset buffer 612 also opens beginning frequency signal STn in order to provide, and (N+1) level offset buffer 613 also opens beginning frequency signal STn+1 in order to provide.Each waveform that opens the beginning frequency signal comes down to be same as the waveform of corresponding signal.Also comprise carry unit 580 compared to N level offset buffer shown in Figure 6 512, the N level offset buffers 612.Carry unit 580 comprises minion and closes 581, is to be used for producing according to drive control voltage VQn and first frequency CK1 opening beginning frequency signal STn and being fed into (N+1) level offset buffer 613.Minion is closed 581 and is comprised first end, second end and gate pole end, and wherein first end is in order to receive first frequency CK1, and gate terminal is electrically connected on first end of electric capacity 536, and second end opens beginning frequency signal STn to the (N+1) level offset buffer 613 in order to output.It is to be thin film transistor (TFT), metal-oxide half field effect transistor or junction field effect transistor that minion closes 581.In addition, first end of buffer transistor 542 then is electrically connected on (N-1) level offset buffer 611 and opens beginning frequency signal STn-1 with reception.All the other grades offset buffer is in like manner analogized, except above-mentioned points, the internal electrical annexation of each grade offset buffer all is analogous to N level offset buffer 512 shown in Figure 6 basically, and the work coherent signal waveform of gate driver circuit 600 also is same as signal waveform shown in Figure 7, so repeat no more.
From the above, in the circuit working of the offset buffer of gate driver circuit of the present invention, be to utilize alternate pull-down operation mechanism keeping the signal of low level, thus the transistor threshold voltage shift can significantly be reduced, and then improve the fiduciary level and the serviceable life of gate driver circuit.
Though the present invention with embodiment openly as above; right its is not in order to limit the present invention; any have a technical field of the invention know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (11)
1. grid drive circuit with high reliability, in order to provide a plurality of signals to a plurality of gate lines, this gate driver circuit comprises plural number level offset buffer, and a N level offset buffer of those grades offset buffer comprises:
One pull-up unit is electrically connected on a N gate line of those gate lines, in order to according to a drive control voltage and a first frequency one N signal of those signals is pulled to a high levle voltage;
One buffer cell is in order to receive an input signal;
One energy-storage units is electrically connected on this pull-up unit and this buffer cell, is used for carrying out a charging procedure to provide this drive control voltage to this pull-up unit according to this input signal;
One discharge cell is electrically connected on this energy-storage units, in order to according to a control signal this drive control voltage is pulled down to a low supply voltage;
One first drop-down unit is electrically connected on this N gate line, in order to according to this control signal this N signal is pulled down to this low supply voltage;
One second drop-down unit is electrically connected on this N gate line, in order to according to an anti-phase second frequency in this first frequency this N signal is pulled down to this low supply voltage; With
One control module is electrically connected on this discharge cell and this first drop-down unit, in order to produce this control signal according to this N signal.
2. gate driver circuit as claimed in claim 1 is characterized in that,
This pull-up unit comprises a transistor, and this transistor comprises:
One first end is in order to receive this first frequency;
One gate terminal is electrically connected on this energy-storage units to receive this drive control voltage; With
One second end is electrically connected on this N gate line;
This energy-storage units comprises an electric capacity;
This discharge cell comprises a transistor, and this transistor comprises:
One first end is electrically connected on this energy-storage units;
One gate terminal is electrically connected on this control module to receive this control signal; With
One second end is in order to receive this low supply voltage.
3. gate driver circuit as claimed in claim 1 is characterized in that this buffer cell comprises a transistor, and this transistor comprises:
One first end is electrically connected on one (N-1) level offset buffer to receive one (N-1) signal;
One gate terminal is electrically connected on this first end; With
One second end is electrically connected on this energy-storage units;
Wherein this input signal is this (N-1) signal.
4. gate driver circuit as claimed in claim 1 is characterized in that this buffer cell comprises
One diode, this diode comprises:
One positive terminal is electrically connected on one (N-1) level offset buffer to receive one (N-1) signal; With
One negative pole end is electrically connected on this energy-storage units;
Wherein this input signal is to be this (N-1) signal.
5. gate driver circuit as claimed in claim 1 is characterized in that, this first drop-down unit comprises a transistor, and this transistor comprises:
One first end is electrically connected on this N gate line;
One gate terminal is electrically connected on this control module to receive this control signal; With
One second end is in order to receive this low supply voltage.
6. gate driver circuit as claimed in claim 1 is characterized in that, this second drop-down unit comprises a transistor, and this transistor comprises:
One first end is electrically connected on this N gate line;
One gate terminal is in order to receive this second frequency; With
One second end is in order to receive this low supply voltage.
7. gate driver circuit as claimed in claim 1 is characterized in that, this control module comprises:
One with the door, comprise:
One first input end is in order to receive this first frequency;
One second input end; With
One output terminal is in order to export this control signal; With
One phase inverter comprises:
One input end is electrically connected on this N gate line; With
One output terminal, be electrically connected on this with the door second input end.
8. gate driver circuit as claimed in claim 1 is characterized in that, this control module comprises a rejection gate NOR Gate, and this rejection gate comprises:
One first input end is in order to receive this second frequency;
One second input end is electrically connected on this N gate line; And
One output terminal is in order to export this control signal.
9. gate driver circuit as claimed in claim 1, it is characterized in that, this N level offset buffer also comprises: a carry unit, be electrically connected on this energy-storage units, be used for producing a N according to this drive control voltage and this first frequency and open the beginning frequency signal, it is a buffer cell that is fed to one (N+1) level offset buffer that this N opens the beginning frequency signal.
The carry unit of this N level offset buffer comprises a transistor, and this transistor comprises:
One first end is used for receiving this first frequency;
One gate terminal is electrically connected on this energy-storage units to receive this drive control voltage; With
One second end is electrically connected on the buffer cell of this (N+1) level offset buffer.
The buffer cell of this N level offset buffer comprises a transistor, and this transistor comprises:
One first end is used for receiving (N-1) that the carry unit of one (N-1) level offset buffer produced and opens the beginning frequency signal;
One gate terminal is electrically connected on this first end; With
One second end is electrically connected on this energy-storage units;
Wherein this input signal is to open the beginning frequency signal for this (N-1).
10. grid drive circuit with high reliability, in order to provide a plurality of signals to a plurality of gate lines, this gate driver circuit comprises plural number level offset buffer, and a N level offset buffer of those grades offset buffer comprises:
One pull-up unit is electrically connected on a N gate line of those gate lines, in order to according to a drive control voltage and a first frequency one N signal of those signals is pulled to a high levle voltage;
One buffer cell is in order to receive an input signal;
One energy-storage units is electrically connected on this pull-up unit and this buffer cell, is used for carrying out a charging procedure to provide this drive control voltage to this pull-up unit according to this input signal;
One first discharge cell is electrically connected on this energy-storage units, is used for according to this first frequency and this N signal with drop-down this drive control voltage;
One second discharge cell is electrically connected on this energy-storage units, in order to one (N+1) signal according to those signals this drive control voltage is pulled down to a low supply voltage;
One first drop-down unit is electrically connected on this N gate line, in order to according to an anti-phase second frequency in this first frequency this N signal is pulled down to this low supply voltage; With
One second drop-down unit is electrically connected on this N gate line, in order to according to this (N+1) signal this N signal is pulled down to this low supply voltage.
11. gate driver circuit as claimed in claim 10 is characterized in that, this first discharge cell comprises a transistor, and this transistor comprises:
One first end is electrically connected on this energy-storage units;
One gate terminal is in order to receive this first frequency; With
One second end is electrically connected on this N gate line.
This second discharge cell comprises a transistor, and this transistor comprises:
One first end is electrically connected on this energy-storage units;
One gate terminal is in order to receive this (N+1) signal; With
One second end is in order to receive this low supply voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910118908A CN101826310A (en) | 2009-03-06 | 2009-03-06 | High reliability grid drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910118908A CN101826310A (en) | 2009-03-06 | 2009-03-06 | High reliability grid drive circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101826310A true CN101826310A (en) | 2010-09-08 |
Family
ID=42690207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910118908A Pending CN101826310A (en) | 2009-03-06 | 2009-03-06 | High reliability grid drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101826310A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102314828A (en) * | 2011-06-29 | 2012-01-11 | 友达光电股份有限公司 | Gate drive circuit |
| CN103594067A (en) * | 2013-11-28 | 2014-02-19 | 矽创电子股份有限公司 | Drive circuit of display panel |
| CN104700769A (en) * | 2015-04-09 | 2015-06-10 | 京东方科技集团股份有限公司 | Shifting register unit, gate driving device and display device |
| CN109064981A (en) * | 2018-07-20 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit and display panel and display device including it |
-
2009
- 2009-03-06 CN CN200910118908A patent/CN101826310A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102314828A (en) * | 2011-06-29 | 2012-01-11 | 友达光电股份有限公司 | Gate drive circuit |
| CN102314828B (en) * | 2011-06-29 | 2014-05-14 | 友达光电股份有限公司 | Gate drive circuit |
| CN103594067A (en) * | 2013-11-28 | 2014-02-19 | 矽创电子股份有限公司 | Drive circuit of display panel |
| CN103594067B (en) * | 2013-11-28 | 2016-08-17 | 矽创电子股份有限公司 | The drive circuit of display floater |
| CN104700769A (en) * | 2015-04-09 | 2015-06-10 | 京东方科技集团股份有限公司 | Shifting register unit, gate driving device and display device |
| US9792868B2 (en) | 2015-04-09 | 2017-10-17 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving device and display device |
| CN109064981A (en) * | 2018-07-20 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit and display panel and display device including it |
| CN109064981B (en) * | 2018-07-20 | 2019-09-17 | 深圳市华星光电技术有限公司 | GOA circuit and display panel and display device including it |
| WO2020015111A1 (en) * | 2018-07-20 | 2020-01-23 | 深圳市华星光电技术有限公司 | Goa circuit, display panel comprising same, and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102054426B (en) | Shift buffer circuit | |
| CN102063858B (en) | Shift register circuit | |
| CN102184697B (en) | Shift buffer circuit | |
| CN101853705B (en) | Shift register circuit | |
| CN104299594B (en) | Shifting register unit, gate driving circuit and display device | |
| CN101533623A (en) | Gate drive for inhibiting drift of a critical voltage | |
| CN104835442B (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN102592561B (en) | Gate drive circuit | |
| CN105513525B (en) | Shift register cell, shift register, gate driving circuit and display device | |
| CN101777386B (en) | Shift register circuit | |
| CN104867438B (en) | Shift register cell and its driving method, shift register and display device | |
| CN102314828B (en) | Gate drive circuit | |
| CN104505050B (en) | Scanning driving circuit for oxide semiconductor thin film transistor | |
| TWI406218B (en) | High-reliability gate driving circuit | |
| CN102024415B (en) | shift register circuit | |
| CN104409055B (en) | Scanning driving circuit for oxide semiconductor thin film transistor | |
| CN102956269A (en) | Shift register | |
| CN104732939A (en) | Shifting register, grid drive circuit, display device and grid drive method | |
| CN102651187B (en) | Shift register unit circuit, shift register, array substrate and liquid crystal displayer | |
| CN204102544U (en) | Shift register cell, gate driver circuit and display device | |
| CN109285504A (en) | Shift register cell and its driving method, gate driving circuit | |
| CN101510416B (en) | Grid drive circuit with high reliability | |
| CN101976581A (en) | Shift register circuit | |
| CN103151013B (en) | Gate driver circuit | |
| CN102034423A (en) | Shift register circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20100908 |