CN101820267B - Automatic correction circuit and method of capacitor - Google Patents
Automatic correction circuit and method of capacitor Download PDFInfo
- Publication number
- CN101820267B CN101820267B CN 200910126012 CN200910126012A CN101820267B CN 101820267 B CN101820267 B CN 101820267B CN 200910126012 CN200910126012 CN 200910126012 CN 200910126012 A CN200910126012 A CN 200910126012A CN 101820267 B CN101820267 B CN 101820267B
- Authority
- CN
- China
- Prior art keywords
- capacitance
- switch
- coupled
- building
- those
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention relates to an automatic correction circuit and a method of a capacitor. The automatic correction circuit comprises a reference capacitor, a capacitor array, a correction circuit and a counting unit, wherein the capacitor array comprises a target capacitor and a plurality of comprehension capacitors. The invention corrects the capacitor array by utilizing an average parameter value generated by multiple corrections so that the capacitor array approaches to the reference capacitor. The invention decides the values of the comprehension capacitors to be connected in parallel to the target capacitor by utilizing the average value of multiple corrections so that errors caused by single correction can be avoided, and correction errors caused by a reference voltage error or noise can be reduced.
Description
Technical field
The present invention relates to a kind of automatic calibration circuit and method of electric capacity, particularly relate to a kind of automatic calibration circuit and method that reduces the electric capacity of reference voltage correction error that error causes.
Background technology
Continuous convergence type (successive approximation type) analog-digital converter (analog to digital converter; ADC) can have accurate electric resistance array or capacitor array usually, its resistance or electric capacity can be arranged with the mode of binary bit weight (binary-weighted).With the capacitor array is example, and except the electric capacity of highest order unit, the capacitance of each electric capacity can be 1/2 of another electric capacity, successively decreases in regular turn, forms the capacitor array of binary bit weight.When capacitance was inaccurate, the kinematic nonlinearity of analog-digital converter (dynamical Nonlinearity) error can increase thereupon, causes the transformed error of analog and digital signal.
In integrated circuit manufacture process; The electric capacity precision can only reach the degree that a 10bit left side has; Promote accuracy; Common practices is via repeatedly processing procedure is extremely minimum the capacitance error correction, or utilizes electricity to penetrate excision (Laser trimming) and adjust capacitance size, yet these methods are not only expensive but also time-consuming.
Therefore; Formerly can utilize automatic method of correcting to come the corrective capacity array in the technology; Building-out capacitor corresponding to the respective capacitances error amount can be set in the capacitor array, utilize reference voltage and reference capacitance to carry out the comparison of capacitance then, why with the capacitance that determines required compensation.Yet, in trimming process,, the kinematic nonlinearity error of analog-digital converter is enlarged if reference voltage is not accurate enough or when having excessive noise, will cause correction error.
Summary of the invention
The present invention provides a kind of automatic calibration circuit and method of electric capacity, repeats repeatedly electric capacity correction program to be compensated the mean value of electric capacity, reduces the correction error that is caused because of the reference voltage error by this.
The object of the invention and solve its technical problem and adopt following technical scheme to realize.For achieving the above object, the automatic calibration circuit according to the present invention proposes a kind of electric capacity comprises a reference capacitance, a capacitor array, a correcting circuit and a counting unit.Wherein, Reference capacitance is coupled between a common terminal and the first input end, and capacitor array one target capacitance and a plurality of building-out capacitor, target capacitance are coupled between this common terminal and one second input; One end of above-mentioned building-out capacitor is coupled to common terminal; The other end couples one first switches set, and wherein first switches set has a plurality of first switches, is respectively coupled between the building-out capacitor and second input.
Correcting circuit is coupled to reference capacitance and capacitor array; The capacitance of correcting circuit comparison reference capacitance and capacitor array to be producing one group of parameter value, in order to the conducting state that determines first switch in first switches set with the parallelly connected relation between adjustment building-out capacitor and the mark electric capacity to adjust the capacitance of capacitor array.
Counting unit is coupled to a correcting circuit and a switches set; In order to keep in parameter value corresponding to the conducting state of first switch; Wherein correcting circuit repeats the capacitance of comparison reference capacitance and capacitor array and produces many group parameter values; The mean value that this counting unit adds up those parameter values and calculates those parameter values to be exporting a final argument value, in order to the conducting state that determines first switch in first switches set capacitance with the adjustment capacitor array.Wherein the capacitance of building-out capacitor is respectively 2
i* C, wherein i is the index value of those building-out capacitors, and i equals positive integer and 0≤i≤(N-1), N is the number of those building-out capacitors, and C is the position of minimum capacitance in those building-out capacitors.
In an embodiment of the present invention, above-mentioned correcting circuit comprises a comparator, a second switch device, a second switch group and an ON-OFF control circuit.Wherein, a positive input terminal of comparator is coupled to an earth terminal, and a negative input end of comparator is coupled to this common terminal; Second switch couples between the positive input terminal and negative input end of comparator; The second switch group is coupled between first input end, second input, a reference voltage and the earth terminal.ON-OFF control circuit is coupled to output, second switch, first switches set and the second switch group of comparator; And in order to control second switch, first switches set and second switch group, wherein ON-OFF control circuit according to the output of comparator generation corresponding to those parameter values of the conducting state of first switch to adjust the capacitance of this capacitor array.
In an embodiment of the present invention; Above-mentioned second switch group comprises one the 3rd switch and one the 4th switch; Wherein an end of the 3rd switch is coupled to first input end; The other end of the 3rd switch is coupled to reference voltage or earth terminal, and an end of the 4th switch is coupled to second input, and the other end of the 4th switch is coupled to reference voltage or earth terminal.
In an embodiment of the present invention, above-mentioned counting unit comprises add up a buffer and a shift registor.The buffer that adds up is coupled to ON-OFF control circuit, in order to those parameter values that add up; Shift registor is coupled to and adds up between the buffer and first switches set, in order to the mean value that calculates those parameter values to export this final argument value.
In an embodiment of the present invention; Above-mentioned automatic calibration circuit is to utilize the following step to produce this parameter value; Comprise: conducting first switch is so that the positive input terminal of comparator and negative input end ground connection; Switch the second switch group so that first input end is coupled to reference voltage with to the reference capacitance charging, and make second input be coupled to earth terminal; Open (turn off) first switch to form open circuit, switch the second switch group so that first input end is coupled to earth terminal, and make second input be coupled to reference voltage so that target capacitance is charged; And according to the output of comparator, the conducting state that determines first switch in regular turn is with the parallelly connected relation of adjustment building-out capacitor with target capacitance.Wherein, the conducting state of first switch is corresponding to this parameter value.
The object of the invention and solve its technical problem and also adopt following technical scheme to realize.For achieving the above object; From another viewpoint; The present invention proposes a kind of method of automatic corrective capacity, is suitable for to adjust a capacitor array, makes the capacitance of capacitor array level off to a reference capacitance; Capacitor array comprises a target capacitance and a plurality of building-out capacitor, and said method comprises the following steps: that the capacitance of (a) comparison capacitor array and reference capacitance is to export one group of parameter value; (b) according to the capacitance of the parallelly connected relation between parameter value adjustment building-out capacitor and the target capacitance with the adjustment capacitor array; (c) repeat above-mentioned steps (a) and (b) organize parameter values more to produce; (d) add up the mean value of parameter value and calculating parameter value to export a final argument value; And (e) according to the final argument value, the parallelly connected relation between decision building-out capacitor and the target capacitance.Wherein the capacitance of building-out capacitor is respectively 2
i* C, wherein i is the index value of those building-out capacitors, and i equals positive integer and 0≤i≤(N-1), N is the number of those building-out capacitors, and C is the position of minimum capacitance in those building-out capacitors.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme; The automatic calibration circuit of electric capacity of the present invention and method have advantage and beneficial effect at least: utilization of the present invention electric capacity is repeatedly proofreaied and correct the mean parameter value produced and is come capacitor array is proofreaied and correct, and makes it level off to required reference capacitance.Because the present invention utilizes repeatedly the mean value of proofreading and correct to decide the building-out capacitor value of required parallel connection, therefore can avoid the error that causes because of single calibration, also can reduce simultaneously because of reference voltage error or correction error that noise caused.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of specification, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 is the automatic calibration circuit sketch map according to the electric capacity of first embodiment of the invention.
Fig. 2 A is according to the capacitor array 130 of present embodiment and the thin portion circuit diagram of reference capacitance 140.
Fig. 2 B is the electric capacity correction program flow chart according to first embodiment of the invention.
Fig. 3 is the sketch map according to the gradual analog-digital converter of second embodiment of the invention.
Fig. 4 is the method flow diagram according to the automatic corrective capacity of third embodiment of the invention.
100: automatic calibration circuit 110,310: ON-OFF control circuit
120: counting unit 122,322: shift registor
124,324: buffer 130 adds up: capacitor array
134: building-out capacitor array 140: reference capacitance
150,255,350: switches set 160,360: comparator
331,332: capacitor array SW
OP, SW
P1, SW
P2, SW
1～SW
N: switch
SW
A1～SW
A4, SW
B1～SW
B3: switch P
11: common terminal
P
1: first input end P
2: second input
N: bit is counted GND: earth terminal
V
REF: reference voltage V
OUT: output voltage
C
T, C
A, C
B: target capacitance C
1～C
N, C
B1～C
B3, C
A1～C
A4: building-out capacitor
C
REF: reference capacitance C
C: electric capacity
P
3: the 3rd input V
IN: input voltage
SW
31, SW
32, SW
33: switch S 210～S294: step
S410～S450: step
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment, automatic calibration circuit and its embodiment of method, structure, step, characteristic and the effect thereof of the electric capacity that proposes according to the present invention is elaborated.
First embodiment
Please with reference to shown in Figure 1, be sketch map according to the automatic calibration circuit of the electric capacity of first embodiment of the invention.The automatic calibration circuit 100 of first embodiment of the invention comprises ON-OFF control circuit 110, counting unit 120, capacitor array 130, reference capacitance 140, switches set 150, comparator 160 and switch SW
OP
Still comprise target capacitance 132 and building-out capacitor array 134 in the above-mentioned capacitor array 130, wherein have a plurality of building-out capacitors (not illustrating) in the building-out capacitor array 134, can be used to the capacitance of parallelly connected target capacitance 132 with adjustment capacitor array 130.
One end of above-mentioned reference capacitance 140 is coupled to common terminal P
11, the other end is coupled to first input end P
1One end of target capacitance 132 is coupled to common terminal P
11, the other end is coupled to the second input P
2One end of building-out capacitor 134 is coupled to common terminal P equally
11, the other end then is coupled to the second input P via switch (not illustrating)
2
The positive input terminal of above-mentioned comparator 160 is coupled to earth terminal GND, and negative input end is coupled to common terminal P
11, the output of comparator 160 then is coupled to ON-OFF control circuit 110.
Above-mentioned switch SW
OPBe coupled between the positive input terminal and negative input end of comparator 160, and be controlled by ON-OFF control circuit 110.
Then comprise switch SW in the above-mentioned switches set 150
P1With SW
P2Switch SW in this switches set 150
P1An end be coupled to first input end P
1, the other end then can be at reference voltage V
REFAnd switch between the earth terminal GND; Switch SW in the switches set 150
P2An end be coupled to the second input P
2, the other end then can be at reference voltage V
REFAnd switch switch SW between the earth terminal GND
P2, SW
P1All be controlled by ON-OFF control circuit 110.
Said counting unit 120 couples switch control unit 110 and capacitor array 130; Can be used to the parameter value that storage switch control circuit 110 is exported, and the mean value that calculates its parameter value comes the parallelly connected relation between control compensation capacitor array 134 and the target capacitance 132.
Above-mentioned ON-OFF control circuit 110 can carry out the electric capacity correction program according to pulse wave signal that the external world provided and digital signal (not illustrating) or by the clock signal that inside circuit produced.So-called electric capacity correction program promptly is to compensate target capacitance 132 with the electric capacity in the building-out capacitor array 134, makes the capacitance of its capacitor array 130 level off to reference capacitance 140.ON-OFF control circuit 110 can be via control switch group 150, with reference voltage V
REFTo reference capacitance 140 chargings, after charging, reference capacitance 140 is switched to earth terminal GND, then target capacitance 130 is charged with reference voltage.Then, by the common terminal P of reference capacitance 140 with target capacitance 130
11Change in voltage come the capacitance of comparison reference capacitance 140 and target capacitance 130.Then, according to the output of comparator 160, the building-out capacitor in the building-out capacitor array 134 is connected in parallel to target capacitance 132 to compensate its capacitance.When the capacitance of the target capacitance 132 after the compensation equals reference capacitance 140, common terminal P
11Output voltage V
OUTIt is accurate to equal the ground connection position, and this is because target capacitance 132 equates with reference capacitance 140, so after its electric charge divides equally, and can let common terminal P
11Current potential to be equivalent to the ground connection position accurate.The capacitance of capacitor array 130 promptly is a target capacitance 132 and measured capacitance after building-out capacitor is parallelly connected, mainly along with building-out capacitor array 134 be used for parallelly connected target capacitance 132 capacitance and become.
In addition, it should be noted that before switch SW to reference capacitance 140 chargings
OPThe first conducting of meeting, the positive input terminal ground connection that lets comparator 160, after 140 chargings are accomplished to reference capacitance, switch SW
OPCan open (not conducting), let common terminal P
11Be in suspension joint (floating) state.Then, again target capacitance 132 building-out capacitor parallelly connected with it charged.
Building-out capacitor in the building-out capacitor array 134 can according to the capacitance of target capacitance 130 and processing procedure the error range that possibly cause set, and mode that can the binary bit weight disposes, with algebraically be the example explanation as follows: the capacitance of building-out capacitor is respectively 2
i* C, wherein i is the index value of building-out capacitor, and i equals positive integer and 0≤i≤(N-1), N is the number of building-out capacitor, and C is the position of minimum capacitance in the building-out capacitor.ON-OFF control circuit 110 can the descending electric capacity of shunt compensation one by one to target capacitance 132, with the mode of two bit convergences (binary approximation), make capacitor array 130 level off to reference capacitance 140.Because in trimming process, it is big that the equivalent capacitance value that target capacitance 132 two ends are measured can become because of shunt compensation electric capacity, therefore when design, the electric capacity that can make target capacitance 132 is less than reference capacitance 140.
Next, further with the thin portion circuit framework of Fig. 2 A explanation capacitor array 130 with reference capacitance 140, please with reference to Fig. 2 A, Fig. 2 A is according to the capacitor array 130 of present embodiment and the thin portion circuit diagram of reference capacitance 140.Fig. 2 A illustrates automatic calibration circuit figure partly, mainly comprises capacitor array 130, reference capacitance 140, shift registor 122, buffer 124 and switches set 150 add up.Comprise target capacitance C in the capacitor array 130
T, building-out capacitor C
1～C
N(belonging to building-out capacitor array 134) and switches set 255 (comprise switch SW
1～SW
N), switch SW wherein
1～SW
NBe respectively coupled to building-out capacitor C
1～C
NWith the second input P
2Between.Building-out capacitor C
1～C
NBetween capacitance as stated, building-out capacitor C
NCapacitance be C, building-out capacitor C
N-1Capacitance be 2C, building-out capacitor C
N-2Capacitance be 4C, the rest may be inferred by analogy for it.Wherein, at building-out capacitor C
1～C
NIn, building-out capacitor C
NCapacitance minimum.132 of target capacitances are with target capacitance C
TExpression, reference capacitance 140 is then with reference capacitance C
REFExpression.Building-out capacitor C
1～C
NVia switch SW
1～SW
NBe parallel to target capacitance C
T, and switch SW
2～SW
NThen be controlled by ON-OFF control circuit 110.
In the process of proofreading and correct, ON-OFF control circuit 110 can be earlier with switch SW
P1Switch to reference voltage V
REFWith to reference capacitance C
REFCharging, at this moment, switch SW
P2Be to switch to earth terminal GND.Then, with switch SW
NP1Switch to earth terminal GND, and with switch SW
P2Switch to reference voltage V
REFWith to target capacitance C
TCharging.At this moment, judge output voltage V by the output of comparator 160
OUTWhether greater than 0, if output voltage V
OUTGreater than 0 expression target capacitance C
TGreater than reference capacitance C
REFIf output voltage V
OUTRepresent target capacitance C greater than 0 less than 0
TLess than reference capacitance C
REF
Work as output voltage V
OUTLess than 0 o'clock, actuating switch SW at first then
1, with building-out capacitor C
1Be connected in parallel to target capacitance C
TEquivalent capacitance value with adjustment capacitor array 130.Then, judge output voltage V via the output of comparator 160 equally
OUTWhether greater than 0 to judge that adjusted capacitor array 130 (is building-out capacitor C
1Be connected in parallel to target capacitance C
T) capacitance whether equal reference capacitance C
REFIf adjusted capacitor array 130 is greater than reference capacitance C
REFThen open (not conducting) switch SW
1, then the switch SW of conducting next stage
2With the less building-out capacitor C of parallel connection
2To target capacitance C
TThen, (be building-out capacitor C this moment to adjusted capacitor array 130
2With target capacitance C
TParallel connection) charge, and via output voltage V
OUTWhether the capacitance of judging adjusted capacitor array 130 two ends equals reference capacitance C
REFIf adjusted capacitor array 130 is less than reference capacitance C
REF, then keep switch SW
1Be conducting state, and then actuating switch SW
2, with building-out capacitor C
1, C
2Be connected in parallel to target capacitance C
T, to adjust the equivalent capacitance value that capacitor array 130 two ends are measured.The rest may be inferred, one by one determine switch SW
1～SW
NConducting state make the capacitance of capacitor array 130 level off to reference capacitance 140.
Accomplish all switch SW
1～SW
NCorrection program after, ON-OFF control circuit 110 can be according to SW
1～SW
NConducting state produce one group of corresponding parameter value, the parameter value that the buffer 124 of adding up can be produced ON-OFF control circuit 110 writes down.Then, ON-OFF control circuit 110 can repeat above-mentioned electric capacity correction program producing the parameter values of many groups, the buffer 124 that adds up those parameter values that can add up, and the mean value that calculates those parameter values via shift registor 122 then is to export a final argument value.Because in the present embodiment, parameter value is the digital signal of a N bit, and the logic state signal of its indivedual bits can correspond respectively to switch SW
1～SW
NConducting state, wherein the least significant bit in parameter value unit (Least Significant Bit is LSB) promptly corresponding to switch SW
NCan obtain the mean value of those parameter values after the accumulated value of parameter value is shifted via shift registor 122, counting unit 120 promptly is to utilize this mean value to decide switch SW
1～SW
NConducting state with the adjustment capacitor array 130 capacitance.
Because the electric capacity correction program that present embodiment can repeat repeatedly comes control switch SW to obtain average parameter value
1～SW
NConducting state, therefore can reduce because of reference voltage V
REFOr the error that in trimming process, taken place of circuit and cause the mistake of parameter value, make the capacitance of adjusted capacitor array 130 more approach reference capacitance C
REF
It should be noted that the building-out capacitor C in the above-mentioned capacitor array 130
1～C
NBe to constitute by single electric capacity, in another embodiment of the present invention, building-out capacitor C
1～C
NAlso can utilize a plurality of capacitances in series to realize less capacitance.
Next, further specify the electric capacity correction program of present embodiment with flow chart, please with reference to Fig. 2 B, Fig. 2 B is the electric capacity correction program flow chart according to first embodiment of the invention.At first, with reference voltage V
REFTo reference capacitance C
REFCharging, and, open switch SW then with the positive and negative input end grounding (step S210) of comparator 160
OPAnd diverter switch SW
P1～SW
P2, with reference voltage V
REFTo capacitor array 130 chargings (step S220).Then, switch SW
1Close with to target capacitance C
TAnd building-out capacitor C
1Output voltage V is compared in charging then
OUTWhether greater than 0, and determine switch SW according to this
1Conducting state (step S232, S234).If output voltage V
OUTGreater than 0, then open switch SW
1(step S232) is if output voltage V
OUTLess than 0, off switch SW then
1(step S234).
Output voltage V
OUTGreater than 0 the expression capacitor array 130 electric capacity greater than reference capacitance C
REF, therefore change the less building-out capacitor C of parallel connection
2To target capacitance C
TUtilize output voltage V then
OUTContinue to judge whether to keep building-out capacitor C
2To target capacitance C
TBetween parallel connection relation (step S240, S242 and S254).Output voltage V
OUTLess than 0 the expression capacitor array 130 electric capacity less than reference capacitance C
REF, so parallelly connected more next building-out capacitor C
2To target capacitance C
TTo improve the capacitance of capacitor array 160.Then, equally according to output voltage V
OUTContinue to judge whether to keep building-out capacitor C
2With target capacitance C
TBetween parallel connection relation (step S250, S252 and S254).Then the rest may be inferred for remaining building-out capacitor, determines its corresponding switch SW in regular turn
1～SW
NConducting is up to the capacitance and the reference capacitance C of capacitor array 160
REFEquate or accomplish all switch SW
1～SW
NDetermining program (step S282, S284, S292, S294).
In all switch SW of decision
1～SW
NConducting state after, just can produce corresponding to switch SW
1～SW
NOne group of parameter value (step S215) of conducting state, repeat above-mentioned steps N time (N is a positive integer, can be set by the designer) then, producing the parameter value of M group, and the M group parameter value (step S225) that adds up.The person of connecing calculates average parameter value (step S235), then according to the capacitance (step S245) of mean parameter value output final argument value with the adjustment capacitor array
Second embodiment
Fig. 3 is the gradual analog-digital converter according to second embodiment of the invention, and analog-digital converter 300 comprises shift registor 322, the buffer 324 that adds up, ON-OFF control circuit 310, switches set 350, comparator 360, reference capacitance C
REFAnd capacitor array 331,332.The shift registor 322 and the buffer 324 that adds up be coupled to ON-OFF control circuit 310 and capacitor array 331, between 332, ON-OFF control circuit 310 is coupled to switches set 350 and this switches set 355 in addition, in order to control switch wherein.Switches set 350 comprises switch SW
31, SW
32, SW
33, the one of which end is respectively coupled to first input end P
1, the second input P
2With the 3rd input P
3, the other end then switchably is coupled to input voltage V
IN, reference voltage V
REFOr earth terminal GND.First input end P
1, the second input P
2With the 3rd input P
3The other end then be respectively coupled to reference capacitance C
REF, capacitor array 331,332.The negative input end of comparator 360 then is coupled to common terminal P
11, comparator 360 positive input terminal be coupled to earth terminal GND.Analog-digital converter 300 is that with the main difference of Fig. 1 analog-digital converter 300 comprises two capacitor arrays 331,332 and capacitor C
C, capacitor C wherein
CBe for the capacitance that reduces capacitor array 331,332 set, this capacitor C
CCapacitance can't do the coupling layout with other electric capacity, so can produce than mistake, therefore must be to capacitor C
AWith C
BCarrying out electric capacity proofreaies and correct.
The electric capacity correcting process that utilizes above-mentioned first embodiment is to target capacitance C
AWith C
BProofread and correct.At first, earlier to target capacitance C
BProofread and correct, utilize building-out capacitor C
B1～C
B3Come the correction target capacitor C
BON-OFF control circuit 310 can be earlier to reference capacitance C
REFCharging, and then to capacitor array 331 chargings, then by common terminal P
11Change in voltage adjust switch SW
B1～SW
B3Conducting state.When accomplishing capacitor C
BCorrection after, then utilize identical method to carry out capacitor C again
ACorrection.Because capacitor C
ACapacitance be capacitor C
BTwice, therefore have four building-out capacitor C
A1～C
A4Building-out capacitor C
B1～C
B3With building-out capacitor C
A1～C
A4Capacitance can according to fabrication errors and capacitor C
A, C
BThe capacitance size decide, present embodiment is not limited.In the present embodiment, building-out capacitor C
B1～C
B3With building-out capacitor C
A1～C
A4Then as the building-out capacitor C among above-mentioned first embodiment
1～C
NGenerally, be provided with two-symbol mode, wherein the capacitance of the building-out capacitor in the individual arrays is that mode with multiple increases.
After accomplishing repeatedly correction, the buffer 324 that adds up can be noted down corresponding to switch SW
A1～SW
A4, SW
B1～SW
B3The parameter value of conducting state is obtained the average of all parameter values via shift registor 322 then, utilizes mean parameter value (being the final argument value) determine switch SW then
A1～SW
A4, SW
B1～SW
B3Conducting state.Via repeatedly reducing the error in the trimming process, let the capacitance of capacitor array 331,332 more approach reference capacitance C from dynamic(al) correction
REFAfterwards, switches set 350 can switch to input voltage V with input
INTo carry out the analog digital conversion.In addition, it should be noted that present embodiment applicable to a plurality of capacitor arrays, be not limited to the capacitor array 331,332 among Fig. 3, the building-out capacitor number in the capacitor array also is not restricted to Fig. 3.In addition, capacitor C
CMainly be capacitance, in another embodiment of the present invention, also capacitor C can be set for the capacitor array that reduces the rear end
CIn analog-digital converter, also can utilize the capacitor array of less bit to be used as reference capacitance, or utilize corrected capacitor array to proofread and correct not calibrated capacitor array with the bigger capacitor array of correction bit.
The 3rd embodiment
From another perspective; The present invention proposes a kind of method of automatic corrective capacity; Utilization repeatedly reduces the error in the trimming process from the program of dynamic(al) correction, and please with reference to Fig. 4, Fig. 4 is the flow chart according to the method for the automatic corrective capacity of third embodiment of the invention.At first, relatively capacitor array and the capacitance of reference capacitance to be to export one group of parameter value (step S410), then according to the parallelly connected relation between parameter value adjustment building-out capacitor and the target capacitance to adjust the capacitance (step S420) of capacitor array.Next, repeat above-mentioned steps S410, S420 producing many group parameter values (step S430), the above-mentioned parameter value that adds up then and the mean value that calculates the above-mentioned parameter value are to export a final argument value (step S440).Then, utilize the final argument value to decide the parallelly connected relation (step S450) between building-out capacitor and the target capacitance.The final argument value is repeatedly the mean parameter value after dynamic(al) correction, utilizes the mean parameter value to decide the parallelly connected relation of building-out capacitor and target capacitance, and the error that can reduce in the trimming process to be taken place lets the capacitance of capacitor array more approach reference capacitance.
In sum; The capacitance of capacitor array is repeatedly adjusted in utilization of the present invention from the mean parameter value that dynamic(al) correction produced; The error that reduces in the trimming process by this to be produced; In addition, the present invention more is provided with add up buffer and shift registor in automatic calibration circuit, let automatic calibration circuit can add up voluntarily parameter value with calculate its mean parameter value.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the method for above-mentioned announcement capable of using and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations; In every case be the content that does not break away from technical scheme of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (6)
1. the automatic calibration circuit of an electric capacity is characterized in that it comprises:
One reference capacitance is coupled between a common terminal and the first input end;
One capacitor array comprises:
One target capacitance is coupled between this common terminal and one second input; And
A plurality of building-out capacitors, an end of those building-out capacitors is coupled to this common terminal, and the other end of those building-out capacitors couples one first switches set, and wherein this first switches set has a plurality of first switches, is respectively coupled between those building-out capacitors and this second input;
One correcting circuit; Be coupled to this reference capacitance and this capacitor array; This correcting circuit relatively the capacitance of this reference capacitance and this capacitor array producing one group of parameter value, in order to the conducting state that determines those first switches in this first switches set to adjust parallelly connected relation between those building-out capacitors and this target capacitance to adjust the capacitance of this capacitor array; And
One counting unit is coupled to this correcting circuit and this first switches set, in order to this parameter value of temporary conducting state corresponding to those first switches,
Wherein, This correcting circuit repeats the capacitance of relatively this reference capacitance and this capacitor array and produces many these parameter values of group; The mean value that this counting unit adds up those parameter values and calculates those parameter values to be exporting a final argument value, in order to the conducting state that determines those first switches in this first switches set to adjust the capacitance of this capacitor array;
The capacitance of wherein said building-out capacitor is respectively 2
i* C, wherein i is the index value of those building-out capacitors, and i equals positive integer and 0≤i≤(N-1), N is the number of those building-out capacitors, and C is the position of minimum capacitance in those building-out capacitors.
2. automatic calibration circuit according to claim 1 is characterized in that wherein said correcting circuit comprises:
One comparator, a positive input terminal of this comparator is coupled to an earth terminal, and a negative input end of this comparator is coupled to this common terminal;
One second switch couples between this positive input terminal and this negative input end of this comparator;
One second switch group is coupled between this first input end, this second input, a reference voltage and the earth terminal; And
One ON-OFF control circuit is coupled to output, this second switch, this first switches set and this second switch group of this comparator, and in order to controlling this second switch, this first switches set and this second switch group,
Wherein, this ON-OFF control circuit produces those parameter values corresponding to the conducting state of those first switches to adjust the capacitance of this capacitor array according to the output of this comparator.
3. automatic calibration circuit according to claim 2 is characterized in that wherein said second switch group comprises:
One the 3rd switch, an end of the 3rd switch is coupled to this first input end, and the other end of the 3rd switch is coupled to this reference voltage or this earth terminal; And
One the 4th switch, an end of the 4th switch is coupled to this second input, and the other end of the 4th switch is coupled to this reference voltage or this earth terminal.
4. automatic calibration circuit according to claim 2 is characterized in that wherein said counting unit comprises:
One buffer that adds up is coupled to this ON-OFF control circuit, in order to those parameter values that add up; And
One shift registor is coupled to this and adds up between buffer and this first switches set, in order to the mean value that calculates those parameter values to export this final argument value.
5. the automatic calibration circuit of electric capacity according to claim 3 is characterized in that wherein said automatic calibration circuit is to utilize the following step to produce this parameter value, comprising:
This first switch of conducting is so that this positive input terminal of this comparator and this negative input end ground connection, switches this second switch group so that this first input end is coupled to this reference voltage with to this reference capacitance charging, and makes this second input be coupled to this earth terminal;
Open this first switch to form open circuit, switch this second switch group, and make this second input be coupled to this reference voltage so that this target capacitance is charged so that this first input end is coupled to this earth terminal; And
According to the output of this comparator, the conducting state that determines those first switches in regular turn is to adjust the parallelly connected relation of those building-out capacitors and this target capacitance.
6. the method for an automatic corrective capacity is suitable for to adjust a capacitor array, makes the capacitance of this capacitor array level off to a reference capacitance, and this capacitor array comprises a target capacitance and a plurality of building-out capacitor, it is characterized in that this method may further comprise the steps:
(a) relatively the capacitance of this capacitor array and this reference capacitance to export one group of parameter value;
(b) according to the parallelly connected relation between those building-out capacitors of this parameter value adjustment and this target capacitance to adjust the capacitance of this capacitor array;
(c) repeat above-mentioned steps (a) and (b) organize these parameter values more to produce;
(d) mean value that adds up those parameter values and calculate those parameter values is to export a final argument value; And
(e), determine the parallelly connected relation between those building-out capacitors and this target capacitance according to this final argument value;
The capacitance of wherein said building-out capacitor is respectively 2
i* C, wherein i is the index value of those building-out capacitors, and i equals positive integer and 0≤i≤(N-1), N is the number of those building-out capacitors, and C is the position of minimum capacitance in those building-out capacitors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910126012 CN101820267B (en) | 2009-02-26 | 2009-02-26 | Automatic correction circuit and method of capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910126012 CN101820267B (en) | 2009-02-26 | 2009-02-26 | Automatic correction circuit and method of capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101820267A CN101820267A (en) | 2010-09-01 |
| CN101820267B true CN101820267B (en) | 2012-12-26 |
Family
ID=42655237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910126012 Active CN101820267B (en) | 2009-02-26 | 2009-02-26 | Automatic correction circuit and method of capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101820267B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI446712B (en) * | 2011-05-13 | 2014-07-21 | Holtek Semiconductor Inc | Voltage calibration circuit and method for resistance mismatch |
| CN102664626B (en) * | 2012-05-17 | 2015-05-06 | 中国电子科技集团公司第二十四研究所 | Capacitance error compensation circuit based on microcurrent source |
| JP2015135622A (en) * | 2014-01-17 | 2015-07-27 | 株式会社ジャパンディスプレイ | Touch detection device, display device with touch detection function, and electronic device |
| CN105281772B (en) * | 2014-07-24 | 2018-08-31 | 上海明波通信技术股份有限公司 | Successive approximation analog-digital commutator |
| CN105790748B (en) * | 2014-12-19 | 2018-10-19 | 原相科技股份有限公司 | High-precision capacitance-type switch |
| CN106230437B (en) * | 2016-07-29 | 2019-09-24 | 电子科技大学 | A kind of TIADC OFFSET ERROR CORRECTION METHODS based on mathematical statistics |
| CN107491136B (en) * | 2017-07-06 | 2019-10-15 | 复旦大学 | A kind of difference type capacity regulator for digital calibration |
| CN110187190A (en) * | 2019-05-27 | 2019-08-30 | 许昌许继风电科技有限公司 | The evaluation method and detection system of capacitor box capacitance |
| CN113922820B (en) * | 2021-12-15 | 2022-05-13 | 之江实验室 | Discontinuous buffer circuit based on background calibration and analog-to-digital converter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4476456A (en) * | 1981-11-03 | 1984-10-09 | Texas Instruments Incorporated | Combination of an analog to digital converter and sampling switch |
| CN1967840A (en) * | 2005-11-14 | 2007-05-23 | 旺玖科技股份有限公司 | Self-correcting circuit for mismatch capacity |
| CN101228697A (en) * | 2005-06-16 | 2008-07-23 | 高通股份有限公司 | Gain error correction in an analog-to-digital converter |
-
2009
- 2009-02-26 CN CN 200910126012 patent/CN101820267B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4476456A (en) * | 1981-11-03 | 1984-10-09 | Texas Instruments Incorporated | Combination of an analog to digital converter and sampling switch |
| CN101228697A (en) * | 2005-06-16 | 2008-07-23 | 高通股份有限公司 | Gain error correction in an analog-to-digital converter |
| CN1967840A (en) * | 2005-11-14 | 2007-05-23 | 旺玖科技股份有限公司 | Self-correcting circuit for mismatch capacity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101820267A (en) | 2010-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101820267B (en) | Automatic correction circuit and method of capacitor | |
| US7924209B2 (en) | Self-calibration circuit and method for capacitors | |
| JP5554675B2 (en) | Successive comparison A / D converter | |
| CN105811979B (en) | A kind of gradually-appoximant analog-digital converter of band correction and its bearing calibration | |
| CN104917524B (en) | Analog-digital converter | |
| CN103873059B (en) | Digital calibration method for high-precision SAR ADC (successive approximation register analog to digital converter) | |
| CN103516365B (en) | Solid state image pickup device | |
| CN103036564B (en) | The method of self calibration analog to digital converter and calibrating analog-to-digital converter medial error | |
| CN102859882B (en) | There is the successive approximation register analog/digital converter that integral non-linearity corrects | |
| CN104242935B (en) | A kind of bearing calibration of SAR ADC sectional capacitance mismatches | |
| US8947290B2 (en) | Successive approximation AD converter | |
| US6642871B2 (en) | Analog/digital converter with error automatic calibration function | |
| US8049654B2 (en) | Digital trimming of SAR ADCs | |
| CN102970038B (en) | The unmatched approaching simulation gradually of corrective capacity is to digital quantizer and method thereof | |
| TWI783072B (en) | Method and apparatus for offset correction in sar adc with reduced capacitor array dac | |
| KR102001762B1 (en) | DAC capacitance array, SAR-type analog-to-digital converter and method of reducing power consumption | |
| JP2013093850A (en) | Multi-bit successive approximation adc | |
| CN107346975B (en) | SAR type ADC's high accuracy calibrating device | |
| KR101419804B1 (en) | Analog digital converting device | |
| CN111786675B (en) | Charge sharing type analog-to-digital converter quantization method based on dynamic tracking | |
| CN115099182B (en) | Integral design method for segmented CDAC (capacitor-to-capacitor converter) bridge capacitor and analog-to-digital converter | |
| CN105049050A (en) | Electric charge reallocation method for successive approximation analog-digital converter | |
| CN110912558B (en) | Two-step asymmetric alternating monotonic switching successive approximation type analog-to-digital converter | |
| TW201310918A (en) | Successive approximation analog to digital converter with capacitor mismatch calibration and method thereof | |
| CN114614821A (en) | SAR ADC offset error correction method and circuit based on differential structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |