CN101814531A - Capacitor formed by semiconductor PN junction capacitance and manufacturing method thereof - Google Patents
Capacitor formed by semiconductor PN junction capacitance and manufacturing method thereof Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 94
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 238000000605 extraction Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 238000002207 thermal evaporation Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 32
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000003068 static effect Effects 0.000 abstract description 5
- 230000008901 benefit Effects 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 abstract description 2
- 238000005566 electron beam evaporation Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000007650 screen-printing Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 8
- 230000002441 reversible effect Effects 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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Abstract
The invention discloses a capacitor formed by utilizing semiconductor PN junction capacitance and a manufacturing method thereof. The capacitor uses a semiconductor as a substrate, the capacitance of the capacitor is the junction capacitance of a PN junction of the semiconductor, and the capacitor specifically comprises the following components: forming a PN junction in a specific region on a high-doped low-resistance P-type or N-type semiconductor substrate by adopting a diffusion method or an ion implantation method; a metal film layer which is manufactured on the N-type area and the P-type area of the semiconductor forming the PN junction by adopting a thermal evaporation method, an electron beam evaporation method or a sputtering method; the metal film layer is provided with electrode salient points which are manufactured by adopting an electroplating method or a screen printing method; according to actual needs, the extraction electrodes can be arranged on two surfaces of the semiconductor substrate or only on the surface of the etching area. The capacitor manufactured by the invention has the advantages of simple structure, large capacitance density, small parasitic parameter, simple manufacturing process and the like, has the function of protecting static electricity and surge, and can be widely used in high-frequency, high-speed and high-power electronic systems.
Description
Technical field
The present invention relates to technical field of microelectronic devices, particularly a kind of capacitor that utilizes the semiconductor PN junction capacitance formation that is mainly used in occasions such as intermediate frequency (200MHz-2.5GHz) decoupling and preparation method thereof.
Background technology
Decoupling capacitor is widely used in the various electronic systems, it generally is connected between the power supply and ground in the supply network in the electronic system, utilize the electric capacity frequency more little principle of high impedance more, the high-frequency noise in the electric power network is reduced, thereby the noise in the electric power network is played inhibitory action.
In the practical application, because intrinsic stray inductance and the resistance of capacitor, any capacitor all can not be accomplished the full frequency band decoupling from the low frequency to the high frequency.In general, capacitor appearance value is big more, and is just good more to low frequency decoupling effect, but volume is just big more, and stray inductance and resistance are also big more, just poor more to the decoupling effect of high frequency; Capacitor appearance value is more little, and volume is just more little, and stray inductance and resistance are just more little, therefore can be used for high frequency, but because the appearance value is little, low frequency decoupling effect is just poor.
For satisfying the broadband decoupling, generally be that the capacitor with a plurality of different appearance values is together in parallel, Da Rong value capacitor is to the low frequency component decoupling, and the low-capacitance capacitor is to the high fdrequency component decoupling.This solution is feasible to the electronic system space without limits the time, but just infeasible when there is strict restriction in the electronic system space.Obviously, optimal situation is that a capacitor has big appearance value and little stray inductance and resistance.Because stray inductance and resistance are directly proportional with volume, volume is big more, and stray inductance and resistance are just big more.So another saying is that optimal decoupling capacitor is to have minimum volume and maximum appearance value.
The decoupling capacitor that is used for intermediate frequency decoupling (500MHz is between several GHz) now is generally multi-layer ceramics surface mount capacitor (MLCC), is of a size of 0201 (0.6 * 0.3 * 0.3 millimeter) or 0402 (1.0 * 0.5 * 0.5 millimeter).It is to be superimposed together by the ceramic dielectric diaphragm of printed electrode (interior electrode) mode with dislocation, form ceramic chip through disposable high temperature sintering, seal up metal level (external electrode) again at the two ends of chip, thereby form the structure of a similar only stone, so also be monolithic capacitor.This patch capacitor device still needs to be connected with circuit by lead-in wire, has increased the adverse effect of parasitic parameter to performance.
The unique capacitive properties that the space charge region had that utilizes semiconductor P district, the formation of N regional boundary face place that the present invention proposes uses traditional microelectronic technique semiconductor fabrication, realizes Da Rong value electric capacity integrated on silicon.It is not the notion of a novelty that PN junction is used as electric capacity, as far back as nineteen sixty-eight, (patent No.: the characteristics of utilizing the PN junction junction capacitance to change with applied voltage 766605) are made variable capacitance as tuning to people such as the Raymond A.Sigsbee of General Corporation at " voltage-Variable capacitorwith extendible PN Junction Region ".The people such as Hslen-Te of Taiwan semiconductor manufacturing company are in " Reverse-Biasd PN Diode Decoupling the Capacitor " (patent No.: 2008/0122036) PN junction junction capacitance effect is applied to the decoupling in the chip power power supply of integrated circuit.People such as the Jung S.Kang of Intel company have also mentioned in " Intrinsic Decoupling capacitor " PN junction have been used in the integrated circuit as decoupling capacitance.Because this electric capacity is on integrated circuit (IC) chip, area is generally all very little, from several square microns to tens square microns about, and they are not independently, usually and other circuit integrate.
The formed electric capacity of large tracts of land PN junction is directly made decoupling capacitor with form independently, and in the surface mount mode, the Electronic Packaging or the system that are used for the intermediate frequency decoupling do not appear in the newspapers as yet.This capacitor also possesses a kind of and common another different characteristics of capacitor: when reverse voltage increases to a certain numerical value, reverse breakdown will appear, reverse voltage does not change with electric current in certain reverse current scope, thereby can reduce the influence to circuit such as static, surge to a great extent.This electric capacity can utilize flip chip technology (fct) (Flip-Chip), and Wire Bonding Technology (wire-bond) directly is mounted on substrate surfaces such as pcb board with the form of nude film, and realization electric capacity decoupling combines with pressure stabilization function.Flip-Chip technology particularly, it is that I/O end at chip utilizes planar technique to make solder bump, chip is faced down, directly be mounted on the substrate, utilize reflow soldering process to make between chip solder salient point and the substrate pads and form solder joint, realize electricity, heat, the mechanical connection of chip and substrate.The advantage of solder bump interconnect has been to omit the lead-in wire between chip and the substrate, electrifying, the solder joint path of interconnect function is short, contact area big, stray inductance/electric capacity is little, the packaging density height utilizes decoupling capacitance that this invention makes can realize the shortest connection of device and substrate with Flip-Chip technology.
In addition, because decoupling capacitor involved in the present invention has special structure in the design of electrode, its electrode itself has extremely low stray inductance, can further improve the decoupling performance.Therefore, both are in conjunction with the influence that can farthest reduce the patch capacitor parasitic parameter.Use the decoupling capacitance of this invention can substitute traditional patch capacitor device, can be widely used in system or encapsulation, especially the intermediate frequency decoupling in the system in package (System-in-Package SiP, System-on-Package SoP).
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide a kind of capacitor that utilizes the semiconductor PN junction capacitance formation and preparation method thereof.
(2) technical scheme
Be an aspect that achieves the above object, the invention provides a kind of capacitor that utilizes semiconductor PN junction capacitance to constitute, as base material, its electric capacity is the junction capacitance of semiconductor PN to this capacitor, specifically comprises with a block semiconductor:
The PN junction that on the P of highly doped low-resistance type or N type semiconductor base material, adopts diffusion method or ion implantation in the specific region, to form;
A metallic diaphragm that on semi-conductive N type zone that forms PN junction and p type island region territory, adopts thermal evaporation, electron-beam vapor deposition method or sputtering method to make;
The electrode salient point that on this metallic diaphragm, adopts electro-plating method or method for printing screen to make; And
On the two sides of semiconductor substrate or the electrode of only drawing at the etch areas face.
In the such scheme, the P type of described highly doped low-resistance or N type semiconductor base material, its thickness can be according to actual needs or process conditions carry out attenuate, thickness range is that tens of microns are to hundreds of microns.
In the such scheme, the areal extent of described PN junction arrives several square millimeters, several square centimeters even for the number square micron.
In the such scheme, described metallic diaphragm conduct is with semi-conductive ohmic contact and electroplate furling plating, the metal furling plating mutually insulated of N type district and p type island region.
In the such scheme, for distinguishing N type and P type polarity, the salient point of N type district and p type island region can be made into difformity, or different size, or different the arrangement, or different number.
In the such scheme, described electrode of drawing is respectively on the two sides of base material, perhaps only on the etch areas face, and the electrode mutually insulated of N type district and p type island region.
Be another aspect that achieves the above object, the invention provides a kind of manufacture method of utilizing the capacitor of semiconductor PN junction capacitance formation, it is characterized in that this method comprises:
In the specific region of the P of highly doped low-resistance type or N type semiconductor base material, form PN junction;
On semi-conductive N type zone that forms PN junction and p type island region territory, make a metallic diaphragm;
On this metallic diaphragm, make the electrode salient point; And
Extraction electrode on the etch areas face on the two sides of semiconductor substrate or only.
In the such scheme, described in the specific region of the P of highly doped low-resistance type or N type semiconductor base material, formation before the PN junction, further comprise: go out the raceway groove of certain depth or the array on island with dry method or wet etching in the semiconductor substrate specific region, with the surface area of increase capacitor, and then increase capacitor appearance value.
In the such scheme, describedly in the specific region of the P of highly doped low-resistance type or N type semiconductor base material, form PN junction, adopt diffusion method or ion implantation to realize.
In the such scheme, describedly on semi-conductive N type zone that forms PN junction and p type island region territory, make a metallic diaphragm, adopt thermal evaporation, electron-beam vapor deposition method or sputtering method realization.
In the such scheme, the described electrode salient point of making on this metallic diaphragm adopts electro-plating method or method for printing screen to realize.
(3) beneficial effect
Advantages such as this capacitor that utilizes the semiconductor PN junction capacitance formation provided by the invention and preparation method thereof utilizes traditional microelectronic processing technology, and the capacitor of making has simple in structure, and capacitance density is big, and parasitic parameter is little, and the manufacture craft process is simple.Theory analysis and actual measurement show that because the peculiar property of semiconductor PN, this capacitor can be operated in quite high frequency, can be used for decoupling or other occasions of intermediate frequency (200MHz is to several GHz).Simultaneously because the intrinsic characteristic of semiconductor PN, the important feature that this capacitor also has traditional capacitor and do not had, promptly static and surge there are safeguard function, can be widely used in the occasions such as decoupling, filtering, coupling, static and surge protection in the high-frequency high-speed high power electronic system.
Description of drawings
Fig. 1 contains printed circuit board (PCB) schematic diagram of the present invention.Wherein:
101-multilayer board substrate;
102-surface mount original paper;
103-is used for interconnected blind hole;
The capacitor of the present invention that 104-adopts flip chip bonding (flip-chip) form to use;
The 105-holding wire;
The capacitor of the present invention that 106-adopts line weldering (wire band) form to use;
107-built-in type resistance;
108-multilayer board core layer;
109-is used for interconnected through hole;
Solder ball in the 110-BGA encapsulation;
Fig. 2 a is the operation principle of PN junction as capacitor.Wherein:
201-adds the electric charge number that forward bias increases the time space charged region;
Fig. 2 b is the operation principle of PN junction as capacitor.Wherein:
202-adds the electric charge number that forward bias reduces the time space charged region;
Fig. 3 a is that two electrodes provided by the invention are at the capacitor schematic cross-section with one side.Wherein:
The semiconductor low resistance base material of 301-capacitor;
The opposite polarity high-doped zone of 302-and base material;
The real work zone of 303-capacitor, i.e. space charge region;
304-plays the dielectric layer of insulation protection effect;
305-capacitor doped region electrode;
306-capacitor basal electrode;
Fig. 3 b is the capacitor schematic cross-sections of two electrodes provided by the invention on two surfaces.Wherein:
The semiconductor low resistance base material of 301-capacitor;
The opposite polarity high-doped zone of 302-and base material;
The real work zone of 303-capacitor, i.e. space charge region;
304-plays the dielectric layer of insulation protection effect;
305-capacitor doped region electrode;
306-capacitor basal electrode;
Fig. 4 is the distribution of electrodes vertical view of capacitor.Wherein:
401-capacitor basal electrode;
402-capacitor doped region electrode;
Fig. 5 is the method flow diagram that making provided by the invention utilizes the capacitor of semiconductor PN junction capacitance formation;
Fig. 6 is the measured result of typical reactance absolute value of capacitor of the present invention and frequency.
Fig. 7 is that capacitor of the present invention is typically surveyed capacitance.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention utilizes semiconductor PN junction capacitance to replace traditional MIM " sandwich " structure capacitive, utilizes its high frequency characteristics good, and the characteristics that reverse leakage current is little are applied in the decoupling circuit.Semi-conductive PN junction junction capacitance has comprised barrier capacitance and diffusion capacitance two parts, barrier capacitance is because the variation of applied voltage on the PN junction, caused electronics and hole " depositing in " and " taking-up " phenomenon in the barrier region, cause the space charge quantity of barrier region to change with applied voltage, this phenomenon is equal to the effect that discharges and recharges of capacitor.And diffusion capacitance is since the amount of charge of diffusion region with the capacity effect that variation produced of applied voltage.The quantity of electric charge of the space charge region of two kinds of electric capacity can all be variable capacitances, as shown in Figure 2 along with change in voltage all.
Because another characteristic of PN junction is that forward conduction oppositely ends, oppositely the time, only have barrier capacitance, and leakage current is little when anti-inclined to one side, therefore, the present invention makes PN junction with diffusion method or ion implantation on a block semiconductor substrate, the barrier capacitance when utilizing PN junction anti-inclined to one side constitutes a capacitor.Because it is big that the appearance value of this capacitor has unit-area capacitance density, parasitic parameter is little, the operating frequency height, and characteristics such as the PN junction area is big, and extraction electrode is flexible are so can be used for decoupling.The unique character of another of this capacitor is when reverse biased is increased to certain limit, because the reverse breakdown characteristics that has of PN junction, so this electric capacity can also prevent the generation of phenomenons such as static or surge when being used for decoupling.This PN junction structure capacitive device comprises the PN utmost point electrode that play up and down two electrode effects corresponding with mim structure and plays the PN junction of electric capacity effect and the space charge region of formation thereof.
In addition, base material is processed into the 3-D graphic with definite shape, thereby reaches the purpose that increases the appearance value with the effective area that increases electric capacity in order to increase the capacitance of capacitor on unit are, can also utilize semiconductor technology as required the characteristics that had.The kind of 3D shape is a lot, as groove-shaped, the square column type, column type etc., this be general patch capacitor device can not accomplish.Because photoetching process has sizable flexibility in the microelectronic processing technology, this decoupling capacitance can have special structure in the design of electrode, shown in Fig. 4 a, b, its multiple spot contact or long rectangular electrode shape have the characteristic of extra low inductance, have further reduced the influence of stray inductance to device performance.
In addition, because being the form with " nude film ", this decoupling capacitance places substrate surface such as PCB, can the extraction electrode of this decoupling capacitor be placed the same surface of device according to active passive device distribution situation in the side circuit, perhaps place two surfaces respectively, further to reduce the influence of parasitic parameter.The flexibility that its extraction electrode distributes also is that general patch capacitor does not have.
Shown in Fig. 3 a and Fig. 3 b, this capacitor that utilizes semiconductor PN junction capacitance to constitute provided by the invention, as base material, its electric capacity is the junction capacitance of semiconductor PN, specifically comprises with a block semiconductor:
The PN junction that on the P of highly doped low-resistance type or N type semiconductor base material, adopts diffusion method or ion implantation in the specific region, to form;
A metallic diaphragm that on semi-conductive N type zone that forms PN junction and p type island region territory, adopts thermal evaporation, electron-beam vapor deposition method or sputtering method to make;
The electrode salient point that on this metallic diaphragm, adopts electro-plating method or printing process to make; And
On the two sides of semiconductor substrate or the electrode of only drawing in corrosion area face.
The P type of highly doped low-resistance or N type semiconductor base material, its thickness can be according to actual needs or process conditions carry out attenuate, thickness range is that tens of microns are to hundreds of microns.The areal extent of PN junction arrives several square millimeters, several square centimeters even for the number square micron.The metallic diaphragm conduct is with semi-conductive ohmic contact and electroplate furling plating, the metal furling plating mutually insulated of N type district and p type island region.For distinguishing N type and P type polarity, the salient point of N type district and p type island region can be made into difformity, or different size, or different the arrangement, or different number.The electrode of drawing is respectively on the two sides of base material, perhaps only on corrosion area face, and the electrode mutually insulated of N type district and p type island region.
Fig. 4 shows the distribution of electrodes vertical view of capacitor.Wherein: the 401st, the capacitor basal electrode; The 402nd, capacitor doped region electrode.
Fig. 5 shows the method flow diagram that making provided by the invention utilizes the capacitor of semiconductor PN junction capacitance formation, and this method comprises:
Step 501: in the specific region of the P of highly doped low-resistance type or N type semiconductor base material, form PN junction;
Step 502: on semi-conductive N type zone that forms PN junction and p type island region territory, make a metallic diaphragm;
Step 503: on this metallic diaphragm, make the electrode salient point;
Step 504: extraction electrode on corrosion area face on the two sides of semiconductor substrate or only.
In the specific region of the P of highly doped low-resistance type or N type semiconductor base material, form before the PN junction described in the step 501, can further comprise as required: go out the raceway groove of certain depth or the array on island with dry method or wet etching in the semiconductor substrate specific region, with the surface area of increase capacitor, and then increase capacitor appearance value.
Describedly described in the step 501 in the specific region of the P of highly doped low-resistance type or N type semiconductor base material, form PN junction, adopt diffusion method or ion implantation to realize.
Describedly described in the step 502 on semi-conductive N type zone that forms PN junction and p type island region territory, make a metallic diaphragm, adopt thermal evaporation, electron-beam vapor deposition method or sputtering method realization.
The described electrode salient point of making on this metallic diaphragm adopts electro-plating method or method for printing screen to realize described in the step 503.
The present invention has three kinds of forms at least according to actual operating position: salient point weldering (or flip chip bonding) form, line weldering form and salient point/line weldering mixed form.Multi-formly make other steps all except that electrode.Below with two electrodes at base material with one side, the capacitor that is used for salient point weldering form is an example:
Step 6, for forming good Ohmic contact, the electrode that forms is heat-treated, reduce the contact resistance of metal semiconductor as much as possible;
Step 7, utilize wafer screen process press or plating and technique of backflow to make salient point needed salient point of when weldering at electrode zone 305,306;
Step 8, the wafer patterned surface for preparing is protected, lower surface is thinned to the thickness that needs;
Step 9, wafer is cut, make independent capacitor, finish capacitor fabrication of the present invention.
If two electrodes of capacitor are produced on two surfaces of base material, then before above-mentioned steps 5, carry out the attenuate of wafer, carry out the making of top electrode again, after above-mentioned steps 8, carry out the making of bottom electrode, manufacture method is identical with step 5, and just metal electrode is on another surface of base material.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. capacitor that utilizes semiconductor PN junction capacitance to constitute is characterized in that as base material, its electric capacity is the junction capacitance of semiconductor PN to this capacitor, specifically comprises with a block semiconductor:
The PN junction that on the P of highly doped low-resistance type or N type semiconductor base material, adopts diffusion method or ion implantation in the specific region, to form;
A metallic diaphragm that on semi-conductive N type zone that forms PN junction and p type island region territory, adopts thermal evaporation, electron-beam vapor deposition method or sputtering method to make;
The electrode salient point that on this metallic diaphragm, adopts electro-plating method or method for printing screen to make; And
On the two sides of semiconductor substrate or the electrode of only drawing in corrosion area face.
2. the capacitor that utilizes semiconductor PN junction capacitance to constitute according to claim 1, it is characterized in that, the P type of described highly doped low-resistance or N type semiconductor base material, its thickness can be according to actual needs or process conditions carry out attenuate, thickness range is that tens of microns are to hundreds of microns.
3. the capacitor that utilizes semiconductor PN junction capacitance to constitute according to claim 1 is characterized in that, the areal extent of described PN junction arrives several square millimeters, several square centimeters even for the number square micron.
4. the capacitor that utilizes semiconductor PN junction capacitance to constitute according to claim 1 is characterized in that, described metallic diaphragm conduct is with semi-conductive ohmic contact and electroplate furling plating, the metal furling plating mutually insulated of N type district and p type island region.
5. the capacitor that utilizes semiconductor PN junction capacitance to constitute according to claim 1 is characterized in that, for distinguishing N type and P type polarity, the salient point of N type district and p type island region can be made into difformity, or different size, or different the arrangement, or different number.
6. the capacitor that utilizes semiconductor PN junction capacitance to constitute according to claim 1 is characterized in that, described electrode of drawing is respectively on the two sides of base material, perhaps only on corrosion area face, and the electrode mutually insulated of N type district and p type island region.
7. manufacture method of utilizing the capacitor that semiconductor PN junction capacitance constitutes is characterized in that this method comprises:
In the specific region of the P of highly doped low-resistance type or N type semiconductor base material, form PN junction;
On semi-conductive N type zone that forms PN junction and p type island region territory, make a metallic diaphragm;
On this metallic diaphragm, make the electrode salient point; And
Extraction electrode on corrosion area face on the two sides of semiconductor substrate or only.
8. the manufacture method of utilizing the capacitor that semiconductor PN junction capacitance constitutes according to claim 7 is characterized in that, describedly forms before the PN junction in the specific region of the P of highly doped low-resistance type or N type semiconductor base material, further comprises:
Go out the raceway groove of certain depth or the array on island in the semiconductor substrate specific region with dry method or wet etching,, and then increase capacitor appearance value with the surface area of increase capacitor.
9. the manufacture method of utilizing the capacitor of semiconductor PN junction capacitance formation according to claim 7, it is characterized in that, describedly in the specific region of the P of highly doped low-resistance type or N type semiconductor base material, form PN junction, adopt diffusion method or ion implantation to realize.
10. the manufacture method of utilizing the capacitor of semiconductor PN junction capacitance formation according to claim 7, it is characterized in that, describedly on semi-conductive N type zone that forms PN junction and p type island region territory, make a metallic diaphragm, adopt thermal evaporation, electron-beam vapor deposition method or sputtering method realization.
11. the manufacture method of utilizing the capacitor of semiconductor PN junction capacitance formation according to claim 7 is characterized in that, the described electrode salient point of making on this metallic diaphragm adopts electro-plating method or method for printing screen to realize.
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| CN109675542A (en) * | 2018-11-29 | 2019-04-26 | 长春理工大学 | Utilize the self-powered semiconductor photoelectrocatalysielectrode device of PN junction |
| CN112234110A (en) * | 2020-10-16 | 2021-01-15 | 重庆大学 | Sandwich-shaped PN junction and accurate construction method thereof |
| WO2023133993A1 (en) * | 2022-01-13 | 2023-07-20 | 长鑫存储技术有限公司 | Semiconductor structure and method for preparing semiconductor structure |
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| CN101017779A (en) * | 2006-02-08 | 2007-08-15 | 中国科学院微电子研究所 | Method for forming through hole on InP substrate and semiconductor photoelectric device |
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| CN109216518A (en) * | 2017-06-30 | 2019-01-15 | 苏州新纳晶光电有限公司 | Antistatic LED chip preparation method and applications |
| CN109675542A (en) * | 2018-11-29 | 2019-04-26 | 长春理工大学 | Utilize the self-powered semiconductor photoelectrocatalysielectrode device of PN junction |
| CN109675542B (en) * | 2018-11-29 | 2021-11-26 | 长春理工大学 | Semiconductor photoelectric catalytic device self-powered by PN junction |
| CN112234110A (en) * | 2020-10-16 | 2021-01-15 | 重庆大学 | Sandwich-shaped PN junction and accurate construction method thereof |
| CN112234110B (en) * | 2020-10-16 | 2022-07-19 | 重庆大学 | Sandwich-shaped PN junction and accurate construction method thereof |
| WO2023133993A1 (en) * | 2022-01-13 | 2023-07-20 | 长鑫存储技术有限公司 | Semiconductor structure and method for preparing semiconductor structure |
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