CN101803210B - 使用块结构奇偶校验矩阵来提供半并行低密度奇偶校验解码的方法、装置和设备 - Google Patents
使用块结构奇偶校验矩阵来提供半并行低密度奇偶校验解码的方法、装置和设备 Download PDFInfo
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- CN101803210B CN101803210B CN200880107168.5A CN200880107168A CN101803210B CN 101803210 B CN101803210 B CN 101803210B CN 200880107168 A CN200880107168 A CN 200880107168A CN 101803210 B CN101803210 B CN 101803210B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6566—Implementations concerning memory access contentions
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- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Description
Claims (25)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/977,644 US8219876B2 (en) | 2007-10-24 | 2007-10-24 | Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix |
US11/977,644 | 2007-10-24 | ||
PCT/IB2008/054412 WO2009053942A2 (en) | 2007-10-24 | 2008-10-24 | Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2013101369610A Division CN103227646A (zh) | 2007-10-24 | 2008-10-24 | 使用块结构奇偶校验矩阵来提供半并行低密度奇偶校验解码的方法、装置和设备 |
Publications (2)
Publication Number | Publication Date |
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CN101803210A CN101803210A (zh) | 2010-08-11 |
CN101803210B true CN101803210B (zh) | 2013-05-22 |
Family
ID=40481796
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200880107168.5A Expired - Fee Related CN101803210B (zh) | 2007-10-24 | 2008-10-24 | 使用块结构奇偶校验矩阵来提供半并行低密度奇偶校验解码的方法、装置和设备 |
CN2013101369610A Pending CN103227646A (zh) | 2007-10-24 | 2008-10-24 | 使用块结构奇偶校验矩阵来提供半并行低密度奇偶校验解码的方法、装置和设备 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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CN2013101369610A Pending CN103227646A (zh) | 2007-10-24 | 2008-10-24 | 使用块结构奇偶校验矩阵来提供半并行低密度奇偶校验解码的方法、装置和设备 |
Country Status (4)
Country | Link |
---|---|
US (2) | US8219876B2 (zh) |
CN (2) | CN101803210B (zh) |
TW (1) | TW201320621A (zh) |
WO (1) | WO2009053942A2 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8386904B2 (en) * | 2009-04-29 | 2013-02-26 | Adeptence, Llc | High speed low density parity check codes encoding and decoding |
US8352846B2 (en) * | 2009-05-07 | 2013-01-08 | Adeptence, Llc | Method an apparatus for low density parity check codes encoding and decoding |
US8539301B2 (en) * | 2009-10-21 | 2013-09-17 | Nec Laboratories America, Inc. | Message-wise unequal error protection |
US10784901B2 (en) | 2015-11-12 | 2020-09-22 | Qualcomm Incorporated | Puncturing for structured low density parity check (LDPC) codes |
US10673461B2 (en) * | 2015-12-24 | 2020-06-02 | Intel Corporation | Hybrid scheduling and latch-based pipelines for low-density parity-check decoding |
US10200066B2 (en) * | 2016-03-09 | 2019-02-05 | SK Hynix Inc. | Code reconstruction scheme for multiple code rate TPC decoder |
US10291354B2 (en) | 2016-06-14 | 2019-05-14 | Qualcomm Incorporated | High performance, flexible, and compact low-density parity-check (LDPC) code |
US10116333B2 (en) * | 2016-07-29 | 2018-10-30 | Sandisk Technologies Llc | Decoder with parallel decoding paths |
US10270466B2 (en) | 2016-08-15 | 2019-04-23 | Hughes Network Systems, Llc | LDPC performance improvement using SBE-LBD decoding method and LBD collision reduction |
US10778371B2 (en) * | 2016-11-02 | 2020-09-15 | Qualcomm Incorporated | Deeply-pipelined high-throughput LDPC decoder architecture |
CN106849957A (zh) * | 2016-12-30 | 2017-06-13 | 北京联想核芯科技有限公司 | 编码方法和装置 |
US10340949B2 (en) | 2017-02-06 | 2019-07-02 | Qualcomm Incorporated | Multiple low density parity check (LDPC) base graph design |
US10312939B2 (en) | 2017-06-10 | 2019-06-04 | Qualcomm Incorporated | Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code |
CN110322523A (zh) * | 2018-03-31 | 2019-10-11 | 深圳忆联信息系统有限公司 | 编码方法和装置 |
CN112636767B (zh) * | 2020-12-03 | 2023-04-07 | 重庆邮电大学 | 一种具有单置换网络的分层半并行ldpc译码器系统 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1905374A (zh) * | 2005-07-25 | 2007-01-31 | 松下电器产业株式会社 | 非对称低密度校验码编译码方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100809619B1 (ko) * | 2003-08-26 | 2008-03-05 | 삼성전자주식회사 | 이동 통신 시스템에서 블록 저밀도 패러티 검사 부호부호화/복호 장치 및 방법 |
US7581157B2 (en) * | 2004-06-24 | 2009-08-25 | Lg Electronics Inc. | Method and apparatus of encoding and decoding data using low density parity check code in a wireless communication system |
US7549105B2 (en) * | 2005-01-10 | 2009-06-16 | Broadcom Corporation | Construction of irregular LDPC (low density parity check) codes using RS (Reed-Solomon) codes or GRS (generalized Reed-Solomon) code |
US7516390B2 (en) * | 2005-01-10 | 2009-04-07 | Broadcom Corporation | LDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems |
CN100486150C (zh) * | 2005-01-23 | 2009-05-06 | 中兴通讯股份有限公司 | 基于非正则低密度奇偶校验码的编译码器及其生成方法 |
US7441178B2 (en) * | 2005-02-24 | 2008-10-21 | Keyeye Communications | Low complexity decoding of low density parity check codes |
US8181083B2 (en) * | 2007-08-27 | 2012-05-15 | Stmicroelectronics S.R.L. | Methods and architectures for layered decoding of LDPC codes with minimum latency |
KR101077552B1 (ko) * | 2007-12-14 | 2011-10-28 | 한국전자통신연구원 | 복수의 기본 패리티 검사행렬을 이용한 저밀도 패리티 검사부호의 복호화 장치 및 그 방법 |
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2007
- 2007-10-24 US US11/977,644 patent/US8219876B2/en active Active
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2008
- 2008-10-24 CN CN200880107168.5A patent/CN101803210B/zh not_active Expired - Fee Related
- 2008-10-24 WO PCT/IB2008/054412 patent/WO2009053942A2/en active Application Filing
- 2008-10-24 CN CN2013101369610A patent/CN103227646A/zh active Pending
- 2008-10-30 TW TW102101819A patent/TW201320621A/zh unknown
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2012
- 2012-05-24 US US13/479,745 patent/US8869003B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1905374A (zh) * | 2005-07-25 | 2007-01-31 | 松下电器产业株式会社 | 非对称低密度校验码编译码方法 |
Non-Patent Citations (1)
Title |
---|
PREDRAG RADOSAVLJEVIC等.HIGH-THROUGHPUT MULTI-RATE LDPC DECODER BASED ON ARCHITECTURE-ORIENTED PARITY CHECK MATRICES.《14th European Signal ProcessingConference(EUSIPCO)》.2006, * |
Also Published As
Publication number | Publication date |
---|---|
US8869003B2 (en) | 2014-10-21 |
US20120240003A1 (en) | 2012-09-20 |
TW201320621A (zh) | 2013-05-16 |
CN101803210A (zh) | 2010-08-11 |
US20090113276A1 (en) | 2009-04-30 |
US8219876B2 (en) | 2012-07-10 |
CN103227646A (zh) | 2013-07-31 |
WO2009053942A3 (en) | 2009-06-11 |
WO2009053942A2 (en) | 2009-04-30 |
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