CN101797848B - High-speed data rotation control device and method based on FPGA (Field Programmable Gate Array) - Google Patents
High-speed data rotation control device and method based on FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention discloses a high-speed data rotation control device based on FPGA (Field Programmable Gate Array), comprising a data receiver, a data input distributor, a data buffer, a data rotator, a data output distributor and a data output device. The invention also provides a high-speed data rotation control method based on the FPGA, which comprises a step of block data receiving control, a step of block data shunt input control, a step of production line control for data processing, a step of block data selection output control and a step of block data output control. The throughput capacity of the data is improved through an operation way of realizing three-level production lines of the data, and a strict circulation operation of the data is realized through the control of a state machine, thereby the reliability of the system is improved.
Description
Technical field
The present invention relates to digit printing control field and FPGA technology, relate in particular to a kind of high-speed data rotating control assembly and method based on FPGA.
Background technology
Along with the develop rapidly of digital decorating machine, the quick growth of digital printing industry, logarithmic code stamp speed has had higher requirement, and the control device that needs faster data-handling capacity is realized the data processing of digital decorating machine.
The FPGA technology has obtained develop rapidly in recent years, can be towards the compute-intensive applications of complexity from changing into towards the application that pure logic substitutes at first.In the FPGA device of up-to-date release, not only be integrated with abundant configurable logic block resource (Configurable Logic Block, CLB), (BlockRAM is BRAM) with the RocketIO GTP transceiver unit that is used for high-speed serial communication also to comprise a large amount of DSP unit towards the computation-intensive application, block RAM.For making things convenient for the debugging of FPGA, each FPGA manufacturer has also released logic analysis testing tool (as the ChipScope of Xilinx company) in the sheet, in the feasibility that has guaranteed to realize high-performance calculation on the software and hardware on FPGA simultaneously.
At the requirement of digital decorating machine self defined interface and high speed data transfer, need dedicated system and handle as the data of digital decorating machine.Relative and all-purpose computer is handled for the data of digital decorating machine, particularly require the rotation of data by the bit position, the processing speed of all-purpose computer can't reach the requirement of printing machine far away, so realize that by dedicated system data high-speed rotates the operating efficiency that improves printing machine.
Summary of the invention
The invention provides the high-speed data rotating control assembly based on FPGA of a kind of high reliability, high-throughput.
A kind of high-speed data rotating control assembly based on FPGA comprises:
Data sink is used for the reception of blocks of data;
Data input distributor connects data sink and three data buffers, is used for the blocks of data that data sink receives is shunted input control;
Three data buffers connect data input distributor, data output distributor and each self-corresponding data circulator, are used for the buffer memory of original block data and rotation back blocks of data;
Three data circulators connect each self-corresponding data buffer, are used for the rotation of data;
(each data buffer and each data circulator are one group, totally three groups)
Data output distributor connects data logger and three data buffers, is used for the blocks of data that three data buffers send is selected output control;
Data logger connects data output distributor, is used for the also line output of blocks of data;
Can the programming by all-purpose computer realize that the present invention adopts the specific function piece among the FPGA to realize, can finish higher data rotation efficiency although the present invention is based on the function of each part of the high-speed data rotating control assembly of FPGA.
The present invention also provides a kind of high-speed data method of controlling rotation based on FPGA.
A kind of high-speed data method of controlling rotation based on FPGA comprises that blocks of data receives the step of control, the step of blocks of data shunting input control, the step of the streamline control that data are handled, blocks of data is selected the step of output control and the step of blocks of data output control, wherein
Blocks of data receives the step of control, is realized by the idle condition of data sink according to data input distributor;
The step of blocks of data shunting input control after by data sink blocks of data being received, decides the shunting input control of blocks of data according to three data buffer idle conditions;
The step of the streamline control that data are handled, three data buffers be respectively to should there being three working stages, the writing of blocks of data, and the reading of the rotation of blocks of data and blocks of data, the streamline work that data are handled is as follows:
Phase I, the writing of the first data buffer begin block data, second data buffer (is in idle condition with the 3rd data buffer, does not do any action;
Second stage, the rotation of the first data buffer begin block data, the writing of the second data buffer begin block data, the 3rd data buffer is in idle condition and does not do any action;
Phase III, the reading of the first data buffer begin block data, the rotation of the second data buffer begin block data, the writing of the 3rd data buffer begin block data;
The quadravalence section, the writing of the first data buffer begin block data, the second data buffer begin block data read the rotation of the 3rd data buffer begin block data;
Five-stage, the rotation of the first data buffer begin block data, the writing of the second data buffer begin block data, the reading of the 3rd data buffer begin block data;
... by that analogy, cycling forms writing of blocks of data, and the three class pipeline work of reading of the rotation of blocks of data and blocks of data improves the handling capacity of data with this.
Blocks of data is selected the step of output control, decides the selection output control of blocks of data according to the blocks of data output completion status of three data buffers;
The step of blocks of data output control is realized by the completion status of data logger according to data output distributor.
Data sink checks whether data input distributor is in idle condition, if then carry out blocks of data and receive; If not, then not carrying out blocks of data receives.
The input distributor is according to first data buffer, and the order of second data buffer and the 3rd data buffer judges that the step of input completion status is as follows:
A. data inputs distributor checks whether first data buffer is in data input completion status, if then check the input completion status of second data buffer if not, then blocks of data to be dispensed to first data buffer;
B. data inputs distributor checks whether second data buffer is in data input completion status, if then check the input completion status of the 3rd data buffer if not, then blocks of data to be dispensed to second data buffer;
C. data inputs distributor checks whether the 3rd data buffer is in data input completion status, if then check the input completion status of first data buffer if not, then blocks of data to be dispensed to the 3rd data buffer;
Data distribution input control circulation A, B, C step.
The output distributor is according to first data buffer, and the order of second data buffer and the 3rd data buffer judges that the step of output completion status is as follows:
D. data output distributor checks whether first data buffer is in the output completion status, if, then check the output completion status of second data buffer, if not, then data distributor is delivered to data logger with the data output of first data buffer;
E. data output distributor checks whether second data buffer is in the output completion status, if, then check the output completion status of the 3rd data buffer, if not, then data distributor is delivered to data logger with the data output of second data buffer;
F. data output distributor checks whether the 3rd data buffer is in the output completion status, if, then check the output completion status of first data buffer, if not, then data distributor is delivered to data logger with the data output of the 3rd data buffer;
Data are selected output control circulation D, E, F step.
The inventive method is to the employing streamline control of the processing of blocks of data, and it is as follows to work:
Phase I, beginning A step;
Second stage begins the blocks of data rotation of first data buffer, beginning B step;
Phase III begins the blocks of data rotation of the second data buffer memory phase, beginning D step, beginning C step;
The quadravalence section begins the blocks of data rotation of the 3rd data buffer, beginning E step, beginning A step;
Five-stage begins the blocks of data rotation of first data buffer, beginning F step, beginning B step;
... with the workflow of this beginning three class pipeline that circulates.
Data logger checks whether data output distributor has the data output state, if, then data are exported the blocks of data of distributor transmission and exported by data logger, if not, then data logger is not exported.
Adopt all-purpose computer to finish the rotation of view data, data for a 200MByte size, need 15 minutes rotational time, adopt treatment system of the present invention and processing method, need 9 seconds rotational time, can find out obviously that treatment system of the present invention and processing method can realize the high speed processing of data, adopt parallel three class pipeline tupe, the data rotary speed can reach the average treatment speed of 60Mbyte/s.
Description of drawings
Fig. 1 is the structural representation block diagram of control device of the present invention;
Fig. 2 is the three class pipeline operation chart of control device of the present invention;
Fig. 3 is the buffer built-in function finite state machine redirect figure of control device of the present invention;
Fig. 4 is the data flow con-trol flow chart of control method of the present invention.
The specific embodiment
As shown in Figure 1, the structure of control device of the present invention comprises:
Data sink 110 is used for the reception of blocks of data, and blocks of data is a scan line to be printed (in the existing digit printing technology, according to the shower nozzle number of printer complete image being divided into several scan lines) of digital decorating machine; In existing digital decorating machine field, generally be that industrial computer will treat that by software print scanned row rotates, and the present invention is rotated scan line to be printed after industrial computer transfers to data sink 110 again.In order to adapt to the transfer of data between industrial computer and the data sink 110, can be that the scan line that industrial computer earlier will be to be printed is packed, transmit (comprising to the reception of the back data of packing, parsing etc.) to data sink 110 by intermediate equipment again.Intermediate equipment can adopt general flush bonding processor and corresponding storage chip.
Data input distributor 120 connects data sink 110, the first data buffers, 130, the second data buffers 150 and the 3rd data buffer 170, is used for the blocks of data that data sink 110 receives is shunted input control;
First data buffer 130 connects data input distributor 120, the first data circulators 140 and data output distributor 190, is used for the buffer memory of original block data and rotation back blocks of data;
The first data circulator 140 connects first data buffer 130, is used for the rotation of data;
Second data buffer 150 connects data input distributor 120, the second data circulators 160 and data output distributor 190, is used for the buffer memory of original block data and rotation back blocks of data;
The second data circulator 160 connects second data buffer 150, is used for the rotation of data;
The 3rd data buffer 170 connects data input distributor 120, the three data circulators 180 and data output distributor 190, is used for the buffer memory of original block data and rotation back blocks of data;
The 3rd data circulator 180 connects the 3rd data buffer 170, is used for the rotation of data;
Data output distributor 190, connect first data buffer 130, second data buffer 150, the 3rd data buffer 170 and data logger 160, be used for first data buffer 130, the blocks of data that second data buffer, 150, the three data buffers 170 send is selected output control;
Data logger 200 connects data output distributor 190, is used for the also line output of blocks of data, the parallel digit printing machine data shower nozzle that exports to.
The present invention is based on the high-speed data method of controlling rotation of FPGA, comprise that blocks of data receives the step of control, the step of blocks of data shunting input control, the step of the streamline control that data are handled, blocks of data is selected the step of output control and the step of blocks of data output control
Blocks of data receives the step of control, is realized by the idle condition of data sink 110 according to data input distributor 120;
The step of blocks of data shunting input control after by data sink 110 blocks of data being received, decides the shunting input control of blocks of data according to the input unfinished state of first data buffer, 130, the second data buffers, 150, the three data buffers 170;
The step of the streamline control that data are handled, the streamline work that data are handled is as follows:
Phase I, first data buffer 130, the writing of begin block data, second data buffer 150 and the 3rd data buffer 170 are in idle condition, do not do any action;
Second stage, the rotation of first data buffer, 130 begin block data, the writing of second data buffer, 150 begin block data, the 3rd data buffer 170 is in idle condition and does not do any action;
Phase III, first data buffer 130, the reading of begin block data, the rotation of second data buffer, 150 begin block data, the writing of the 3rd data buffer 170 begin block data;
The quadravalence section, first data buffer 130, the writing of begin block data, second data buffer, 150 begin block data read the rotation of the 3rd data buffer 170 begin block data;
Five-stage, first data buffer 130, the rotation of begin block data, the writing of second data buffer, 150 begin block data, the reading of the 3rd data buffer 170 begin block data;
... by that analogy, cycling forms writing of blocks of data, and the three class pipeline work of reading of the rotation of blocks of data and blocks of data improves the handling capacity of data with this.
Blocks of data is selected the step of output control, decides the selection output control of blocks of data according to the blocks of data output completion status of first data buffer, 130, the second data buffers, 150, the three data buffers 170;
The step of blocks of data output control is realized by the completion status of data logger 200 according to data output distributor 190.
As shown in Figure 2, the three class pipeline operation chart of control device of the present invention:
The streamline control that data are handled, it is as follows to work:
Phase I, the blocks of data that begins first data buffer 130 writes;
Second stage begins the blocks of data rotation of first data buffer 130, and the blocks of data that begins second data buffer 150 writes;
Phase III begins the blocks of data rotation of second data buffer 150, and the blocks of data that begins first data buffer 130 is read, and the blocks of data that begins the 3rd data buffer 170 writes;
The quadravalence section begins the blocks of data rotation of the 3rd data buffer 170, and the blocks of data that begins second data buffer 150 is read, and the blocks of data that begins first data buffer 130 writes;
Five-stage begins the blocks of data rotation of first data buffer 130, and the blocks of data that begins the 3rd data buffer 170 is read, and the blocks of data that begins second data buffer 150 writes;
... with the workflow of this beginning three class pipeline that circulates.
As shown in Figure 3, the buffer built-in function finite state machine of control device of the present invention:
Idle condition, any operation is not done in buffer inside;
The data input state, the ablation process of data will be carried out in buffer inside;
The data rotation status, the inner rotary manipulation of carrying out data of buffer;
The data output state, the inner read operation of carrying out data of buffer.
After system resetted, buffer inside was in idle condition, did not do any operation, when request that data write, enter the data input state, carry out the ablation process of data, when data write finish after, enter the data rotation status, carry out the rotary manipulation of data, after the data rotation finishes, enter the data output state, carry out the output function of reading of data, after data output finishes, enter idle condition, the request that waits pending data to write.
As shown in Figure 4, the data-flow-control of control method of the present invention drawing:
After system resetted, the idle marker position of three buffers was judged in blocks of data input, and whether decision receives data, if not, waits for that then the idle marker position is effective, if, beginning the operation of three class pipeline shown in Figure 2, cycling stops until the input of blocks of data.
Claims (4)
1. the high-speed data rotating control assembly based on FPGA is characterized in that, comprising:
Data sink (110) is used for the reception of blocks of data;
Data input distributor (120) connects data sink (110), first data buffer (130), and second data buffer (150) and the 3rd data buffer (170) are used for the blocks of data that data sink (110) receives is shunted input control;
First data buffer (130) connects data input distributor (120), the first data circulator (140) and data output distributor (190) simultaneously,
The buffer memory that is used for original block data and rotation back blocks of data;
The first data circulator (140) is used for the rotation of data;
Second data buffer (150) connects data input distributor (120), the second data circulator (160) and data output distributor (190) simultaneously,
The buffer memory that is used for original block data and rotation back blocks of data;
The second data circulator (160) is used for the rotation of data;
The 3rd data buffer (170) connects data input distributor (120), the 3rd data circulator (180) and data output distributor (190) simultaneously,
The buffer memory that is used for original block data and rotation back blocks of data;
The 3rd data circulator (180) is used for the rotation of data;
Data output distributor (190) and data logger (200) are used for first data buffer (130), and the blocks of data that second data buffer (150) and the 3rd data buffer (170) send is selected output control;
Data logger (200) connects data output distributor (190), is used for the also line output of blocks of data;
Described FPGA is the abbreviation of Field-Programmable Gate Array, i.e. field programmable gate array.
2. high-speed data method of controlling rotation based on FPGA, comprise that blocks of data receives the step of control, the step of blocks of data shunting input control, the step of the streamline control that data are handled, blocks of data is selected the step of output control and the step of blocks of data output control, it is characterized in that:
Blocks of data receives the step of control, the idle condition of data sink (110) judgment data input distributor (120), and when data input distributors (120) were idle, data sink (110) received blocks of data and transfers to data input distributor (120) again;
The step of blocks of data shunting input control, input distributor (120) is according to first data buffer (130), the order of second data buffer (150) and the 3rd data buffer (170) is judged the input completion status, with blocks of data be sent to be in unfinished state and order data buffer the preceding;
The step of the streamline control that data are handled, first data buffer (130), second data buffer (150) and the 3rd data buffer (170) carry out writing of blocks of data, the rotation of blocks of data and the output function of blocks of data to the data block that input distributor (120) sends separately;
Blocks of data is selected the step of output control, output distributor (190) is according to first data buffer (130), the order of second data buffer (150) and the 3rd data buffer (170) is judged the output completion status, select to be in the output completion status and order data buffer the preceding; The step of blocks of data output control is exported according to the completion status of data output distributor by data logger;
Described FPGA is the abbreviation of Field-Programmable Gate Array, i.e. field programmable gate array.
3. high-speed data method of controlling rotation as claimed in claim 2, it is characterized in that, in the step of described blocks of data shunting input control, input distributor (120) is according to first data buffer (130), and the order of second data buffer (150) and the 3rd data buffer (170) judges that the step of input completion status is as follows:
A. data input distributors (120) check whether first data buffer (130) is in data input completion status, if, then check the input completion status of second data buffer (150), if not, then blocks of data is dispensed to first data buffer (130);
B. data inputs distributors (120) check whether second data buffers (150) are in data input completion status, if the input completion status of then checking the 3rd data buffer (150) then is dispensed to blocks of data second data buffer (150) if not;
C. data inputs distributors (120) check whether the 3rd data buffers (170) are in data input completion status, if the input completion status of then checking first data buffer (150) then is dispensed to blocks of data the 3rd data buffer (170) if not;
Data distribution input control circulation A, B, C step.
4. high-speed data method of controlling rotation as claimed in claim 3 is characterized in that, described blocks of data is selected in the step of output control, and output distributor (190) is according to first data buffer
(130), the order of second data buffer (150) and the 3rd data buffer (170) judges that the step of output completion status is as follows:
D. data output distributors (190) check whether first data buffer (130) is in the output completion status, if, then check the output completion status of second data buffer (150), if not, then data distributor (190) is delivered to data logger (200) with the data output of first data buffer (130);
E. data output distributors (190) check whether second data buffer (150) is in the output completion status, if, then check the output completion status of the 3rd data buffer (150), if not, then data distributor (190) is delivered to data logger (200) with the data output of second data buffer (150);
F. data output distributors (190) check whether the 3rd data buffer (170) is in the output completion status, if, then check the output completion status of first data buffer (150), if not, then data distributor (190) is delivered to data logger (200) with the data output of the 3rd data buffer (170);
Data are selected output control circulation D, E, F step.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2002002060A (en) * | 2000-06-23 | 2002-01-08 | Hitachi Ltd | Control circuit system for multiple function printer |
| US7191342B1 (en) * | 2002-06-04 | 2007-03-13 | Xilinx, Inc. | Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002002060A (en) * | 2000-06-23 | 2002-01-08 | Hitachi Ltd | Control circuit system for multiple function printer |
| US7191342B1 (en) * | 2002-06-04 | 2007-03-13 | Xilinx, Inc. | Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames |
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