CN101795136A - Digital-to-analog conversion circuit - Google Patents

Abstract

The invention relates to a digital-to-analog conversion circuit, which belongs to the technical field of electronics. The digital-to-analog conversion circuit comprises a transistor MN0, resistors RA and RB, a capacitor C0, an operational amplifier op and a resistor voltage division array DAC_res_array with a resistance compensation network, wherein the operational amplifier realizes the function of clamping and determines the current of the branch circuit on which the transistor MN0 is positioned together with the resistor RB, thereby reducing the power consumption; the resistor voltage division array DAC_res_array is provided with a resistance compensation network; the control signal of the resistance compensation network is controlled by a digital input signal Digital and can obtain the corresponding compensating resistance value under the conditions of different digital input signals Digital to regulate the equivalent resistance at the AB end of the resistor voltage division array, thereby finally ensuring the conversion accuracy of the DAC circuit. In the invention, the resistance compensation network uses a transmission gate as the element to highly match the conducting resistor of the transmission gate in the resistor voltage division array, thereby enhancing the circuit precision; and the area occupied by the transmission gate is much smaller than the resistor, thereby reducing the chip area and the cost.

Description

A kind of D/A converting circuit

Technical field

The invention belongs to electronic technology field, relate to a kind of have low-power consumption and high-precision digital-to-analogue conversion (DAC) circuit.

Background technology

Interface between DAC Chang Zuowei digital system and the analogue system uses.D/A converting circuit is receiving digitally encoded signal and provides corresponding analog current or the code translator of voltage output signal.When input received the set of number encoded signals, it was benchmark that output produces with certain reference quantity, changes proportional analog signal with input word, and such circuit is called linear DAC.Desirable N bit resolution DAC, its corresponding simulating signal is output as:

Vout＝V _REF(b ₀2 ⁰+b ₁2 ¹+b ₂2 ²+……+b _N-12 ^N-1)

B wherein ₀, b ₁, b ₂... b _nBe the digital code of output, V _REFBe reference level.

The fast development of digital processing technology is had higher requirement to DAC.For example, higher speed, higher resolution, lower power consumption and lower operating voltage etc.DAC structure commonly used generally mainly contains electric resistance partial pressure type DAC, switching capacity type DAC, current drive-type DAC etc.

Because electric resistance partial pressure type DAC (Resistor Divider DAC) is simple in structure, compact, regular, and because the magnitude of voltage of each voltage tap can not be lower than the magnitude of voltage of an adjacent following tap, thereby guaranteed monotonicity, therefore in the field of middle low resolution and middle low speed, be extensive use of.Electric resistance partial pressure type DAC is made up of three parts, as shown in Figure 1.First is a resistance pressure-dividing network, and the resistance of using N similar resistance is with reference level V _REFBe divided into 2 ^NIndividual magnitude of voltage; Second portion is switch arrays, and for given input coding, switch arrays provide a resistive path, will pass to output node corresponding to the level of input coding; For suitable resistance coupling and certain driving force are provided, also need an output buffer as last part.

But there are some shortcomings in existing electric resistance partial pressure type DAC.For example switch arrays are realized by metal-oxide-semiconductor usually, because the influence of metal-oxide-semiconductor conducting resistance makes the output impedance of DAC present the input coding mudulation effect, cause existing electric resistance partial pressure type DAC to exist precision lower, can't satisfy application demand.

Summary of the invention

The objective of the invention is, a kind of D/A converting circuit (DAC) is provided, compare with existing electric resistance partial pressure type DAC, the conducting resistance that the present invention has overcome owing to metal-oxide-semiconductor in the switch arrays causes DAC output impedance to present the problem of input coding mudulation effect, thereby has improved the precision of DAC circuit greatly.

Detailed technology scheme of the present invention is:

A kind of D/A converting circuit, as shown in Figure 2, by operational amplifier op, transistor MN0, resistance R _A, resistance R _B, capacitor C ₀Form with electric resistance partial pressure array DAC_res_array.The positive input terminal of operational amplifier op connects reference voltage signal Vref, negative input end passes through resistance R _BPass through capacitor C in the time of the grid of ground connection, output termination transistor MN0 ₀Ground connection; Resistance R is passed through in the drain electrode of transistor MN0 _AMeet power supply V _D, source electrode connecting resistance dividing potential drop array DAC_res_array port A and export analog signal Vout; The port B of electric resistance partial pressure array DAC_res_array passes through resistance R when connecing the negative input end of operational amplifier op _BGround connection; The digital signal input end of electric resistance partial pressure array DAC_res_array meets digital input signals digital.

Described electric resistance partial pressure array DAC_res_array is by roughly adjusted rheostat R _C, 5 series resistance R that resistance becomes geometric ratio to increase progressively ₀, R ₁, R ₂, R ₃And R ₄, 5 transmission gates, 5 inverters and 1 resnstance transformer network constitute, as shown in Figure 3.Resnstance transformer network and resistance R _C, R ₀, R ₁, R ₂, R ₃, R ₄Be connected on successively between the port B and port A of electric resistance partial pressure array DAC_res_array; Resistance R ₀, R ₁, R ₂, R ₃And R ₄Two ends transmission gate T0, T1, T2, T3 and a T4 respectively in parallel; The 1st signal Digital＜0th among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T0 when connecing the NMOS tube grid of transmission gate T0 by inverter INV0, the 2nd signal Digital＜1st among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T1 when connecing the NMOS tube grid of transmission gate T1 by inverter INV1, the 3rd signal Digital＜2 among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T2 when connecing the NMOS tube grid of transmission gate T2 by inverter INV2, the 4th signal Digital＜3 among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T3, the 5th signal Digital＜4 among the digital input signals digital when connecing the NMOS tube grid of transmission gate T3 by inverter INV3〉connect the gate pmos utmost point of transmission gate T4 when connecing the NMOS tube grid of transmission gate T4 by inverter INV4.

Described resnstance transformer network as shown in Figure 4, is made of 15 transmission gates and 5 inverters.6 transmission gate T10, T11, T12, T13, T14, T15 are connected on port B and the resistance R of electric resistance partial pressure array DAC_res_array successively _CBetween, the grid of the PMOS pipe of these 6 transmission gates is ground connection all, and the grid of NMOS pipe all meets power supply V _DEnd after transmission gate T0a and the T0b series connection is meeting between transmission gate T11 and the T12 another termination port B; The 1st signal Comp_ctrl＜0th among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T0a and T0b, connect the grid of two PMOS pipes of transmission gate T0a and T0b simultaneously by an inverter.End after transmission gate T1a and the T1b series connection is meeting between transmission gate T12 and the T13 another termination port B; The 2nd signal Comp_ctrl＜1st among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T1a and T1b, connect the grid of two PMOS pipes of transmission gate T1a and T1b simultaneously by an inverter.End after transmission gate T2a and the T2b series connection is meeting between transmission gate T13 and the T14 another termination port B; The 3rd signal Comp_ctrl＜2 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T2a and T2b, connect the grid of two PMOS pipes of transmission gate T2a and T2b simultaneously by an inverter.End after transmission gate T3a and the T3b series connection is meeting between transmission gate T14 and the T15 another termination port B; The 4th signal Comp_ctrl＜3 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T3a and T3b, connect the grid of two PMOS pipes of transmission gate T3a and T3b simultaneously by an inverter.End after transmission gate T4a and the T4b series connection is connecing transmission gate T15 and resistance R _CBetween, another termination port B; The 5th signal Comp_ctrl＜4 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T4a and T4b, connect the grid of two PMOS pipes of transmission gate T4a and T4b simultaneously by an inverter.

Described compensating control signal comp_ctrl and digital input signals digital satisfy following relation: when digital input signals digital was 00000, compensating control signal comp_ctrl was 00000; When having one 1 among the digital input signals digital, compensating control signal comp_ctrl is 00001; When having two 1 among the digital input signals digital, compensating control signal comp_ctrl is 00011; When having three 1 among the digital input signals digital, compensating control signal comp_ctrl is 00111; When having four 1 among the digital input signals digital, compensating control signal comp_ctrl is 01111; When digital input signals digital was 11111, compensating control signal comp_ctrl was 11111.

The invention has the beneficial effects as follows:

A kind of low power consumption high-precision DAC circuit provided by the invention, compare with existing electric resistance partial pressure type DAC, owing to adopted the resnstance transformer network, the conducting resistance that has overcome owing to metal-oxide-semiconductor in the switch arrays causes DAC output impedance to present the problem of input coding mudulation effect, thereby improved the precision of DAC circuit greatly, reduced power consumption.And owing to what use in the compensating network all are metal-oxide-semiconductors, but not resistance so also reduced chip area, has reduced cost.

Description of drawings:

Fig. 1 conventional, electric-resistance is divided die mould DAC circuit diagram.

Fig. 2 DAC circuit diagram provided by the invention.

The circuit diagram of electric resistance array among Fig. 3 DAC provided by the invention.

The circuit diagram of electric resistance array internal resistance compensating network among Fig. 4 DAC provided by the invention.

Specific embodiments

Common electric resistance partial pressure type DAC circuit is all by resistance pressure-dividing network, and switch arrays and buffer are formed, as shown in Figure 1.But switch arrays are realized by metal-oxide-semiconductor usually, because the influence of metal-oxide-semiconductor parasitic capacitance and conducting resistance, make the output impedance of DAC present the input coding mudulation effect, just can cause the pressure reduction between adjacent input digit coding inconsistent, the output voltage precision is lower.If in switch arrays, add the resnstance transformer network, be used for compensating the conducting resistance of introducing owing to the MOS switching tube, make that the switch conduction resistance in the electric resistance partial pressure array keeps constant value, just can improve DAC circuit precision.

A kind of D/A converting circuit, as shown in Figure 2, by operational amplifier op, transistor MN0, resistance R _A, resistance R _B, capacitor C ₀Form with electric resistance partial pressure array DAC_res_array.The positive input terminal of operational amplifier op connects reference voltage signal Vref, negative input end passes through resistance R _BPass through capacitor C in the time of the grid of ground connection, output termination transistor MN0 ₀Ground connection; Resistance R is passed through in the drain electrode of transistor MN0 _AMeet power supply V _D, source electrode connecting resistance dividing potential drop array DAC_res_array port A and export analog signal Vout; The port B of electric resistance partial pressure array DAC_res_array passes through resistance R when connecing the negative input end of operational amplifier op _BGround connection; The digital signal input end of electric resistance partial pressure array DAC_res_array meets digital input signals digital.

The effect of operational amplifier op be current potential clamper with inverting input at Vref, i.e. the value of amplifier in-phase input end.Because R _BA terminal voltage value be clamped at reference voltage vref, regulate resistance R _BResistance, can change the current value of electric resistance partial pressure array.Resistance R _BValue is fixing, and then adjustment pipe MN0 place branch current I is constant is:

$I=\frac{V_{\mathrm{ref}}}{R_B}---\left(1\right)$

This shows that DAC circuit of the present invention has the quiescent current that can control, make the power consumption under the various output situations all lower.

Described electric resistance partial pressure array DAC_res_array is by roughly adjusted rheostat R _C, 5 series resistance R that resistance becomes geometric ratio to increase progressively ₀, R ₁, R ₂, R ₃And R ₄, 5 transmission gates, 5 inverters and 1 resnstance transformer network constitute, as shown in Figure 3.Resnstance transformer network and resistance R _C, R ₀, R ₁, R ₂, R ₃, R ₄Be connected on successively between the port B and port A of electric resistance partial pressure array DAC_res_array; Resistance R ₀, R ₁, R ₂, R ₃And R ₄Two ends transmission gate T0, T1, T2, T3 and a T4 respectively in parallel; The 1st signal Digital＜0th among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T0 when connecing the NMOS tube grid of transmission gate T0 by inverter INV0, the 2nd signal Digital＜1st among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T1 when connecing the NMOS tube grid of transmission gate T1 by inverter INV1, the 3rd signal Digital＜2 among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T2 when connecing the NMOS tube grid of transmission gate T2 by inverter INV2, the 4th signal Digital＜3 among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T3, the 5th signal Digital＜4 among the digital input signals digital when connecing the NMOS tube grid of transmission gate T3 by inverter INV3〉connect the gate pmos utmost point of transmission gate T4 when connecing the NMOS tube grid of transmission gate T4 by inverter INV4.

As Digital＜n〉when signal was 0, the gate pmos pole tension of its pairing transmission gate Tn was high, NMOS tube grid voltage is low, so transmission gate Tn closes the resistance R that is connected in parallel with this transmission gate _nBe access between port A, the B of electric resistance partial pressure array; And as Digital＜n when signal was 1, the gate pmos pole tension of its pairing transmission gate Tn was low, NMOS tube grid voltage is high, thus transmission gate Tn open because the conducting resistance of transmission gate is significantly less than the resistance R that is connected in parallel with it _n, resistance R _nBe equivalent to by short circuit the conducting resistance R of transmission gate _GBe access between port A, the B of electric resistance partial pressure array.As Digital＜4:0〉when signal changes, the transmission gate conducting resistance R that is access in _GNumber also can change, will cause the input coding mudulation effect like this, not of uniform size the causing of step that makes adjacent two binary code corresponding simulating output causes error bigger.So just must introduce a resnstance transformer network, come the electric resistance partial pressure array is compensated.

Described resnstance transformer network as shown in Figure 4, is made of 15 transmission gates and 5 inverters.6 transmission gate T10, T11, T12, T13, T14, T15 are connected on port B and the resistance R of electric resistance partial pressure array DAC_res_array successively _CBetween, the grid of the PMOS pipe of these 6 transmission gates is ground connection all, and the grid of NMOS pipe all meets power supply V _DEnd after transmission gate T0a and the T0b series connection is meeting between transmission gate T11 and the T12 another termination port B; The 1st signal Comp_ctrl＜0th among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T0a and T0b, connect the grid of two PMOS pipes of transmission gate T0a and T0b simultaneously by an inverter.End after transmission gate T1a and the T1b series connection is meeting between transmission gate T12 and the T13 another termination port B; The 2nd signal comp_ctrl＜1st among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T1a and T1b, connect the grid of two PMOS pipes of transmission gate T1a and T1b simultaneously by an inverter.End after transmission gate T2a and the T2b series connection is meeting between transmission gate T13 and the T14 another termination port B; The 3rd signal Comp_ctrl＜2 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T2a and T2b, connect the grid of two PMOS pipes of transmission gate T2a and T2b simultaneously by an inverter.End after transmission gate T3a and the T3b series connection is meeting between transmission gate T14 and the T15 another termination port B; The 4th signal Comp_ctrl＜3 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T3a and T3b, connect the grid of two PMOS pipes of transmission gate T3a and T3b simultaneously by an inverter.End after transmission gate T4a and the T4b series connection is connecing transmission gate T15 and resistance R _CBetween, another termination port B; The 5th signal Comp_ctrl＜4 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T4a and T4b, connect the grid of two PMOS pipes of transmission gate T4a and T4b simultaneously by an inverter.

Resnstance transformer network of the present invention adopts the R-2R network configuration, simultaneously in order to guarantee the compensation levels of precision to the transmission gate conducting resistance, with the element of transmission gate as this circuit." 2R " part in this circuit, i.e. the transmission gate Tna and the Tnb of two series connection are by Comp_ctrl＜n〉control of signal realization switch.And the Comp_ctrl signal is subjected to the control of digital input signals Digital.Be achieved as follows logic by programming: " 1 " that occurs in the Digital signal is all moved to right, be input among the Comp_ctrl again, promptly 1 among the Comp_ctrl begins to occur to a high position from lowest order, 1 the number that 1 number equals that Digital occurs.For example, when the Digital signal was 0 entirely, Comp_ctrl was 00000, and the all-in resistance of resnstance transformer network is 6R _GWhen one " 1 " only appearred in the Digital signal, Comp_ctrl was 00001, among the transmission gate T0a and T0b place in circuit in the resnstance transformer lattice network, with the T1 that connects, the T0 parallel connection, these four transmission gate equivalences become a transmission gate, at this moment, the all-in resistance of resnstance transformer network is 5R _GThe rest may be inferred, and when the Digital signal was 1 entirely, Comp_ctrl was 11111, and the all-in resistance of resnstance transformer network is R _GIn conjunction with the operation principle of electric resistance partial pressure array recited above, as can be known, no matter how the Digital signal changes, and the number of the transmission gate conducting resistance that inserts in the electric resistance partial pressure array is constant, is 6R _GLike this, the voltage of adjacent two binary digit input signal Digital correspondences output difference is just fixing.

When Digital is 0 entirely, the resistance value maximum between A, B, R _AB=6R _G+ R _C+ R ₀+ R ₁+ R ₂+ R ₃+ R ₄, corresponding output voltage V out is maximum Vout (max); When Digital is 1 entirely, the resistance value minimum between A, B, R _AB=6R _G+ R _C, corresponding output voltage V out is minimum value Vout (min), by regulating R _CCan obtain required minimum output voltage.According to formula

$V_{\mathrm{LSB}}=\frac{V_{\mathrm{out}}\left(\max \right)-V_{\mathrm{out}}\left(\min \right)}{2^N-1}---\left(2\right)$

Can obtain the minimum analog quantity that DAC can differentiate.

The resistance R of the electric resistance partial pressure array the inside in the DAC circuit of the present invention ₀, R ₁, R ₂, R ₃, R ₄Proportional the increasing progressively of resistance.The resistance computing formula is

R _n＝2 ⁿR (3)

In the formula, R is a unit resistance, and the value of this resistance is determined by the minimum analog quantity in electric current in the formula 4 and the formula 6.

$R=\frac{V_{\mathrm{LSB}}}{I}=\frac{V_{\mathrm{out}}\left(\max \right)-V_{\mathrm{out}}\left(\min \right)}{(2^N-1)I}---\left(4\right)$

According to specific requirement, set parameters such as resistor current, can derive the functional relation between output voltage and supplied with digital signal,

$V_{\mathrm{out}}=\frac{V_{\mathrm{ref}}}{R_B}(R_B+6R_G+R_C+\underset{n=0}{\overset{4}{\mathrm{\&Sigma;}}}\mathrm{Didital}<n>R_n)---\left(5\right)$

DAC circuit of the present invention can carry out the position expansion, and Output Voltage Formula is as follows

$V_{\mathrm{out}}=\frac{V_{\mathrm{ref}}}{R_B}[R_B+(n+1)R_G+R_C+\underset{i=0}{\overset{n}{\mathrm{\&Sigma;}}}\mathrm{Didital}<i>R_i]---\left(6\right)$

The present invention can be applicable in the design of any electric resistance partial pressure type DAC, by transmission gate resnstance transformer network, can eliminate the coded modulation effect among traditional DAC, improves the precision of DAC greatly.In the design of this DAC, the quiescent current except that amplifier has only one the tunnel, and can be by regulating reference voltage and resistance R _BChange, can obtain the very low high accuracy DAC circuit of quiescent dissipation.

Claims (1)

1. D/A converting circuit is by operational amplifier op, transistor MN0, resistance R _A, resistance R _B, capacitor C ₀Form with electric resistance partial pressure array DAC_res_array; The positive input terminal of operational amplifier op connects reference voltage signal Vref, negative input end passes through resistance R _BPass through capacitor C in the time of the grid of ground connection, output termination transistor MN0 ₀Ground connection; Resistance R is passed through in the drain electrode of transistor MN0 _AMeet power supply V _D, source electrode connecting resistance dividing potential drop array DAC_res_array port A and export analog signal Vout; The port B of electric resistance partial pressure array DAC_res_array passes through resistance R when connecing the negative input end of operational amplifier op _BGround connection; The digital signal input end of electric resistance partial pressure array DAC_res_array meets digital input signals digital;

It is characterized in that:

Described electric resistance partial pressure array DAC_res_array is by roughly adjusted rheostat R _C, 5 series resistance R that resistance becomes geometric ratio to increase progressively ₀, R ₁, R ₂, R ₃And R ₄, 5 transmission gates, 5 inverters and 1 resnstance transformer network constitute; Resnstance transformer network and resistance R _C, R ₀, R ₁, R ₂, R ₃, R ₄Be connected on successively between the port B and port A of electric resistance partial pressure array DAC_res_array; Resistance R ₀, R ₁, R ₂, R ₃And R ₄Two ends transmission gate T0, T1, T2, T3 and a T4 respectively in parallel; The 1st signal Digital＜0th among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T0 when connecing the NMOS tube grid of transmission gate T0 by inverter INV0, the 2nd signal Digital＜1st among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T1 when connecing the NMOS tube grid of transmission gate T1 by inverter INV1, the 3rd signal Digital＜2 among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T2 when connecing the NMOS tube grid of transmission gate T2 by inverter INV2, the 4th signal Digital＜3 among the digital input signals digital〉connect the gate pmos utmost point of transmission gate T3, the 5th signal Digital＜4 among the digital input signals digital when connecing the NMOS tube grid of transmission gate T3 by inverter INV3〉connect the gate pmos utmost point of transmission gate T4 when connecing the NMOS tube grid of transmission gate T4 by inverter INV4;

Described resnstance transformer network is made of 15 transmission gates and 5 inverters; 6 transmission gate T10, T11, T12, T13, T14, T15 are connected on port B and the resistance R of electric resistance partial pressure array DAC_res_array successively _CBetween, the grid of the PMOS pipe of these 6 transmission gates is ground connection all, and the grid of NMOS pipe all meets power supply V _DEnd after transmission gate T0a and the T0b series connection is meeting between transmission gate T11 and the T12 another termination port B; The 1st signal Comp_ctrl＜0th among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T0a and T0b, connect the grid of two PMOS pipes of transmission gate T0a and T0b simultaneously by an inverter; End after transmission gate T1a and the T1b series connection is meeting between transmission gate T12 and the T13 another termination port B; The 2nd signal Comp_ctrl＜1st among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T1a and T1b, connect the grid of two PMOS pipes of transmission gate T1a and T1b simultaneously by an inverter; End after transmission gate T2a and the T2b series connection is meeting between transmission gate T13 and the T14 another termination port B; The 3rd signal Comp_ctrl＜2 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T2a and T2b, connect the grid of two PMOS pipes of transmission gate T2a and T2b simultaneously by an inverter; End after transmission gate T3a and the T3b series connection is meeting between transmission gate T14 and the T15 another termination port B; The 4th signal Comp_ctrl＜3 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T3a and T3b, connect the grid of two PMOS pipes of transmission gate T3a and T3b simultaneously by an inverter; End after transmission gate T4a and the T4b series connection is connecing transmission gate T15 and resistance R _CBetween, another termination port B; The 5th signal Comp_ctrl＜4 among the compensating control signal comp_ctrl〉connect the grid of two NMOS pipes of transmission gate T4a and T4b, connect the grid of two PMOS pipes of transmission gate T4a and T4b simultaneously by an inverter.

Described compensating control signal comp_ctrl and digital input signals digital satisfy following relation: when digital input signals digital was 00000, compensating control signal comp_ctrl was 00000; When having one 1 among the digital input signals digital, compensating control signal comp_ctrl is 00001; When having two 1 among the digital input signals digital, compensating control signal comp_ctrl is 00011; When having three 1 among the digital input signals digital, compensating control signal comp_ctrl is 00111; When having four 1 among the digital input signals digital, compensating control signal comp_ctrl is 01111; When digital input signals digital was 11111, compensating control signal comp_ctrl was 11111.

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