CN101789265A - FLASH express programming method for Power PC system - Google Patents
FLASH express programming method for Power PC system Download PDFInfo
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- CN101789265A CN101789265A CN200910312763A CN200910312763A CN101789265A CN 101789265 A CN101789265 A CN 101789265A CN 200910312763 A CN200910312763 A CN 200910312763A CN 200910312763 A CN200910312763 A CN 200910312763A CN 101789265 A CN101789265 A CN 101789265A
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Abstract
The invention discloses a FLASH express programming method for a Power PC system, comprising the steps as follows: (1) using the initialization function of a register of a Power PC processor Boot Sequencer to start Bootloader I from the external part; and (2) using a serial interface to store and download an FLASH image file or Bootloader II from a storage by the Bootloader I, and downloading an image file via a high-speed interface by the Bootloader II if the Bootloader II is stored and downloaded by the Bootloader I from the storage via the serial interface. The invention can greatly improve the production efficiency and lower the cost, and the programming procedures can automatically finish, thus greatly reducing operation steps and operation time.
Description
Technical field
The present invention relates to the PowerPC series processors, especially relate to a kind of method the FLASH of PowerPC system fast programming.
Background technology
The PowerPC series processors has a wide range of applications in various communications electronics products, in these Embedded Application, generally uses FLASH storage code and data.The FLASH chip when dispatching from the factory without any content, need the user voluntarily it to be programmed, can certainly require FLASH manufacturer or third party to write the data of customization, but need the order of some like this or pay certain expense according to requirement of client.In actual applications, after the assembling of having finished PCB, by the processor on the plate it is programmed again often.
To being assemblied in the FLASH programming on the PCB, can use programmable device it to be programmed with the pin of FLASH being caused a socket when the design PCB by this socket.But the number of pins of FLASH a lot (especially NOR-FLASH), this method is also impracticable.Also can utilize the jtag interface of processor, can transmit by this interface and want data programmed and its bus of control to carry out programming operation, but the shortcoming of this method be to use expensive debugger and complicated IDE software operation, efficient is very low.Use a kind of method of the programming of FLASH fast to raise the efficiency greatly and to reduce cost.
Summary of the invention
The purpose of this invention is to provide a kind of production efficiency height, method that cost is low to the FLASH of PowerPC system fast programming.
In order to achieve the above object, the present invention adopts following technical scheme: a kind of method to the FLASH of PowerPC system fast programming, at first utilize the initialization of register function of PowerPC processor B oot Sequencer to start small-sized Bootloader I from the outside, promptly utilize the function of Boot Sequencer configuration register to load and move a small-sized BootloaderI; Secondly, Bootloader I uses serial line interface to download the BootloaderII of FLASH image file or telotism from memory stores, be to download second level Bootloader II or directly download the FLASH image file by serial line interfaces such as SPI after BootloaderI starts, if Bootloader I is to use serial line interface to download BootloaderII from memory stores, then BootloaderII downloads image file by high-speed interface, be that Bootloader II can be by the bigger image file of interface file in download size more at a high speed, if Bootloader I uses serial line interface to download the FLASH image file from memory stores, then programming finishes.
During the such file of described Bootloader II programming JFFS, residual F LASH sector is carried out the mark of CLEAN-MARKER.
Described serial line interface is the interface that SPI interface or NAND FLASH interface or plug connectors such as SD interface or MMC interface are easy to connect.
Described high-speed interface is Ethernet or high-speed synchronous serial ports or USB interface or blue tooth interface.
Among the present invention, many PowerPC processors all comprise one and are called Boot Sequencer functional module, some critical registers configurations that it can initialization processor.Its function of initializing principle of work is roughly as follows: behind processor reset, if hardware pin has been selected BootSequncer (being boot sequence) pattern, inner Boot Sequencer module begins to take out register configuration data (address and the data that comprise register) from the IIC storer of outside, then the data of correspondence is write in the corresponding address.Utilize this function also can carry out proper configuration, a small-sized Bootloader I is copied among the SDRAM go then, and carry out SDRAM (Synchronous Dynamic Random Access Memory) controller of processor.Utilize this small-sized Bootloader I will be stored in the FLASH mirror image data of external memory storage or the BootloaderII programming of perfect in shape and function in FLASH by interfaces such as SPI.Why use a small-sized Bootloader I, be because the space that can visit of iic bus is limited, the maximum address space that can only visit 64KB, add Boot Sequencer and need memory address and data simultaneously, the size of Bootloader I has very strict restriction, also can only realize limited function.The storer of interfaces such as SPI then can be stored bigger file.Bootloader II will support communication interface at a high speed, as Ethernet etc., can download to this locality by the file that volume is bigger, and programming be in FLASH.For file system, can also write the mark of CLEAN-MARKER in the residue sector of its subregion as JFFS.System can reduce greatly in the time that for the first time file system is write like this.
IIC interface and SPI interface pin are seldom, IIC storer, SPI storer and the startup wire jumper interface form with subcard or frock is connected on the mainboard, after mainboard resetted, above-mentioned programming step just can be finished automatically, had reduced the step and the time of operation greatly.
The invention has the beneficial effects as follows: can enhance productivity greatly and reduce cost, programming step can be finished automatically, has reduced operation steps and running time greatly.
Description of drawings
The present invention will illustrate by example and with reference to the mode of accompanying drawing, wherein:
Fig. 1 is the FLASH subregion exemplary plot of embedded PowerPC system;
Fig. 2 is the storer connection diagram;
Fig. 3 is the process flow diagram of one-level Bootloader (Bootloader I) programming FLASH;
Fig. 4 is the process flow diagram of two-stage Bootloader (Bootloader II) programming FLASH.
Embodiment
Disclosed all features in this instructions, or the step in disclosed all methods or the process except mutually exclusive feature and/or step, all can make up by any way.
Disclosed arbitrary feature in this instructions (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
A kind of method to the FLASH of PowerPC system fast programming, at first utilize the initialization of register function of PowerPC processor B oot Sequencer to start small-sized BootloaderI from the outside, depend on whether utilize Boot Sequencer to load executable routine data; Secondly, serial line interfaces such as Bootloader I use SPI are downloaded the BootloaderII of FLASH mirror image or telotism from memory stores, interface is not limited only to the SPI interface, the interface that connector is easy to connect is all right, as NANDFLASH interface or SD interface or MMC interface, in this step, if Bootloader I is to use serial line interface such as SPI to download the FLASH image file from memory stores, that programming finishes.If Bootloader I is to use serial line interfaces such as SPI from the complete BootloaderII of memory stores download function, at last, Bootloader II also can be by the bigger data file of high speed interfaces such as Ethernet transmission, be that Bootloader II also can download image file by high speed interfaces such as Ethernets, high-speed interface is not limited only to Ethernet interface, can also be high-speed synchronous serial ports or USB interface or blue tooth interface.
When Bootloader II programming JFFS file, the mark of CLEAN-MARKER is carried out in residual F LASH sector, be not limited only to the JFFS file system, as long as this document system need make sign in free sector can.
The FLASH data of general embedded PowerPC system as shown in Figure 1, each subregion can be used as independent file and preserves, and also the FLASH mirror image can be made into a file.When whole FLASH mirror image is no more than SPIROM big or small, can be directly burned by BootloaderI, during oversize, can transmit the mirror image of each subregion respectively by network by Bootloader II, programming is to FLASH then.The connection of total system starts configuration wire jumper, IIC ROM and SPIROM and is connected to mainboard by connector as shown in Figure 2.
When SPIROM stored whole FLASH mirror image, whole programming process as shown in Figure 3.After MPU resetted, BootSequencer was good with the register configuration of sdram controller by iic bus, subsequently the code of Bootloader I was moved SDRAM and operation.BootloaderI reads the FLASH mirror image among the SPI ROM, and programming is in FLASH then.Whole operation is finished, and restarts system after removing connector, and MPU just can start in FLASH.
When whole mirror image was big, the content of each subregion was divided into independent file.Whole programming process as shown in Figure 4, the step of front is similar to last a kind of situation.Different is that BootloaderI moves internal memory and operation with the Bootloader II in the SPIROM.High-speed network appliance is supported in the perfect in shape and function of Bootloader II, and it downloads and write FLASH with the image file of each subregion.During at the file system of JFFS type, also the sign with free sector writes, and then whole operation is finished.
BootLoader is exactly one section small routine of operation before the operating system nucleus operation.By this section small routine, can initiating hardware equipment, set up the mapping graph of memory headroom, thus take the hardware environment of system to a proper state, so that be ready to correct environment for final call operation system kernel.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.
Claims (4)
1. method to the FLASH of PowerPC system fast programming, it is characterized in that: method step is:
(1), utilize the initialization of register function of PowePC processor B oot Sequencer to start BootloaderI from the outside;
(2), described Bootloader I uses serial line interface to download FLASH image file or BootloaderII from memory stores, if BootloaderI is to use serial line interface to download Bootloader II from memory stores, then Bootloader II downloads image file by high-speed interface.
2. a kind of method to the FLASH of PowerPC system fast programming according to claim 1 is characterized in that: during the such file of described Bootloader II programming JFFS, residual F LASH sector is carried out the mark of CLEAN-MARKER.
3. a kind of method to the FLASH of PowerPC system fast programming according to claim 1 is characterized in that: described serial line interface is SPI interface or NAND FLASH interface or SD interface or MMC interface.
4. a kind of method to the FLASH of PowerPC system fast programming according to claim 1 is characterized in that: described high-speed interface is Ethernet or high-speed synchronous serial ports or USB interface or blue tooth interface.
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| CN2009103127639A CN101789265B (en) | 2009-12-31 | 2009-12-31 | FLASH express programming method for Power PC system |
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| CN2009103127639A CN101789265B (en) | 2009-12-31 | 2009-12-31 | FLASH express programming method for Power PC system |
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| CN101789265A true CN101789265A (en) | 2010-07-28 |
| CN101789265B CN101789265B (en) | 2012-11-14 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012062132A1 (en) * | 2010-11-10 | 2012-05-18 | 中兴通讯股份有限公司 | Self-programming method and device for file system based on nand flash memory |
| CN104751881A (en) * | 2013-12-27 | 2015-07-01 | 纬创资通股份有限公司 | flash memory burning method |
| CN105117255A (en) * | 2015-08-28 | 2015-12-02 | 青岛中星微电子有限公司 | Boot method and apparatus for BootLoader program |
| CN105302593A (en) * | 2015-07-17 | 2016-02-03 | 天津市英贝特航天科技有限公司 | Remote upgrade system and method of PowerPC motherboard |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416451C (en) * | 2001-12-11 | 2008-09-03 | 中兴通讯股份有限公司 | Embedded system software loading device and method |
| US7493478B2 (en) * | 2002-12-05 | 2009-02-17 | International Business Machines Corporation | Enhanced processor virtualization mechanism via saving and restoring soft processor/system states |
| CN100432986C (en) * | 2005-06-17 | 2008-11-12 | 艾默生网络能源系统有限公司 | fast programming/debugging device |
| JP2010500682A (en) * | 2006-08-15 | 2010-01-07 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Flash memory access circuit |
-
2009
- 2009-12-31 CN CN2009103127639A patent/CN101789265B/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| 谭征华等: "《基于串口的PowerPC_bootloader的开发》", 《计算机技术与发展》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012062132A1 (en) * | 2010-11-10 | 2012-05-18 | 中兴通讯股份有限公司 | Self-programming method and device for file system based on nand flash memory |
| CN104751881A (en) * | 2013-12-27 | 2015-07-01 | 纬创资通股份有限公司 | flash memory burning method |
| CN104751881B (en) * | 2013-12-27 | 2018-01-05 | 纬创资通股份有限公司 | flash memory burning method |
| CN105302593A (en) * | 2015-07-17 | 2016-02-03 | 天津市英贝特航天科技有限公司 | Remote upgrade system and method of PowerPC motherboard |
| CN105302593B (en) * | 2015-07-17 | 2018-12-18 | 天津市英贝特航天科技有限公司 | The remote update system and method for PowerPC motherboard |
| CN105117255A (en) * | 2015-08-28 | 2015-12-02 | 青岛中星微电子有限公司 | Boot method and apparatus for BootLoader program |
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| CN101789265B (en) | 2012-11-14 |
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