CN101789265B

CN101789265B - FLASH express programming method for Power PC system

Info

Publication number: CN101789265B
Application number: CN2009103127639A
Authority: CN
Inventors: 周祺睿
Original assignee: NTS Technology Chengdu Co Ltd
Current assignee: NTS Technology Chengdu Co Ltd
Priority date: 2009-12-31
Filing date: 2009-12-31
Publication date: 2012-11-14
Anticipated expiration: 2029-12-31
Also published as: CN101789265A

Abstract

The invention discloses a FLASH express programming method for a Power PC system, which comprises the steps as follows: (1) using the initialization function of a register of a Power PC processor Boot Sequencer to start Bootloader I from the external part; and (2) using a serial interface to store and download an FLASH image file or Bootloader II from a storage by the Bootloader I, and downloading an image file via a high-speed interface by the Bootloader II if the Bootloader II is stored and downloaded by the Bootloader I from the storage via the serial interface. The invention can greatly improve the production efficiency and lower the cost. The programming procedures can automatically finish, thus greatly reducing operation steps and the operation time.

Description

A kind of method to the FLASH of PowerPC system fast programming

Technical field

The present invention relates to the PowerPC series processors, especially relate to a kind of method the FLASH of PowerPC system fast programming.

Background technology

The PowerPC series processors has a wide range of applications in various communications electronics products, in these Embedded Application, generally uses FLASH storage code and data.The FLASH chip has no content when dispatching from the factory; Need the user voluntarily it to be programmed; Can certainly require FLASH manufacturer or third party to write the data of customization, but need the order of some like this or pay certain expense according to requirement of client.In practical application, after the assembling of having accomplished PCB, through the processor on the plate it is programmed again often.

To being assemblied in the FLASH programming on the PCB, can use programmable device it to be programmed with the pin of FLASH being caused a socket when the design PCB through this socket.But the number of pins of FLASH a lot (especially NOR-FLASH), this method is also impracticable.Also can utilize the jtag interface of processor, can transmit through this interface and want data programmed and its bus of control to carry out programming operation, but the shortcoming of this method be to use expensive debugger and complicated IDE software operation, efficient is very low.Use a kind of method of the programming of FLASH fast to raise the efficiency greatly and to reduce cost.

Summary of the invention

The purpose of this invention is to provide the method that a kind of production efficiency is high, cost is low to the FLASH of PowerPC system fast programming.

In order to achieve the above object; The present invention adopts following technical scheme: a kind of method to the FLASH of PowerPC system fast programming; At first utilize the initialization of register function of PowerPC processor B oot Sequencer to start small-sized Bootloader I from the outside, promptly utilize the function of Boot Sequencer configuration register to load and move a small-sized BootloaderI; Secondly; Bootloader I uses serial line interface to download the BootloaderII of FLASH image file or telotism from memory stores; Be to download second level Bootloader II or directly download the FLASH image file through serial line interfaces such as SPI after BootloaderI starts; If Bootloader I is to use serial line interface to download BootloaderII from memory stores; Then BootloaderII downloads image file through high-speed interface; Be that Bootloader II can be through the bigger image file of interface file in download size more at a high speed, if Bootloader I uses serial line interface to download the FLASH image file from memory stores, then programming finishes.

During the such file of said Bootloader II programming JFFS, residual F LASH sector is carried out the mark of CLEAN-MARKER.

Said serial line interface is the interface that SPI interface or NAND FLASH interface or plug connectors such as SD interface or MMC interface are easy to connect.

Said high-speed interface is Ethernet or high-speed synchronous serial ports or USB interface or blue tooth interface.

Among the present invention, many PowerPC processors all comprise one and are called Boot Sequencer functional module, some critical registers configurations that it can initialization processor.Its function of initializing principle of work is roughly following: behind processor reset; If hardware pin has been selected BootSequncer (being boot sequence) pattern; Inner Boot Sequencer module begins to take out register configuration data (address and the data that comprise register) from the IIC storer of outside, writes the data of correspondence in the corresponding address then.Utilize this function also can carry out proper configuration, a small-sized Bootloader I is copied among the SDRAM go then, and carry out SDRAM (Synchronous Dynamic Random Access Memory) controller of processor.Utilize FLASH mirror image data or the BootloaderII programming of perfect in shape and function that this small-sized Bootloader I can will be stored in external memory storage through interfaces such as SPI in FLASH.Why use a small-sized Bootloader I; Be because the space that can visit of iic bus is limited; The maximum address space that can only visit 64KB; Adding Boot Sequencer needs memory address and data simultaneously, and the size of Bootloader I has very strict restriction, also can only realize limited function.The storer of interfaces such as SPI then can be stored bigger file.Bootloader II will support communication interface at a high speed, like Ethernet etc., can download to this locality by the file that volume is bigger, and programming be in FLASH.For file system, can also write the mark of CLEAN-MARKER in the residue sector of its subregion as JFFS.System can reduce in the time that for the first time file system is write greatly like this.

IIC interface and SPI interface pin are seldom; IIC storer, SPI storer and the startup wire jumper interface form with subcard or frock is connected on the mainboard; After mainboard resetted, above-mentioned programming step just can be accomplished automatically, had reduced the step and the time of operation greatly.

The invention has the beneficial effects as follows: can enhance productivity greatly and reduce cost, programming step can be accomplished automatically, has reduced operation steps and running time greatly.

Description of drawings

The present invention will explain through example and with reference to the mode of accompanying drawing, wherein:

Fig. 1 is the FLASH subregion exemplary plot of embedded PowerPC system;

Fig. 2 connects synoptic diagram for storer;

Fig. 3 is the process flow diagram of one-level Bootloader (Bootloader I) programming FLASH;

Fig. 4 is the process flow diagram of two-stage Bootloader (Bootloader II) programming FLASH.

Embodiment

Disclosed all characteristics in this instructions, or the step in disclosed all methods or the process except mutually exclusive characteristic and/or the step, all can make up by any way.

Disclosed arbitrary characteristic in this instructions (comprising any accessory claim, summary and accompanying drawing) is only if special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, only if special narration, each characteristic is an example in a series of equivalences or the similar characteristics.

A kind of method to the FLASH of PowerPC system fast programming; At first utilize the initialization of register function of PowerPC processor B oot Sequencer to start small-sized BootloaderI from the outside, depend on whether utilize Boot Sequencer to load executable routine data; Secondly; Serial line interfaces such as Bootloader I use SPI are from the BootloaderII of memory stores download FLASH mirror image or telotism, and interface is not limited only to the SPI interface, and the interface that connector is easy to connect is all right; Like NANDFLASH interface or SD interface or MMC interface; In this step, if Bootloader I is to use serial line interface such as SPI to download the FLASH image file from memory stores, that programming finishes.If Bootloader I is to use serial line interfaces such as SPI from the complete BootloaderII of memory stores download function; At last; Bootloader II also can be through the bigger data file of high-speed interfaces such as Ethernet transmission; Be that Bootloader II also can download image file through high-speed interfaces such as Ethernets, high-speed interface is not limited only to Ethernet interface, can also be high-speed synchronous serial ports or USB interface or blue tooth interface.

When Bootloader II programming JFFS file, the mark of CLEAN-MARKER is carried out in residual F LASH sector, be not limited only to the JFFS file system, as long as this document system need make sign in free sector can.

The FLASH data of general embedded PowerPC system are as shown in Figure 1, and each subregion can be used as independent file and preserves, and also can the FLASH mirror image be made into a file.When whole FLASH mirror image is no more than SPIROM big or small, can be directly burned through BootloaderI, during oversize, can transmit the mirror image of each subregion respectively through network through Bootloader II, programming is to FLASH then.The connection of total system is as shown in Figure 2, starts configuration wire jumper, IIC ROM and SPIROM and is connected to mainboard through connector.

When SPIROM stored whole FLASH mirror image, whole programming process was as shown in Figure 3.After MPU resetted, BootSequencer was good with the register configuration of sdram controller through iic bus, subsequently the code of Bootloader I was moved SDRAM and operation.BootloaderI reads the FLASH mirror image among the SPI ROM, and programming is in FLASH then.Whole operation is accomplished, and restarts system after removing connector, and MPU just can start in FLASH.

When whole mirror image was big, the content of each subregion was divided into independent file.Whole programming process is as shown in Figure 4, and the step of front is similar with last a kind of situation.Different is that BootloaderI moves internal memory and operation with the Bootloader II in the SPIROM.High-speed network appliance is supported in the perfect in shape and function of Bootloader II, and it downloads and write FLASH with the image file of each subregion.During to the file system of JFFS type, also the sign with free sector writes, and then whole operation is accomplished.

BootLoader is exactly one section small routine of operation before the operating system nucleus operation.Through this section small routine, can initiating hardware equipment, set up the mapping graph of memory headroom, thus take the hardware environment of system to a proper state, so that be ready to correct environment for final call operation system kernel.

The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.

Claims

1. method to the FLASH of PowerPC system fast programming is characterized in that may further comprise the steps:

(1), the initialization of register function of utilizing PowerPC processor B oot Sequencer starts the Bootloader I from the outside, said Bootloader I is the one-level bootstrap loader; Saidly start said Bootloader I from the outside and comprise: Boot Sequencer module begins to take out the register configuration data from the IIC storer of outside; Said register configuration data comprise the address and the data of register, said Bootloader I is copied among the SDRAM go then;

(2), through moving the Bootloader I among the said SDRAM of copying to; Use serial line interface to download FLASH image file or Bootloader II from external memory stores; Said Bootloader II is the two-stage bootstrap loader; If use serial line interface to download said Bootloader II, then use high-speed interface to download the FLASH image file through operation Bootloader II from said external memory stores.

2. according to the described a kind of method of claim 1, it is characterized in that: during the such file of said Bootloader II programming JFFS, residual F LASH sector is carried out the mark of CLEAN-MARKER the FLASH of PowerPC system fast programming.

3. according to the described a kind of method to the FLASH of PowerPC system fast programming of claim 1, it is characterized in that: said serial line interface is SPI interface or NAND FLASH interface or SD interface or MMC interface.

4. according to the described a kind of method to the FLASH of PowerPC system fast programming of claim 1, it is characterized in that: said high-speed interface is Ethernet interface or high-speed synchronous serial ports or USB interface or blue tooth interface.