CN101789222A - Method utilizing data enable signal to control time sequence of display device and time sequence control circuit - Google Patents
Method utilizing data enable signal to control time sequence of display device and time sequence control circuit Download PDFInfo
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- CN101789222A CN101789222A CN200910003392A CN200910003392A CN101789222A CN 101789222 A CN101789222 A CN 101789222A CN 200910003392 A CN200910003392 A CN 200910003392A CN 200910003392 A CN200910003392 A CN 200910003392A CN 101789222 A CN101789222 A CN 101789222A
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Abstract
The invention relates to a method utilizing a data enable signal to control time sequence of a display device and a time sequence control circuit. In a first display period of the display device, a first count value is recorded at the position of the rising edge of the data enable signal so as to control the time length of a horizontal line in the first display period, and zero clearing is carried out on the value of a counter after the first count value is recorded. Then, a second count value is recorded at the position of the falling edge of the data enable signal so as to indicate a time point of the data enable signal in the first display period from high potential to low potential. After a porch period following the first display period starts, zero clearing is carried out on the value of the counter when the value of the counter reaches the first count value. In a second display period following the porch period, zero clearing is carried out on the value of the counter at the position of the rising edge of the data enable signal and the time length of the horizontal line in the second display period is controlled according to the first count value.
Description
Technical field
The present invention is relevant to a kind of method and correlation timing control circuit that uses single data enable signal to control time sequence of display device, refers to especially a kind ofly use single data enable signal to control method and correlation timing control circuit that display hides from view the cycle sequential.
Background technology
Display system can be come picture frame in the receiving video signals by transmission channel, pass through signal Processing again after, can on screen, show still image or dynamic video.Display system is generally followed (the Video Electronics Standards Association of VESA, VESA) broad sense that is proposed is formula (Generalized Timing Formula regularly, and can be divided into simulation display system or digital display system GTF), according to the form of view data.
Traditional CRT display (cathode ray tube, CRT) be simulation system, on screen and non-once show the view data of whole display frames, but the characteristic that persists by eye image, column scan will be pursued after the picture signal segmentation again, that is after scanning the other end from a horizontal end, move to next bar horizontal line again and begin to scan next time.In the sequential control of CRT display, the signal packet of a picture contains horizontal picture signal and vertical picture signal.Horizontal picture signal comprises every horizontal view data, rising edge signal (front porch), horizontal-drive signal (horizontalsynchronization) and back along signal (back porch).Any data are not transmitted along signal in forward position and back, but are used for allowing cathode-ray tube (CRT) have the enough time to move to the starting point of scanning, and horizontal-drive signal then is used for notifying cathode-ray tube (CRT) when to begin scanning.In like manner, vertical picture signal comprises rising edge signal, vertical synchronizing signal (vertical synchronization) and back along signal, and its function is identical with horizontal picture signal.
Liquid crystal indicator (liquid crystal display, LCD) be digital display circuit, because have low radiation, volume is little and advantage such as low power consuming, therefore replace traditional cathode-ray tube display gradually, be widely used in mobile computer, personal digital assistant (personal digital assistant, PDA), flat-surface television, or on the information products such as mobile phone.In liquid crystal indicator, gate drivers (gatedriver) sends a signal to the sweep trace on the display panel, with the switch of each pixel on the controlling level line.Source electrode driver (source driver) is the data line of transmitted image data (as the red, green, blue signal) to the display panel then, to drive the liquid crystal molecule of each pixel.LCD there is no the problem existence that cathode-ray tube (CRT) need move owing to differ widely with traditional monitor on the structure in sequential control, replacing is to drive the time of liquid crystal shutter and the time delay of data transmission etc.Generally still can adopt the VESA standard to carry out internal image and handle and timing technology, for example the usage level synchronizing signal is used for defining the initial of every sweep trace, and uses vertical synchronizing signal to be used for defining the initial of each frame.
Please refer to Fig. 1, Fig. 1 is the sequential chart of the sequential control mode of LCD in the prior art.Fig. 1 has shown vertical synchronizing signal Vsync, horizontal-drive signal Hsync, data enable (data enable) signal DE, and pixel data signal PX.In display cycle TD, horizontal-drive signal Hsync, vertical synchronizing signal Vsync and data enable signal DE have noble potential, and can write corresponding pixel respectively this moment with view data; Therefore in the cycle of hiding from view (porch period) TP, data enable signal DE has electronegative potential, does not write view data, can utilize this moment horizontal-drive signal Hsync and vertical synchronizing signal Vsync control between other signal synchronously.
Please refer to Fig. 2, Fig. 2 is the sequential chart of the sequential control mode of another LCD in the prior art.The sequential chart of Fig. 2 has shown data enable signal DE, pixel data signal PX, and count value LC, can be applicable to not have in the cycle of hiding from view the LCD of external horizontal synchronization Hsync and vertical synchronizing signal Vsync.Owing to there is no external horizontal synchronization Hsync and vertical synchronizing signal Vsync in the cycle of hiding from view, this prior art adopts single data enable signal DE to control sequential when hiding from view the cycle, understand the value of zero clearing (clear) thread count (line counter) at the rising edge of data enable signal DE, and the opening entry temporal information, make LCD in the cycle of hiding from view, can carry out other running according to count value.Yet, when leaving when hiding from view period T P and entering display cycle TD once more, if data enable signal DE is offset (Δ t as shown in Figure 1) to some extent, synchronously problem can take place between data enable signal DE and the frame interior border.
Summary of the invention
The invention provides a kind of method of using single data enable signal to control sequential in the display, it is included in the rising edge place of data enable signal in first display cycle, first count value of recording counter to be being controlled at horizontal line in this first display cycle, and after this first count value of record the value of this counter of zero clearing with counting again; The falling edge of this data enable signal in this first display cycle, second count value that writes down this counter is to be indicated in this data enable signal in this first display cycle is transferred to electronegative potential by noble potential time point; Entering all after dates that hides from view of following after this first display cycle, when the value of this counter arrived this first count value, the value of this counter of zero clearing was to count again; And at the rising edge place that follows this data enable signal in this hides from view second display cycle of all after dates, the value of this counter of zero clearing is with counting again, and is controlled at horizontal time span in this second display cycle according to this first count value.
The present invention provides a kind of sequential control circuit that utilizes single data enable signal to control display in addition, it comprises counting assembly, be used in first display cycle, following hiding from view the cycle after this first display cycle, and write down corresponding count value respectively following in this hides from view second display cycle of all after dates, and when receiving reset signal, count again; Pen recorder is used in this first display cycle rising edge place of data enable signal to write down first count value of this counting assembly, and the falling edge of this data enable signal writes down second count value of this counting assembly in this first display cycle; Control device, be used for after this first count value of record, providing this reset signal, providing this reset signal when this value of hiding from view all this counting assemblys of after date arrives this first count value, and the rising edge place of this data enable signal provides this reset signal in this second display cycle when entering; And signal generation device, be used to provide this data enable signal, and this first and this second display cycle in control a horizontal time span according to this first count value.
Description of drawings
Fig. 1 is the sequential chart of the sequential control mode of LCD in the prior art.
Fig. 2 is the sequential chart of the sequential control mode of another LCD in the prior art.
Fig. 3 and Fig. 4 are the sequential chart of the sequential control mode of LCD among the present invention.
[primary clustering symbol description]
Hsync horizontal-drive signal Vsync vertical synchronizing signal
DE data enable signal PX pixel data signal
TD display cycle TP hides from view the cycle
CT control signal LC count value
410～490 steps
Embodiment
Please refer to Fig. 3, Fig. 3 is the sequential chart of the sequential control mode of LCD among the present invention.Fig. 3 has shown data enable signal DE, pixel data signal PX, count value LC, and control signal CT.At the LCD of not having external horizontal synchronization Hsync and vertical synchronizing signal Vsync in the cycle of hiding from view, the present invention adopts single data enable signal DE to come control timing, all can recording time information at the rising edge (rising edge) of data enable signal DE and negative edge (falling edge), with as the timing control signal when the display cycle or the cycle of hiding from view, the method for recording time information of the present invention has detailed introduction in the instructions subsequent content.
During time point T1 in display cycle TD, control a horizontal time span at first at the count value N of the rising edge place of data enable signal DE call wire counter, and according to count value N.Write down behind the count value N zero clearing thread count again, and beginning counting again.
Then, the time point T in display cycle TD
M(T1+M) time, again at the count value M of the falling edge call wire counter of data enable signal DE, count value M representative data enable signal DE transfers the time point of electronegative potential to by noble potential, and count value M can be used to be used as the reference point when producing inner clock signal.For instance, if want input control signal CT, can define the starting point T of control signal CT according to count value M to carry out other and operate hiding from view period T P
M-i(T
M-i) and end point T
M+i(T
M+ j).
Enter hide from view period T P after, when the value of thread count arrived count value N, this moment can the zero clearing thread count and counting again once more, but can't revise count value N during the period.In other words, the present invention keeps the sequential of hiding from view period T P by the count value N that before notes in the rising edge place of data enable signal DE.
LCD is left when time point T2 and is hidden from view period T P, and when entering display cycle TD once more, and this moment can be at the rising edge place zero clearing thread count of the first stroke data enable signal DE New count of laying equal stress on, but can't revise count value N.So, when hiding from view period T P and return general display cycle TD, fail suitable keeping and hide from view under the situation of time of period T P if the skew to some extent of data enable signal DE or external system take place, the present invention still can come control timing with correct count value N.
At last, when (for example time point T3), all can write down new count value N, and control horizontal time span in the follow-up display cycle TD when the rising edge of data enable signal DE in follow-up display cycle TD, occurring according to New count value N.Write down after the N value zero clearing thread count again, and beginning counting again.
Please refer to Fig. 4, the flowchart text of Fig. 4 utilize single data enable signal to control the method for sequential in the LCD among the present invention, comprise the following step:
Step 410: in first display cycle before one hides from view the cycle, in horizontal time span of the count value N of the rising edge place of data enable signal DE call wire counter, the thread count of zero clearing simultaneously is to count again;
Step 420: in first display cycle, transfer the time point of electronegative potential to by noble potential with unlabeled data enable signal DE at the count value M of the falling edge call wire counter of data enable signal DE;
Step 430: hide from view all after dates entering, judge whether the value of thread count has arrived N: if the value of thread count has arrived N, execution in step 440; If the value of thread count is no show N still, execution in step 430;
Step 440: the zero clearing thread count is to count again;
Step 450: provide a control signal clearly according to count value M;
Step 460: leaving in second display cycle of hiding from view all after dates, with counting again, and be controlled at horizontal time span in second display cycle according to first count value at the rising edge place zero clearing thread count of data enable signal DE;
Step 470: in second display cycle, transfer the time point of electronegative potential to by noble potential with unlabeled data enable signal DE at the count value M of the falling edge recording counter of data enable signal DE;
Step 480: in the 3rd display cycle after second display cycle, being controlled at horizontal time span in the 3rd display cycle, the thread count of zero clearing simultaneously is with counting again at the count value N of the rising edge place of data enable signal DE recording counter;
Step 490: in the 3rd display cycle, at the count value M of the falling edge recording counter of data enable signal DE to be indicated in data enable signal DE in the 3rd display cycle is transferred to electronegative potential by noble potential time point; Execution in step 410.
The above only is the preferred embodiments of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. method of using single data enable signal to control sequential in the display, it comprises:
The rising edge place of data enable signal in first display cycle, first count value of recording counter to be being controlled at horizontal time span in this first display cycle, and after this first count value of record the value of this counter of zero clearing with counting again;
The falling edge of this data enable signal in this first display cycle, second count value that writes down this counter is to be indicated in this data enable signal in this first display cycle is transferred to electronegative potential by noble potential time point;
Entering all after dates that hides from view of following after this first display cycle, when the value of this counter arrived this first count value, the value of this counter of zero clearing was to count again; And
At the rising edge place that follows this data enable signal in this hides from view second display cycle of all after dates, the value of this counter of zero clearing is with counting again, and is controlled at horizontal time span in this second display cycle according to this first count value.
2. the method for claim 1, it comprises in addition:
The falling edge of this data enable signal in this second display cycle, the value that writes down this counter is to be indicated in this data enable signal in this second display cycle is transferred to electronegative potential by noble potential time point.
3. method as claimed in claim 2, it comprises in addition:
The rising edge place of this data enable signal in the 3rd display cycle after this second display cycle, the 3rd count value that writes down this counter to be being controlled at horizontal time span in the 3rd display cycle, and after record the 3rd count value the value of this counter of zero clearing with counting again.
4. method as claimed in claim 2, it comprises in addition:
The sequential of control signal when hiding from view the cycle, this is provided according to this second count value.
5. method as claimed in claim 2, wherein the value of record and this counter of zero clearing comprises the value of record and zero clearing thread count.
6. the method for claim 1, it comprises in addition:
Whether the value of judging this counter arrives this first count value.
7. sequential control circuit that utilizes single data enable signal to control display, it comprises:
Counting assembly is used in first display cycle, is following hiding from view the cycle after this first display cycle, and writes down corresponding count value respectively following in this hides from view second display cycle of all after dates, and counts again when receiving reset signal;
Pen recorder is used in this first display cycle rising edge place of data enable signal to write down first count value of this counting assembly, and the falling edge of this data enable signal writes down second count value of this counting assembly in this first display cycle;
Control device, be used for after this first count value of record, providing this reset signal, providing this reset signal when this value of hiding from view all this counting assemblys of after date arrives this first count value, and the rising edge place of this data enable signal provides this reset signal in this second display cycle when entering; And
Signal generation device is used to provide this data enable signal, and this first and this second display cycle in control a horizontal time span according to this first count value.
8. sequential control circuit as claimed in claim 7, wherein this pen recorder also in this second display cycle the falling edge of this data enable signal write down the value of this counter, to be indicated in this data enable signal in this second display cycle is transferred to electronegative potential by noble potential time point.
9. sequential control circuit as claimed in claim 7, wherein:
This pen recorder is the rising edge place of this data enable signal in the 3rd display cycle after this second display cycle also, writes down the 3rd count value of this counter;
This signal generation device is also controlled a horizontal time span according to the 3rd count value in the 3rd display cycle; And
This control device also is used for providing this reset signal after record the 3rd count value.
10. sequential control circuit as claimed in claim 7, wherein this signal generation device also provides the sequential of control signal according to this second count value when this hides from view the cycle.
11. sequential control circuit as claimed in claim 7, wherein this counting assembly comprises thread count.
12. sequential control circuit as claimed in claim 7, it also comprises:
Judgment means is used for judging whether the value of this counter arrives this first count value when this hides from view the cycle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100033926A CN101789222B (en) | 2009-01-22 | 2009-01-22 | Method utilizing data enable signal to control time sequence of display device and time sequence control circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009100033926A CN101789222B (en) | 2009-01-22 | 2009-01-22 | Method utilizing data enable signal to control time sequence of display device and time sequence control circuit |
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| CN101789222A true CN101789222A (en) | 2010-07-28 |
| CN101789222B CN101789222B (en) | 2012-05-23 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103155022A (en) * | 2010-09-17 | 2013-06-12 | 欧姆龙株式会社 | Image data transmission system and electronic device |
| WO2023201731A1 (en) * | 2022-04-22 | 2023-10-26 | 京东方科技集团股份有限公司 | Read timing control method and apparatus, and computer-readable storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6636205B1 (en) * | 2000-04-10 | 2003-10-21 | Infocus Corporation | Method and apparatus for determining a clock tracking frequency in a single vertical sync period |
| JP4668202B2 (en) * | 2004-09-30 | 2011-04-13 | シャープ株式会社 | Timing signal generation circuit, electronic device, display device, image receiving device, and electronic device driving method |
| JP2006171125A (en) * | 2004-12-13 | 2006-06-29 | Nec Lcd Technologies Ltd | Display apparatus and automatic synchronism judgement circuit |
| CN100468492C (en) * | 2007-04-04 | 2009-03-11 | 友达光电股份有限公司 | Method for correcting display data enable signal |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103155022A (en) * | 2010-09-17 | 2013-06-12 | 欧姆龙株式会社 | Image data transmission system and electronic device |
| WO2023201731A1 (en) * | 2022-04-22 | 2023-10-26 | 京东方科技集团股份有限公司 | Read timing control method and apparatus, and computer-readable storage medium |
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| CN101789222B (en) | 2012-05-23 |
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