CN204807860U - Liquid crystal display panel's testing arrangement - Google Patents
Liquid crystal display panel's testing arrangement Download PDFInfo
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- CN204807860U CN204807860U CN201520539447.6U CN201520539447U CN204807860U CN 204807860 U CN204807860 U CN 204807860U CN 201520539447 U CN201520539447 U CN 201520539447U CN 204807860 U CN204807860 U CN 204807860U
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Abstract
The utility model provides a liquid crystal display panel's testing arrangement, it is including being used for the decoder to the image signal decode of headend equipment output, the first processor that handles is carried out to data after being used for decoding to the decoder, and first processor is connected with the decoder, a memory for saving first data, the second processor of the first data of the 2nd data reading memory after being arranged in handling according to first processor, second processor is connected with first processor and memory, and be used for the encoder of output test signal to the liquid crystal display panel, the encoder is connected with the liquid crystal display panel, first processor and second processor. Wherein, first data include the liquid crystal display panel's driver chip's initialization configuration parameter, and the second data include driver chip's chronogenesis parameter. The utility model discloses a liquid crystal display panel's testing arrangement can ensure the liquid crystal display panel's normal test, and need not to burn again record procedure, convenient operation, with low costs.
Description
Technical field
The utility model relates to technical field of measurement and test, particularly a kind of proving installation of display panels.
Background technology
Liquid crystal indicator (LiquidCrystalDisplay, LCD) possesses the plurality of advantages such as frivolous, energy-conservation, radiationless, has therefore replaced traditional cathode-ray tube (CRT) (CRT) display gradually.Current liquid crystal indicator is widely used in the electronic equipments such as HD digital TV, desk-top computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera.
For the test of liquid crystal indicator, in the signal input interface standardization of large-sized liquid crystal indicator, it can mate with the output interface of front-end equipment such as optic test board, to receive the low-voltage differential signal (LowVoltageDifferentialSignaling, LVDS) that optic test board exports.But, for mobile Industry Processor Interface (MobileIndustryProcessorInterface, MIPI) small size liquid crystal indicator, when liquid crystal indicator receives the LVDS signal of optic test board output, must be further processed LVDS signal, make itself and MIPI Interface Matching, and then obtain the LVDS signal of optic test board output.In addition, undersized liquid crystal indicator is when testing, parameter configuration must be carried out to the driving chip of liquid crystal indicator (DriverIC), that is, liquid crystal indicator needs the configuration parameter receiving DriverIC, being configured by DriverIC deals with problems arising from an accident can receive front-end equipment export picture signal.
Fig. 1 is the proving installation module diagram of prior art small-medium size liquid crystal indicator.As shown in Figure 1, this proving installation comprises LVDS demoder 12, field programmable gate array (Field-ProgrammableGateArray, FPGA) 14, single-chip microcomputer (MCU) 16 and MIPI scrambler 18.Wherein, in single-chip microcomputer 16, burning has the configuration parameter of the DriverIC of liquid crystal indicator, this configuration parameter comprises initial configuration parameter and time sequence parameter, configuration parameter is sent to MIPI scrambler 18 by single-chip microcomputer 16, encoded to be converted to MIPI signal to it by MIPI scrambler 18. and then the MIPI signal after conversion is sent to the liquid crystal indicator of rear end, parameter configuration is carried out to the DriverIC of liquid crystal indicator, liquid crystal indicator receives the picture signal that optic test board 10 exports again, and then realizes the test of liquid crystal indicator.
But, because the time sequence parameter in the DriverIC of liquid crystal indicator is determined by the program be burnt in single-chip microcomputer 16, and in optic test board 10 time sequence parameter of picture signal from optic test board 10, when the time sequence parameter of the picture signal that optic test board 10 is arranged is inconsistent with the program time sequence parameter be burnt in single-chip microcomputer, liquid crystal indicator will be caused to test normally, even can not light display panels.In addition, the initial configuration parameter of the DriverIC of liquid crystal indicator is also determined by the program be burnt in single-chip microcomputer 16, when needing the liquid crystal indicator testing different machine or different size, need again initial configuration parameter to be burnt in single-chip microcomputer 16, inefficiency, complicated operation, is not easy to the test of the liquid crystal indicator of different machine, and the increase of burning number of times may cause the damage of single-chip microcomputer 16, adds cost.
Therefore, be necessary to provide the technical scheme of improvement to overcome the above technical matters existed in prior art.
Utility model content
In view of above problem, the utility model provides a kind of proving installation of display panels, and it can guarantee the proper testing of display panels, and easy to operate, cost is low.
The utility model provides a kind of proving installation of display panels, and described proving installation comprises the demoder that the picture signal for exporting front-end equipment is decoded; For the first processor processed the data after described decoders decode, described first processor is connected with described demoder; For storing the storer of the first data; For the second processor of the first data in storer according to the second digital independent after described first processor process, described second processor is connected with described first processor and described storer; And for exporting the scrambler of test signal to display panels; Described scrambler is connected with display panels, described first processor and described second processor, wherein, described first data comprise the initial configuration parameter of the driving chip of display panels, and described second data comprise the time sequence parameter of described driving chip.
Further, the first data in LCD board test device comprise the initial configuration parameter of the driving chip of at least one display panels.
Further, the second data in LCD board test device also comprise pixel clock signal, line synchronizing signal, field sync signal, data enable signal and picture element signal.
Further, the demoder in LCD board test device is low-voltage differential signal demoder.
Further, the scrambler in LCD board test device is mobile Industry Processor Interface signal coder.
Further, the first processor in LCD board test device is field programmable gate array.
Further, the second processor in LCD board test device is advanced reduced instruction set computer microprocessor.
Further, the communication mode between the second processor in LCD board test device and described scrambler, described storer is serial communication.
The proving installation of display panels of the present utility model utilizes first processor to be processed by the signal that front-end equipment exports, again the second data comprising the time sequence parameter of display panels driving chip after process are sent to the second processor, make the time sequence parameter of driving chip consistent with the parameter of front-end equipment, and the second processor is according to the initial configuration parameter of the driving chip stored in this second digital independent storer, and then again these second data and initial configuration parameter are encoded, to export display panels to, ensure that display panels can normally be tested.In addition, initiation parameter is stored in memory, when Initialize installation is carried out to the driving chip of the display panels of different machine, only need read the data stored in storer, without the need to re-starting the burning of drive IC program, easy to operate and cost is low.
Accompanying drawing explanation
Fig. 1 is the proving installation module diagram of prior art small-medium size liquid crystal indicator.
The proving installation module diagram of the display panels that Fig. 2 provides for the utility model one embodiment.
The time diagram of the time sequence parameter of the proving installation of the display panels that Fig. 3 provides for an embodiment of the present utility model.
Embodiment
For further setting forth the utility model for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to according to its embodiment of proving installation of the display panels that the utility model proposes, method, step, structure, feature and effect, be described in detail as follows.
About aforementioned and other technology contents, feature and effect of the present utility model, can clearly present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the utility model for the technological means reaching predetermined object and take and effect be able to more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the utility model.
Please refer to Fig. 2, proving installation 100 module diagram of the display panels that Fig. 2 provides for the utility model one embodiment.As shown in Figure 2, the proving installation 100 of display panels of the present utility model comprises demoder 20, first processor 22, second processor 24, storer 26 and scrambler 28.Demoder 20 is connected with first processor 22, and first processor 22 is connected with the second processor 24 and scrambler 28, and the second processor 24 is connected with storer 26 and scrambler 28, and scrambler 28 is connected with display panels (not identifying in figure).
Wherein, the picture signal that demoder 20 receiving front-end equipment such as optic test board 10 exports, this picture signal is LVDS signal, optic test board 10 exports this LVDS signal in the mode of Serial output, demoder 20 receives this LVDS signal, and it is decoded, so that LVDS signal is converted to transistor-transistor logic (Transistor-TransistorLogic, TTL) level signal.Wherein, decoded data comprise the red (Red of image, R) color pixel information, green (Green, G) color pixel information, blue (Blue, B) color pixel information, and comprise the line synchronizing signal (HorizontalSynchronizingSignal of image, HSYNC or HS), field sync signal (VerticalSynchronizingSignal, VSYNC or VS), pixel clock (PixelClock, PCLK) signal and data enable (DataEnable, DE) signal, owing to adopting serial communication mode to communicate between optic test board 10 with demoder 20, therefore the R that receives of demoder 20, G, B Pixel Information is respectively strange passage R, G, B Pixel Information and even passage R, G, B Pixel Information.
Decoded data are sent to first processor 22 in the mode of parallel communications by demoder 20, the data after first processor 22 receipt decoding, and integrate decoded data, detect to obtain the second data.Further, R, G, B Pixel Information of strange passage and R, G, B Pixel Information of even passage are integrated into complete R, G, B Pixel Information of an oem character set by first processor 22, and using the PCLK signal received as clock reference, respectively HS signal, VS signal and DE signal are sampled, to detect the time sequence parameter of the driving chip of display panels.In the present embodiment, these second data comprise above-mentioned time sequence parameter.
Time sequence parameter is sent to the second processor 24 by first processor 22, this time sequence parameter that second processor 24 sends according to first processor 22 reads the first data be stored in storer 26, and these first data and this time sequence parameter are sent to scrambler 28, these first data and this time sequence parameter are encoded by scrambler 28, so that the MIPI signal data after coding is sent to display panels.In addition, what scrambler 28 also received that first processor 22 sends is R, G, B Pixel Information of the picture signal of TTL form, HS signal, VS signal and DE signal, and those signals are sent to display panels.It should be noted that, in the present embodiment, the first data comprise the initial configuration parameter of the driving chip of display panels.The initial configuration parameter that display panels sends according to scrambler 28 carries out initialization to driving chip, and shows the picture signal that scrambler 28 sends according to time sequence parameter, to realize the test of display panels.
In better embodiment of the present utility model, the first data of LCD board test device comprise the initial configuration parameter of the driving chip of at least one display panels.
In an embodiment of the present utility model, the first data are a kind of initial configuration parameter of driving chip of display panels, and that is, the first data are the initial configuration parameter of the driving chip of the set a kind of display panels of resolution.When only storing a kind of initial configuration parameter of driving chip of display panels in storer 26, to carry out the Initialize installation of the driving chip of the liquid crystal display of different machine, only storer 26 need be changed, and without the need to burning program again, reduce the loss brought because frequent burning program causes processor to damage, cost is low.
In another embodiment of the present utility model, the first data are the initial configuration parameter of the driving chip of plurality of liquid crystals display panel.That is, the initial configuration parameter of the driving chip of different display panels is included in the first data.When carrying out Initialize installation to the driving chip of different display panels, second processor 24 need read the initial configuration parameter of the driving chip of the different display panels stored in storer 26, without the need to changing storer 26, easy to operate.
In an embodiment of the present utility model, the second data also comprise PCLK signal, HS signal, VS signal, DE signal and R, G, B picture element signal.
In an embodiment of the present utility model, demoder 20 is LVDS decoding signals.
In an embodiment of the present utility model, scrambler 28 is MIPI signal coder.
In an embodiment of the present utility model, first processor 22 is FPGA.
In an embodiment of the present utility model, the second processor 24 is advanced reduced instruction set computer (AdvancedRISCMachine, ARM) microprocessor.
In an embodiment of the present utility model, the communication mode between the second processor 24 in LCD board test device and scrambler 28, storer 26 is serial communication.
The above-mentioned proving installation 100 for display panels has done detailed description, and present composition graphs 3 illustrates the time sequence parameter how first processor 22 detects the driving chip of display panels.Please refer to Fig. 3, the time diagram of the time sequence parameter of the proving installation 100 of the display panels that Fig. 3 provides for an embodiment of the present utility model.Suppose, the picture signal refreshing frequency that optic test board 10 exports is 60HZ, i.e. switching 60 frame picture per second, as shown in Figure 3, the starting point of every frame is the one-period of VS signal to the starting point of next frame, the periodic packets of each VS signal is containing field sync signal width (VerticalSynchronizingSignalWide, VSW), blank (VerticalForwardPorch before field, VFP) blank (VerticalBlackPorch behind region, field, VBP) region and field effectively (VerticalACTIVE, VACTIVE) region.Comprise n HS signal period in each VACTIVE region, n equals the line number of resolution, and that is, when the resolution of liquid crystal display is 1024*768, the number of n is 768.Line synchronizing signal width (HorizontalSynchronizingSignalWide is comprised in the cycle of each HS signal, HSW), blank (HorizontalForwardPorch before row, HFP) blank (HorizontalBlackPorch after region, row, and row effectively (HorizontalACTIVE, HACTIVE) region HBP).In addition, each row HS signal period in VACTIVE region corresponding DE signal, only have when DE signal is effective, the grid of the current line of display panels is opened, each PCLK transmits data, completes the transmission of data line within the DE signal effective time.
Particularly, the high level of the signals such as above-mentioned VSW, VFP, VBF, VACTIVE, HSW, HFP, HBP, HACTIVE that first processor 22 detects is 1, and low level is 0.First processor 22 is using the PCLK signal that the receives reference clock as VS signal, HS signal and DE signal, to detect the parameters such as VSW, VFP, VBP, VACTIVE, HSW, HFP, HBP, HACTIVE, and the parameters such as VSW, VFP, VBP, VACTIVE, HSW, HFP, HBP, HACTIVE are stored in register therein.
The rising edge that first processor 22 is detecting each HS signal starts PCLK signal-count, and terminates PCLK signal-count to during next HS rising edge, and the PCLK number of signals of gained is as the cycle of HS signal.In the one-period of HS signal, start counting when first processor 22 receives HS signal rising edge, to terminating counting during HS signal negative edge, the rising edge number of the PCLK signal counted to get is parameter HSW; First processor 22 detect that first time receives between the rising edge of DE signal and the negative edge of the HS signal nearest apart from this rising edge PCLK number of signals, and using this PCLK number of signals as parameter HBP; First processor 22 detects the PCLK number of signals received between the negative edge of DE signal and the rising edge of the HS signal nearest apart from this negative edge, and using this PCLK number of signals as parameter HFP; First processor 22 detects the PCLK number of signals between the rising edge of a DE signal and negative edge, and using this PCLK number of signals as parameter HACTIVE.
Further, first processor 22 counts from the rising edge of the VS signal received, and to terminating counting during the negative edge of this VS signal, the HS number of signals comprised therebetween is as parameter VSW; First processor 22 detects the HS number of signals between the rising edge of the negative edge of the nearest VS signal of the rising edge of DE signal that first time receives HS signal nearest before the rising edge of this DE signal, and using this number of signals as parameter VBP; The rising edge again that first processor 22 detects VS signal to the last DE signal above negative edge between HS number of signals as parameter VFP; Within the cycle of a VS signal, counting is started during HS signal rising edge before first processor 22 detects the rising edge of first DE signal, terminate counting during the rising edge of the HS signal after the negative edge of last DE signal, the HS number of signals between this is as parameter VACTIVE.
In sum, the proving installation 100 of display panels is in test process, the sequential that the time sequence parameter of the driving chip of display panels detects by first processor 22 picture signal that front-end equipment sends obtains, if the sequential of the picture signal of change front-end equipment, then synchronously can obtain the time sequence parameter of the driving chip of display panels, and then make the time sequence parameter of the driving chip of display panels consistent with the signal sequence of front-end equipment.
The proving installation 100 of display panels of the present utility model utilizes first processor 22 to be processed by the signal that front-end equipment exports, again the second data comprising the time sequence parameter of display panels driving chip after process are sent to the second processor 24, make the time sequence parameter of driving chip consistent with the parameter of front-end equipment, and the second processor 22 is according to the initial configuration parameter of the driving chip stored in this second digital independent storer 26, and then again these second data and initial configuration parameter are encoded, to export display panels to, ensure that display panels can normally be tested.In addition, initiation parameter is stored in storer 26, when Initialize installation is carried out to the driving chip of the display panels of different machine, only need reads 26 data stored in storer, without the need to re-starting the burning of program, easy to operate and cost is low.
The above, it is only preferred embodiment of the present utility model, not any pro forma restriction is done to the utility model, although the utility model discloses as above with preferred embodiment, but and be not used to limit the utility model, any those skilled in the art, do not departing within the scope of technical solutions of the utility model, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solutions of the utility model content, according to any simple modification that technical spirit of the present utility model is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solutions of the utility model.
Claims (8)
1. a proving installation for display panels, is characterized in that, described proving installation comprises:
For the demoder that the picture signal exported front-end equipment is decoded;
For the data after described decoders decode are processed first processor, described first processor is connected with described demoder;
For storing the storer of the first data;
For the second processor of the first data in storer according to the second digital independent after described first processor process, described second processor is connected with described first processor and described storer; And
For exporting the scrambler of test signal to display panels; Described scrambler is connected with display panels, described first processor and described second processor;
Wherein, described first data comprise the initial configuration parameter of the driving chip of display panels, and described second data comprise the time sequence parameter of described driving chip.
2. the proving installation of display panels according to claim 1, is characterized in that, described first data comprise the initial configuration parameter of the driving chip of at least one display panels.
3. the proving installation of display panels according to claim 1, is characterized in that, described second data also comprise pixel clock signal, line synchronizing signal, field sync signal, data enable signal and picture element signal.
4. the proving installation of display panels according to claim 1, is characterized in that, described demoder is low-voltage differential signal demoder.
5. the proving installation of display panels according to claim 1, is characterized in that, described scrambler is mobile Industry Processor Interface signal coder.
6. the proving installation of display panels according to claim 1, is characterized in that, described first processor is field programmable gate array.
7. the proving installation of display panels according to claim 1, is characterized in that, described second processor is advanced reduced instruction set computer microprocessor.
8. the proving installation of display panels according to claim 1, is characterized in that, the communication mode between described second processor and described scrambler, described storer is serial communication.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448220A (en) * | 2015-12-17 | 2016-03-30 | 昆山龙腾光电有限公司 | Driving signal configuration method and driving signal configuration device |
| CN105704543A (en) * | 2016-01-26 | 2016-06-22 | 武汉精测电子技术股份有限公司 | A portable picture signal source and a control method thereof |
| CN106571113A (en) * | 2016-10-20 | 2017-04-19 | 昆山龙腾光电有限公司 | Test device and test method for display module |
| CN110648617A (en) * | 2019-09-29 | 2020-01-03 | 成都天马微电子有限公司 | Display device, detection method and display system |
-
2015
- 2015-07-23 CN CN201520539447.6U patent/CN204807860U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448220A (en) * | 2015-12-17 | 2016-03-30 | 昆山龙腾光电有限公司 | Driving signal configuration method and driving signal configuration device |
| CN105704543A (en) * | 2016-01-26 | 2016-06-22 | 武汉精测电子技术股份有限公司 | A portable picture signal source and a control method thereof |
| CN106571113A (en) * | 2016-10-20 | 2017-04-19 | 昆山龙腾光电有限公司 | Test device and test method for display module |
| CN110648617A (en) * | 2019-09-29 | 2020-01-03 | 成都天马微电子有限公司 | Display device, detection method and display system |
| CN110648617B (en) * | 2019-09-29 | 2023-02-28 | 成都天马微电子有限公司 | Display device, detection method and display system |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301 No.1 Longteng Road, Kunshan City, Suzhou City, Jiangsu Province Patentee before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |