CN101783859B - Storage method of image data - Google Patents

Abstract

The invention discloses a storage method of image data, which is characterized in that a storage array block is divided into eight sub-blocks; when the image data is written into the storage array block by a storage control block, a point-by-point storage method is used for compact matrix, and a CSR format storage method is used for sparse matrix; and reference drawing data and template drawing data are stored into the eight sub-blocks according to four different storage modes Mem Mode: a single-element compact matrix 00, a double-element compact matrix 01, a single-element sparse matrix 10 and a double-element sparse matrix 11. The storage control block adopts the same control for reference drawing and template drawing of the storage array block, so that parallel access of the image data of the reference drawing and the template drawing can be realized, and intelligent access of the image data aiming at the different image data characteristics can be realized at the same time.

Description

A kind of storage means of view data

Technical field

The present invention relates to the image data recording method in a kind of image processing equipment.

Background technology

Images match is the basic problem in the image processing, and it is that two width of cloth images (can be described as reference diagram and template figure) are carried out computing according to certain algorithm, according to operation result and criterion, gets corresponding results and conclusion.Wherein, view data is to store and computing in the mode of matrix.This matrix has two kinds: a kind of is that all data are the matrix of non-zero, is called tight matrix; A kind of is that a great number of elements is zero matrix, is called sparse matrix.Matrix is big more, needs the view data of storage just many more, and needed memory space is just big more.In order to satisfy the needs of nonidentity operation, effectively save memory space, improve the storage access performance, in image processing equipment, need a kind of storage means of new view data.

Traditional image data recording method is that pointwise is stored.This method can be used for storing tight matrix.For sparse matrix, adopt the pointwise storage, both caused the significant wastage of memory space, cause a large amount of invalid operation of arithmetic element again, arithmetic speed occurs and descend, memory capacity becomes big situation.Therefore, this storage means can not fine solution to the storage of view data, have certain shortcoming.

Summary of the invention

Can not be applicable at existing image data recording method and the requirement of sparse matrix storage the invention provides a kind of image data recording method that adapts to tight matrix and sparse matrix.

For reaching above purpose, the present invention takes following technical scheme to be achieved:

A kind of storage means of view data, it is characterized in that, divide the storage array piece into eight sub-pieces, wherein zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2 memory capacity are identical to be respectively zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2, the 3rd sub-piece Block3, the 4th sub-piece Block4, the 5th sub-piece Block5, the 6th sub-piece Block6, the 7th sub-piece Block7., and bigger 1 times than the memory capacity of the 3rd sub-piece Block3; The size of the 4th sub-piece Block4 to the seven sub-piece Block7 memory capacity is 1/4 of the 3rd sub-piece Block3 memory capacity.

When storage controll block writes the storage of storage array piece with view data, tight matrix is adopted the method for pointwise storage, sparse matrix is adopted the storage means of CSR form, with reference map data and template diagram data according to four kinds of different memory module MemMOde: the tight matrix 00 of single element, the tight matrix 01 of dual element, single element sparse matrix 10 and dual element sparse matrix 11 store in eight sub-pieces, wherein single element is the real part of data, dual element is the real part+imaginary part of data, and the data allocations mode is as follows:

When memory module MemMode=00, Block0～Block3 stored reference diagram data, Block4 and Block5 storing template diagram data, the every capable nonzero element number of Block6 stored reference figure, the every capable nonzero element number of Block7 storing template figure.

When memory module MemMode=01, Block0 and Block2 stored reference diagram data real part, Block1 and Block3 stored reference diagram data imaginary part, Block4 storing template diagram data real part, Block5 storing template diagram data imaginary part, the every capable nonzero element number of Block6 stored reference figure, the every capable nonzero element number of Block7 storing template figure.

When memory module MemMode=10, Block0 and Block1 stored reference figure nonzero element, Block2 and Block3 stored reference figure nonzero element row number, Block4 storing template figure nonzero element, the every capable nonzero element number of Block5 stored reference figure, Block6 storing template figure nonzero element row number, the every capable nonzero element number of Block7 storing template figure.

When memory module MemMode=11, Block0 stored reference figure nonzero element real part, Block1 stored reference figure nonzero element imaginary part, Block2 stored reference figure nonzero element row number, the every capable nonzero element number of Block3 stored reference figure, Block4 storing template figure nonzero element real part, Block5 storing template figure nonzero element imaginary part, Block6 storing template figure nonzero element row number, the every capable nonzero element number of Block7 storing template figure.

The controlled step of image data storage is:

(1) when beginning storage pulse StoreStart is effective, produce storage array data address MemQAddr and data rows address MemEcolAddr by data initial address AddrQStart, produce every capable nonzero element number address MemElsAddr by every capable nonzero element number initial address AddrEStart, produce the data rows initial value simultaneously;

(2) write fashionablely when view data,, only data rows number is added up if data are zero; If data are nonzero element, will produce storage array data write signal MemQWe, these data and row number write the sub-piece of storage array respective stored according to above data allocations; Write finish after data address MemQAddr, data rows address MemEcolAddr, every capable nonzero element number M emElsDin and data rows number add 1; After a row element writes end, produce every capable nonzero element number write signal MemElsWe, current line nonzero element number is write the sub-piece of the corresponding storage of storage array piece;

(3) the next line data write repeating step (2), until depositing total data in;

When (4) view data is read, storage controll block generates read signal and the address to storage array, because storage array is that flowing water is read, when beginning load pulses LoadStart is effective, produce storage array data address MemQAddr and data rows address MemEcolAddr by data initial address AddrQStart, produce the every capable nonzero element number address MemElsAddr of storage array by every capable nonzero element number initial address AddrEStart, produce storage array data reading signal MemQRd simultaneously, data rows read signal MemEcolRd and every capable nonzero element number read signal MemElsRd, according to described MemQAddr, MemEcolAddr and MemElsAddr address signal, the view data that deposits in is read into the output buffers of storing controll block in advance, as data reading signal ImgQRd, data rows read signal EcolRd, sense data from the output buffers of storage controll block again after every capable nonzero element number read signal ElsRd arrives, data rows number and every capable nonzero element number.

In the such scheme, in described eight sub-pieces, zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2 memory capacity are identical, and bigger 1 times than the memory capacity of the 3rd sub-piece Block3; The size of the 4th sub-piece Block4 to the seven sub-piece Block7 memory capacity is 1/4 of the 3rd sub-piece Block3 memory capacity.

When storage controll block writes the storage array piece with view data, for the tight matrix of dual element, data real part MemQ0Din and data imaginary part MemQ1Din are written in parallel to, for single element or dual element sparse matrix, data real part MemQ0Din, data imaginary part MemQ1Din and row MemEcolDin thereof are written in parallel to; When data are read from the storage array piece, for the tight matrix of dual element, data real part MemQ0Din and data imaginary part MemQ1Din parallel read-out, every capable nonzero element number M emElsDin reads separately, for single element or dual element sparse matrix, data real part MemQ0Din and data imaginary part MemQ1Din parallel read-out, data rows MemEcolDin and every capable nonzero element number M emElsDin read separately.

The present invention combines with the storage array piece by storage controll block, can realize four kinds of memory modules.Storage controll block adopts identical control to storage array piece reference diagram with template figure, has realized the concurrent access of reference diagram and template figure view data, has realized the intellectual access at the view data of different images data characteristics simultaneously.The present invention is applicable to data storage cell part in the image processing equipment, can effectively improve computer data memory access performance in the Defense Weapon System, during handling, the spaceborne Multi-source Information Fusion of effectively satisfied bullet, high-speed parallel treatment technology and high speed information, therefore have a wide range of applications to the demand of mass data memory access.

Description of drawings

The present invention is described in further detail below in conjunction with the drawings and the specific embodiments.

Fig. 1 is the storage array piece of realizing image data storage of the present invention and the structural representation of storing controll block.Among the figure:

Following symbol is the signal from external control unit input storage controll block:

The MemMOde-memory module; ImgDimX-image dimension; StoreStart-begins storage pulse; LoadStart-begins load pulses; AddrQStart-data initial address; The every capable nonzero element number initial address of AddrEStart-; The ImgQWe-view data is write; The ImgQRd-view data is read; The input of QDin-view data; The EcolRd-data rows number is read; The every capable nonzero element number of ElsRd-is read.

Following symbol is the signal of storage array piece to the output of storage controll block:

The output of Data-storage array blocks of data.

Following symbol is the signal of storage controll block to the output of storage array piece, also is the input signal of storage array piece:

MemQWe-storage array view data is write; MemQRd-storage array view data is read; MemQAddr-storage array view data address; The input of MemQ0Din-storage array view data real part; The input of MemQ1Din-storage array view data imaginary part; MemEcolRd-storage array view data row number are read; MemEcolAddr-storage array image column address; Number input of MemEcolDin-storage array view data row; The every capable nonzero element number of MemElsWe-storage array view data is write; The every capable nonzero element number of MemElsRd-storage array view data is read; The every capable nonzero element number of MemElsAddr-storage array view data address; The every capable nonzero element number input of MemElsDin-storage array view data.

Following symbol/numeral is the signal of storage controll block to outside arithmetic element output:

The output of 800-storage controll block view data real part; The output of 801-storage controll block view data imaginary part; Number output of 802-storage controll block view data row; The every capable nonzero element number output of 803-storage controll block view data.

Embodiment

As shown in Figure 1, the view data of storage comprises reference map data and template diagram data in storage array is fast.In the storage array piece,, adopt CSR form (row format storage method) to store to the storage of sparse matrix view data to the method for tight matrix image The data pointwise storage.Its basic thought is that nonzero elements all in the image data matrix is extracted, according to from top to bottom, from left to right order lines up a sequence.The CSR form has 4 characteristic vectors.One of them characteristic vector is the location index of every first nonzero element of row, mainly is the random access of being convenient to any row in the matrix.Because CSR is a sequential access to view data, therefore can preserve this characteristic vector.Like this, the inventive method only need be stored three characteristic vectors: nonzero element, nonzero element row number and every capable nonzero element number.

The present invention divides the storage array piece into eight sub-pieces, is respectively zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2, the 3rd sub-piece Block3, the 4th sub-piece Block4, the 5th sub-piece Block5, the 6th sub-piece Block6, the 7th sub-piece Block7.Wherein zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2 memory capacity are identical, and bigger 1 times than the memory capacity of the 3rd sub-piece Block3; The size of the 4th sub-piece Block4 to the seven sub-piece Block7 memory capacity is 1/4 of the 3rd sub-piece Block3 memory capacity.

During storage, with reference map data and template diagram data according to four kinds of different memory module MemMode: tight matrix unit element 00, tight matrix dual element 01, sparse matrix single element 10 and sparse matrix dual element 11 store in eight sub-pieces, and data allocations is as shown in table 1.Wherein, single element is the data real part, and dual element is a data reality+imaginary part.

Table 1 storage array blocks of data allocation table

In the table 1, when memory module MemMode=00, Block0～Block3 stored reference diagram data, Block4 and Block5 storing template diagram data, the every capable nonzero element number of Block6 stored reference figure, the every capable nonzero element number of Block7 storing template figure.

When memory module MemMode=01, Block0 and Block2 stored reference diagram data real part, Block1 and Block3 stored reference diagram data imaginary part, Block4 storing template diagram data real part, Block5 storing template diagram data imaginary part, the every capable nonzero element number of Block6 stored reference figure, the every capable nonzero element number of Block7 storing template figure.

When memory module MemMode=10, Block0 and Block1 stored reference figure nonzero element, Block2 and Block3 stored reference figure nonzero element row number, Block4 storing template figure nonzero element, the every capable nonzero element number of Block5 stored reference figure, Block6 storing template figure nonzero element row number, the every capable nonzero element number of Block7 storing template figure.

When memory module MemMode=11, Block0 stored reference figure nonzero element real part, Block1 stored reference figure nonzero element imaginary part, Block2 stored reference figure nonzero element row number, the every capable nonzero element number of Block3 stored reference figure, Block4 storing template figure nonzero element real part, Block5 storing template figure nonzero element imaginary part, Block6 storing template figure nonzero element row number, the every capable nonzero element number of Block7 storing template figure.

In practical engineering application, according to the target image storage demand, reference diagram matrix maximum 512 * 512 (256K); Template figure matrix maximum 128 * 128 (16K).Required area of composite chip and adaptive consideration, the storage array size is set at 256K * 12bits, the employing amount of capacity is that the memory cell of 4k * 12bits (the maximum storage degree of depth of VeriSilicon company memory compilation tool support is 4K) is formed totally 64.Memory capacity size under four kinds of memory modules is seen Fig. 1, and wherein zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2 size are 16*4K (16 4k * 12bits memory cell); The size of the 3rd sub-piece Block3 is 8*4K (8 4k * 12bits memory cell); The size of the 4th sub-piece Block4 to the seven sub-piece Block7 is 2*4K (2 4k * 12bits memory cell).

In storage controll block, the view data width that the external control unit writes is 2 times (24) of reading in the view data width of storage array piece, and under the single element pattern, view data is hanged down 12 view data as the storage array piece; Under the dual element pattern, view data high 12 as storage array piece view data imaginary part, low 12 as storage array piece view data real part.

Storage controll block writes view data before the storage array, need provide memory module MemMode, image dimension ImgDimX; When storage controll block writes the storage array piece with view data, for the tight matrix of dual element, data real part MemQ1Din and data imaginary part MemQ1Din are written in parallel to, for single element or dual element sparse matrix, data real part MemQ0Din, data imaginary part MemQ1Din and row MemEcolDin thereof are written in parallel to; When view data is read from the storage array piece, for the tight matrix of dual element, data real part MemQ0Din, data imaginary part MemQ1Din parallel read-out, for single element or dual element sparse matrix, data real part MemQ0Din and data imaginary part MemQ1Din parallel read-out, data rows MemEcolDin and every capable nonzero element number M emElsDin read separately.During image data storage, tight matrix adopts the method for pointwise storage, view data sequential storage; For sparse matrix, the storing step that view data is concrete is:

(1) when beginning storage pulse StortStart is effective, produce storage array data address MemQAddr and data rows address MemEcolAddr by data initial address AddrQStart, produce the every capable nonzero element number address MemElsAddr of storage array (initial address is set to the 0th memory cell) by every capable nonzero element number initial address AddrEStart, produce data rows initial value (initial value is 0) simultaneously.

(2) write fashionablely when view data,, only data rows number is added up if data are zero; If view data is a nonzero element, will produce storage array data write signal MemQWe, these data and row number write the sub-piece of storage array respective stored according to the data distribution list of table 1; Write finish after data address MemQAddr, data rows address MemEcolAddr, every capable nonzero element number M emElsDin and data rows number add 1; After a row element writes end, produce every capable nonzero element write signal MemElsWe, current nonzero element number is write the sub-piece of the corresponding storage of storage array piece.

(3) the next line data write repeating step (2), until depositing total data in.

When (4) view data is read, storage controll block generates read signal and the address to storage array, because storage array is that flowing water is read, when beginning load pulses LoadStart is effective, produce storage array data address MemQAddr and data rows address MemEcolAddr by data initial address AddrQStart, produce the every capable nonzero element number address MemElsAddr of storage array by every capable nonzero element number initial address AddrEStart, produce storage array data reading signal MemQRd simultaneously, data rows read signal MemEcolRd and every capable nonzero element number read signal MemElsRd, according to described MemQAddr, MemEcolAddr and MemElsAddr address signal, the view data that deposits in is read into the output buffers of storing controll block in advance, as view data read signal ImgQRd, view data row read signal EcolRd, sense data real part from the output buffers of storage controll block again after every capable nonzero element number read signal ElsRd arrives, the data imaginary part, data rows number and every capable nonzero element number.

Embodiment 1

Be that example further specifies method of the present invention with the memory module in the table 1 10 below:

If the view data that the external control unit need be stored is reference diagram view data QDin, the A matrix of memory module MemMode=10, image dimension ImgDimx=6*6:

$A=\left(\begin{array}{cccccc}0& 5& 0& 0& 0& 2\\ 1& 0& 0& 0& 0& 0\\ 0& 2& 0& 0& 0& 1\\ 3& 0& 0& 0& 0& 0\\ 1& 0& 0& 3& 0& 0\\ 0& 0& 0& 0& 0& 3\end{array}\right)$

Data writing process:

When memory module MemMode=10, find out that by table 1 the storage array blocks of data is assigned as: block0 and block1 stored reference figure nonzero element; Block2 and block3 stored reference figure nonzero element row number; The every capable nonzero element number of block5 stored reference figure.Data and data rows number are written in parallel to.

1. in storage controll block, when beginning storage pulse StoreStart is effective, produce storage array address (MemQAddr, MemEcolAddr and MemElsAddr: point to the 0th address location respectively), produce data rows initial value (=0) simultaneously.

2. write fashionablely when the 0th data of A matrix (=0), do not carry out storage operation, only to data rows number add up (=1).

3. working as the 1st data of A matrix (=5) writes fashionable, produce storage array data write signal MemQWe, at this moment, storage array data M emQDin (=5) and this data rows MemQEcolDin (=1) write in storage array block0 and the 0th address location of block2 simultaneously; Write finish after, data address MemQAddr, data rows address MemEcolAddr, every capable nonzero element number M emElsDin add 1, data rows number adds 1 (=2).

4. three data of A matrix of input all are 0 subsequently, do not carry out storage operation, only to data rows number add up (MemQEcolDin=4).

5. working as the 5th data of A matrix (=2) writes fashionable, to produce storage array data write signal MemQWe, at this moment, storage array data M emQDin (=2) and this element column MemQEcolDin (=5) write in block0 and the 1st address location of block2 simultaneously; Write finish after, data address MemQAddr, data rows address MemEcolAddr, every capable nonzero element number M emElsDin add 1, data rows number adds 1 (=5); Produce every capable nonzero element number write signal MemElsWe according to data column number value (MemQEcolDin=5), write current line nonzero element number M emElsDin (=2) in the block5 piece this moment, finished writing of the 0th line data this moment.

6. the repetition 2～5 that writes of several line data in back goes on foot.

7. after data all deposited in, the table of comparisons 1 was described, and the data of respectively storing sub-piece storage in the storage array piece are as follows:

block0：{5；2；1；2；1；3；1；3；3}；

block2：{1；5；0；1；5；0；0；3；5}；

block5：{2；1；2；1；2；1}；

The data readout:

When data were read at memory module MemMode=10, data, data rows number and every capable nonzero element number were read separately.

1. in storage controll block, when beginning load pulses LoadStart is effective, produce the initial address (MemQAddr, MemEcolAddr and MemElsAddr: carry out the initialization setting according to calculating needs, this example is to point to the 0th memory cell) of storage array; Produce the storage array data simultaneously and read (MemQRd, MemEcolRd and MemElsRd), at this moment, according to initial address (MemQAddr, MemEcolAddr and MemElsAddr), respectively data (=5), data rows number (=1) and nonzero element number (=2) are read into the output buffers of storing in the controll block in advance.

2. when data reading signal ImgQRd, data rows read signal EcolRd and every capable nonzero element number read signal ElsRd are effective, data output respectively from the output buffers of storage controll block, at this moment, storage controll block view data output (800) is 5, number output (802) of storage controll block view data row is 1, and the storage controll block every capable nonzero element number output of view data (803) is 2.

3. after data are read, take off one group of data from buffer memory, repeated for second step, all read, so far finished read operation the storage array piece up to all data to buffer memory.

According to the above-mentioned storage means of the present invention, for the 6*6 single element sparse matrix of the foregoing description 1, the sparse factor is 0.25.If adopt the pointwise storage means, need 36 memory spaces, and use storage means of the present invention, only need 24 memory spaces.Therefore, can save 12 memory spaces.

Embodiment 2

Be that example further specifies method of the present invention with the memory module MemMode=11 in the table 1 below:

If the view data that the external control unit need be stored is template figure view data QDin, memory module MemMode=11, image dimension are the B matrix of 6*6:

$B=\left(\begin{array}{cccccc}(1,2)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)\\ (0,0)& \left(\mathrm{0,3}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)\\ \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& (4,0)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)\\ \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{5,6}\right)\\ \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{7,8}\right)& \left(\mathrm{0,0}\right)\\ \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{8,9}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)& \left(\mathrm{0,0}\right)\end{array}\right)$

Data writing process:

When memory module MemMode=11, find out that by table 1 the storage array blocks of data is assigned as: block4 storing template figure nonzero element real part; Block5 storing template figure nonzero element imaginary part; Block6 storing template figure nonzero element row number; The every capable nonzero element number of block7 storing template figure.Data real part, data imaginary part and data rows number are written in parallel to; The ablation process of view data when memory module MemMode=11 is identical with the ablation process of embodiment 1 view data.

When the 0th view data (=(1 of B matrix, 2)) write fashionable, storage controll block produces storage array data write signal MemQWe, at this moment, storage array data real part MemQ0Din (=2), storage array data imaginary part MemQ1Din (=1) and this data rows MemQEcolDin (=0) write in storage array block4, block5 and the 0th address location of block6 simultaneously; Write finish after, data address MemQAddr, data rows address MemEcolAddr, every capable nonzero element number M emElsDin add 1, data rows number adds 1 (=1); When data rows number is added to 5, produce every capable nonzero element number write signal MemElsWe, write current line nonzero element number M emElsDin (=1) in the block7 piece this moment, finished writing of the 0th line data at this moment.

7. after data all deposited in, the table of comparisons 1 was described, and the view data of respectively storing sub-piece storage in the storage array piece is as follows:

Block4：{2；3；0；6；8；9}；

Block5：{1；0；4；5；7；8}；

Block6：{0；1；3；5；4；2}；

Block7：{1；1；1；1；1；1}；

The data readout:

When view data is read at memory module MemMode=11, data real part and data imaginary part parallel read-out, data rows number and every capable nonzero element number are read separately.View data is identical with the readout of embodiment 1 view data at the readout of memory module MemMode=11.According to initial address (MemQAddr, MemEcolAddr and MemElsAddr), simultaneously data real part (=2), data imaginary part (=1), data rows number (=0) and every capable nonzero element number (=1) are read into the output buffers of storing in the controll block in advance.When view data read signal ImgQRd, view data row read signal EcolRd and every capable nonzero element number read signal ElsRd are effective, reading respectively in the output buffers of data from storage controll block, at this moment, storage controll block view data real part output (800) is 2, storage controll block view data imaginary part output (801) is 1, number output (802) of storage controll block view data row is 0, and the storage controll block every capable nonzero element number output of view data (803) is 1.After data are read from buffer memory, take off one group of data to buffer memory, all read up to all data.

According to the above-mentioned storage means of the present invention, for the 6*6 dual element sparse matrix of the foregoing description 2, the sparse factor is 0.167.If adopt the pointwise storage means, need 72 memory spaces, and use storage means of the present invention, only need 24 memory spaces.Therefore, can save 48 memory spaces.Along with the increase of sparse matrix dimension and reducing of the sparse factor, image data storage of the present invention realizes that effect can be more obvious.

Claims (3)

1. the storage means of a view data, it is characterized in that, divide the storage array piece into eight sub-pieces, be respectively zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2, the 3rd sub-piece Block3, the 4th sub-piece Block4, the 5th sub-piece Block5, the 6th sub-piece Block6, the 7th sub-piece Block7; When storage controll block writes the storage array piece with view data, tight matrix is adopted the method for pointwise storage, sparse matrix is adopted the storage means of CSR form, with reference map data and template diagram data according to four kinds of different memory module MemMode: the tight matrix 00 of single element, the tight matrix 01 of dual element, single element sparse matrix 10 and dual element sparse matrix 11 store in eight sub-pieces, wherein single element is the real part of data, dual element is the real part+imaginary part of data, and the data allocations mode is as follows:

When memory module MemMode=00, Block0～Block3 stored reference diagram data, Block4 and Block5 storing template diagram data, the every capable nonzero element number of Block6 stored reference figure, the every capable nonzero element number of Block7 storing template figure;

When memory module MemMode=01, Block0 and Block2 stored reference diagram data real part, Block1 and Block3 stored reference diagram data imaginary part, Block4 storing template diagram data real part, Block5 storing template diagram data imaginary part, the every capable nonzero element number of Block6 stored reference figure, the every capable nonzero element number of Block7 storing template figure;

When memory module MemMode=10, Block0 and Block1 stored reference figure nonzero element, Block2 and Block3 stored reference figure nonzero element row number, Block4 storing template figure nonzero element, the every capable nonzero element number of Block5 stored reference figure, Block6 storing template figure nonzero element row number, the every capable nonzero element number of Block7 storing template figure;

When memory module MemMode=11, Block0 stored reference figure nonzero element real part, Block1 stored reference figure nonzero element imaginary part, Block2 stored reference figure nonzero element row number, the every capable nonzero element number of Block3 stored reference figure, Block4 storing template figure nonzero element real part, Block5 storing template figure nonzero element imaginary part, Block6 storing template figure nonzero element row number, the every capable nonzero element number of Block7 storing template figure;

The controlled step of image data storage is:

(1) when beginning storage pulse StoreStart is effective, produce storage array data address MemQAddr and data rows address MemEcolAddr by data initial address AddrQStart, produce every capable nonzero element number address MemElsAddr by every capable nonzero element number initial address AddrEStart, produce the data rows initial value simultaneously;

(2) write fashionablely when view data,, only data rows number is added up if data are zero; If data are nonzero element, will produce storage array data write signal MemQWe, these data and row number write the sub-piece of storage array respective stored according to above data allocations mode; Write finish after data address MemQAddr, data rows address MemEcolAddr, every capable nonzero element number M emElsDin and data rows number add 1; After a row element writes end, produce every capable nonzero element number write signal MemElsWe, current line nonzero element number is write the sub-piece of the corresponding storage of storage array piece;

(3) the next line data write repeating step (2), until depositing total data in;

When (4) view data is read, storage controll block generates read signal and the address to storage array, because storage array is that flowing water is read, when beginning load pulses LoadStart is effective, produce storage array data address MemQAddr and data rows address MemEcolAddr by data initial address AddrQStart, produce the every capable nonzero element number address MemElsAddr of storage array by every capable nonzero element number initial address AddrEStart, produce storage array data reading signal MemQRd simultaneously, data rows read signal MemEcolRd and every capable nonzero element number read signal MemElsRd, according to described MemQAddr, MemEcolAddr and MemElsAddr address signal, the view data that deposits in is read into the output buffers of storing controll block in advance, as view data read signal ImgQRd, data rows read signal EcolRd, sense data from the output buffers of storage controll block again after every capable nonzero element number read signal ElsRd arrives, data rows number and every capable nonzero element number.

2. the storage means of view data as claimed in claim 1 is characterized in that, in described eight sub-pieces, zero sub-piece Block0, the first sub-piece Block1, the second sub-piece Block2 memory capacity are identical, and bigger 1 times than the memory capacity of the 3rd sub-piece Block3; The size of the 4th sub-piece Block4 to the seven sub-piece Block7 memory capacity is 1/4 of the 3rd sub-piece Block3 memory capacity.

3. the storage means of view data as claimed in claim 1, it is characterized in that, when storage controll block writes the storage array piece with view data, for the tight matrix of dual element, data real part MemQ0Din and data imaginary part MemQ1Din are written in parallel to, for single element or dual element sparse matrix, data real part MemQ0Din, data imaginary part MemQ1Din and row MemEcolDin thereof are written in parallel to; When data are read from the storage array piece, for the tight matrix of dual element, data real part MemQ0Din and data imaginary part MemQ1Din parallel read-out, every capable nonzero element number M emElsDin reads separately, for single element or dual element sparse matrix, data real part MemQ0Din and data imaginary part MemQ1Din parallel read-out, data rows MemEcolDin and every capable nonzero element number M emElsDin read separately.