CN101783663A - Controllable on/off circuit - Google Patents
Controllable on/off circuit Download PDFInfo
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- CN101783663A CN101783663A CN200910215284A CN200910215284A CN101783663A CN 101783663 A CN101783663 A CN 101783663A CN 200910215284 A CN200910215284 A CN 200910215284A CN 200910215284 A CN200910215284 A CN 200910215284A CN 101783663 A CN101783663 A CN 101783663A
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Abstract
The invention provides a controllable on/off circuit. The controllable on/off circuit comprises a first reset circuit, a second reset circuit and a latching circuit, wherein the second reset circuit comprises a reset chip U2, a regulating capacitor E3 and an NPN triode Q5;The input end of the first reset circuit is connected with a power button S1; the input end of the second reset circuit is connected with the power button S1 through the latching circuit; the output end of the first reset circuit and the Cd end of the reset chip U2 are connected to the positive pole of the regulating capacitor E3; the Vdd end of the reset chip U2 is the input end of the second reset circuit; the OUT end of the reset chip U2 is connected with the base of the triode Q5; the collector of the triode Q5 is connected to a complete machine system power supply VSYSTEM through an MOS tube Q2; and the power button S1 and the collector of the triode Q5 are connected to both ends of the power supply VPOWER in parallel. The invention can switch the on/off state by pressing one button only after treating the hardware circuit, and does not need software programming, thereby having the advantage of low cost.
Description
[technical field]
The present invention relates to a kind of circuit, particularly a kind of controlled on/off circuit.
[background technology]
In the telecommunications application industry, on/off circuit there is higher requirement, and, requires on/off circuit to want wrong action protection, anti-shake at mid-to high-end product, and the software-controllable function.But existing on/off circuit needs a programming device (as single-chip microcomputer), and circuit need be programmed and participated in the switching on and shutting down process; In addition, the time set of switching on and shutting down is to realize by software, therefore causes integrated circuit price comparison height.
As shown in Figure 1, it shows a kind of existing on/off circuit, comprises a NPN triode BG2, and it hangs down and turn-off by the high-low level control sets electrode of base stage and the high conducting of turn-on and turn-off of emitter; One PNP triode BG1, it hangs down conducting by the high-low level control sets electrode of base stage and the turn-on and turn-off of emitter, the high shutoff; One single-chip microcomputer DPJ, as programmable controller spare, it has two IO mouths of IO1/IO2 pin, also comprises a D1 diode, a SW-PB switch key.
Circuit does not power at ordinary times, press switch key after, electric current is by D1, the BG2 conducting.BG1 conducting then.Circuit powers on, and detects the io1 pin after single-chip microcomputer powers on, if certain time (as 1s) thinks that one is effectively started shooting, and puts io2=high (to high level) then.Even unclamp key circuit and still can keep conducting this moment.When shutting down, press normal button, program detects this normal button, thinks power-off operation, and the program of then deactivating is with io2=low (to low level).After waiting for that the user unclamps button, then shutdown.In the middle of work, this button can also be handled as a common button.
Because this on/off circuit needs single-chip microcomputer DPJ as programming device, and circuit need programme and participate in the switching on and shutting down process, and the time set of switching on and shutting down is to realize that by software cost greatly improves, and therefore is necessary to improve.
[summary of the invention]
The technical problem to be solved in the present invention is to provide a kind of controlled on/off circuit, only needs the processing of hardware circuit just can realize a key switch machine, need not software programming and gets involved, and cost is low.
The present invention is achieved in that a kind of controlled on/off circuit, comprises one first reset circuit, one second reset circuit, a latching circuit, and described second reset circuit comprises reset chip U2, a control capacittance E3 and a NPN triode Q5; The input of described first reset circuit is connected with power button S1, the input of described second reset circuit is connected with power button S1 by described latching circuit, the Cd end of the output of described first reset circuit and the chip U2 that resets all is connected to the positive pole of control capacittance E3, the Vdd end of chip U2 of resetting is the input of this second reset circuit, the OUT end of chip U2 of resetting connects the base stage of triode Q5 again, the collector electrode of this triode Q5 is connected to machine system power supply VSYSTEM by a metal-oxide-semiconductor Q2 again, and the collector electrode of described power button S1 and triode Q5 is attempted by the two ends of power supply VPOWER again.
Described first reset circuit further comprises reset chip U1, a control capacittance E1 and a NPN triode Q1, and the capacitance integral duration of E1 and E3 is different; The Vdd end of the described chip U1 that resets is the input of this first reset circuit, the Cd end of the described chip U1 that resets connects the positive pole of described control capacittance E1, and the output of the base stage of the described triode Q1 of OUT end connection of the described chip U1 that resets, the collector electrode of triode Q1 is the output of this first reset circuit.
Line or circuit that described latching circuit adopts two diode D2 and D3 to be formed by connecting, wherein the positive pole of D2 connects a D3.3V power supply, and the positive pole of D3 connects button S1, and the negative pole of D2 and D3 all is connected to the Vdd end of the chip U2 that resets.
This on/off circuit also comprises a NPN triode Q3, and the base earth of described triode Q3, collector electrode connect described power button S1, and emitter is connected to the positive pole of D3 in the input of described first reset circuit and the latching circuit respectively.
This on/off circuit also comprises the input port INT6 of a CPU and the delivery outlet PA7 of a CPU, and PA7 is high-impedance state at system's powered on moment, and described INT6 connects the collector electrode of Q6, and described PA7 connects the emitter of described Q4.
Reset chip U1, U2 is the R3112N241A chip.
The invention has the advantages that: adopt two reset circuits that reset chip and control capacitance composition to carry out the switching on and shutting down duration and set, only need the processing of hardware circuit just can realize a key switch machine, need not software programming gets involved, cost is low, and the time delay of switching on and shutting down process also can effectively be eliminated hardware shake and artificial misoperation.And also reserved the software control interface, shutdown process can be preserved protection application datas such as parameter is provided with for software systems.
[description of drawings]
The present invention is further illustrated in conjunction with the embodiments with reference to the accompanying drawings.
Fig. 1 is the structural representation of on/off circuit of the prior art.
Fig. 2 is the structural representation of on/off circuit of the present invention.
[embodiment]
See also shown in Figure 2ly, a kind of preferred embodiment of the present invention is provided, the controlled on/off circuit in the present embodiment comprises one first reset circuit 11, one second reset circuit 12, a latching circuit 13.
Described first reset circuit 11 further comprises reset chip U1, a control capacittance E1 and a NPN triode Q1; Described second reset circuit 12 further comprises reset chip U2, a control capacittance E3 and a NPN triode Q5; This two reset chip U1, U2 is the R3112N241A chip, and the capacitance integral duration of E1 and E3 is different; Line or circuit that described latching circuit 13 adopts two diode D2 and D3 to be formed by connecting, the positive pole of D2 connects a D3.3V power supply in the described latching circuit, and the positive pole of D3 connects power button S1, and the negative pole of D2 and D3 all is connected to the Vdd end of the chip U2 that resets.
The Vdd end of the described chip U1 that resets is the input of this first reset circuit 11, the input of this first reset circuit 11 is connected with power button S 1 by a NPN triode Q3, the Cd end of the described chip U1 that resets connects the positive pole of described control capacittance E1, the output of the base stage of the described triode Q1 of OUT end connection of the described chip U1 that resets, the collector electrode of triode Q1 is the output of this first reset circuit 11, and the output of this first reset circuit 11 is connected to the positive pole of the control capacittance E3 in described second reset circuit 12.
The Vdd end of the described chip U2 that resets is the input of this second reset circuit 12, the input of this second reset circuit 12 is connected with power button S1 by a D3 and the NPN triode Q3 in the described latching circuit 13, the Cd end of the described chip U2 that resets is connected to the positive pole of control capacittance E3, the OUT end of chip U2 of resetting connects the base stage of triode Q5 again, the collector electrode of this triode Q5 is connected to machine system power supply VSYSTEM by a metal-oxide-semiconductor Q2 again, and the collector electrode of described power button S1 and triode Q5 is attempted by the two ends of power supply VPOWER again, VPOWER is the complete machine power supply, and original power supply is provided.
The base earth of described NPN triode Q3, collector electrode connect described power button S1, and emitter is connected to the positive pole of D3 in the input of described first reset circuit 11 and the latching circuit 13 respectively.
On/off circuit in the present embodiment also can comprise the input port INT6 of a CPU and the delivery outlet PA7 of a CPU again, and PA7 is high-impedance state at system's powered on moment, and described INT6 connects the collector electrode of Q6, and described PA7 connects the emitter of described Q4.
Operation principle of the present invention is as follows:
Two reset duration that chip U1, U2 control capacittance E1 and the E3 by its Cd pin control time-delay.Its computing formula is Td=0.69*6.5*1000000*Cd; Cd is the capacitance parameter value on this pin.According to above-mentioned formula, when design circuit, the output time-delay of U2 can be designed to 1S; The output time-delay of U1 is designed to 6S.
During start, when power button S1 presses, machine system power connection, and two reset chip U1, U2 are powered simultaneously, but because of the electric capacity E1 of two chip pins and the setting duration of E3 (capacitance integral duration) different, and U2 start duration length during than shutdown; Therefore the OUT of U2 end at first produces from low to high and changes, and Q5 is with regard to conducting like this, and Q2 is conducting also, and machine system power supply VSYSTEM also produces the D3.3V in the latching circuit with regard to conducting thereupon like this, and the chip U2 that resets power supply produces self-locking.This moment, power button S1 unclamped, and the chip U1 power supply that resets is cut off, therefore can not trigger the shutdown action (prolong during because of the shutdown time delay than start, as long as when guaranteeing to start shooting by power button S1 duration less than the shutdown duration).
During shutdown, press power button S1, as long as by the shutdown duration to setting, at this moment the OUT pin of U1 produces variation from low to high, Q1 conducting, cause starting shooting time delay electric capacity E3 moment discharges over the ground, so in a single day, unclamp button S1, because of E3 has discharged, U2 is output as low, therefore Q5 ends, and Q2 also ends thereupon.Machine system power supply VSYSTEM also breaks like this, and D3.3V also breaks, and the self-locking power supply of U2 destroys like this, and at this moment machine system just is in electroless state.Above hardware switch machine process; all be that hardware circuit is realized; need not software programming gets involved; we are referred to as hard shutdown this process; and the time delay of switching on and shutting down process can effectively be eliminated hardware shake and artificial misoperation; and shutdown process can be preserved protection application datas such as parameter is provided with for software systems.
Below we will introduce the soft-off notion:
This circuit design has also been reserved the software control interface, can use IO interface INT6 and the PA7 of two CPU to realize.
After system boot was intact, power button S1 pressed, Q6 conducting this moment, INT6 pin step-down, (the INT6 pin is high at ordinary times); At this moment CPU detects this pin step-down, knows that power key S1 presses, and by the time power key S1 unclamps that at this moment just can to put PA7 be low, and E3 just discharges by Q4 like this.Like this, the output pin of U2 will become low, this moment, Q5 and Q2 ended, and machine system is with regard to power down like this.This software shutdown can remedy long shortcoming of hard unused time, is to prevent that software systems from crashing but reserve hard benefit of shutting down, and at this moment soft-off is with invalid.In this soft-off process, there are 2 needs to merit attention: just PA7 can be put lowly after 1, software will wait power button S1 to unclamp, otherwise switching on and shutting down shakes will occur; If 2, power button S 1 time of pressing reaches the shutdown duration, will trigger hard shutdown circuit, at this moment will directly hard shutdown.
In sum; the present invention adopts the two chip R3112N241A that reset to carry out the switching on and shutting down duration and set; duration can be accurate to 0.1 second; only need the processing of hardware circuit just can realize a key switch machine; cost is low; the time delay of switching on and shutting down process can effectively be eliminated hardware shake and artificial misoperation and also reserve the software control interface, and shutdown process can be preserved parameter for software systems and is provided with etc. and protect application data.
Claims (6)
1. controlled on/off circuit is characterized in that: comprise one first reset circuit, one second reset circuit, a latching circuit, described second reset circuit comprises reset chip U2, a control capacittance E3 and a NPN triode Q5; The input of described first reset circuit is connected with power button S1, the input of described second reset circuit is connected with power button S1 by described latching circuit, the Cd end of the output of described first reset circuit and the chip U2 that resets all is connected to the positive pole of control capacittance E3, the Vdd end of chip U2 of resetting is the input of this second reset circuit, the OUT end of chip U2 of resetting connects the base stage of triode Q5 again, the collector electrode of this triode Q5 is connected to machine system power supply VSYSTEM by a metal-oxide-semiconductor Q2 again, and the collector electrode of described power button S1 and triode Q5 is attempted by the two ends of power supply VPOWER again.
2. a kind of controlled on/off circuit according to claim 1 is characterized in that: described first reset circuit further comprises reset chip U1, a control capacittance E1 and a NPN triode Q1, and the capacitance integral duration of E1 and E3 is different; The Vdd end of the described chip U1 that resets is the input of this first reset circuit, the Cd end of the described chip U1 that resets connects the positive pole of described control capacittance E1, and the output of the base stage of the described triode Q1 of OUT end connection of the described chip U1 that resets, the collector electrode of triode Q1 is the output of this first reset circuit.
3. a kind of controlled on/off circuit according to claim 1, it is characterized in that: line or circuit that described latching circuit adopts two diode D2 and D3 to be formed by connecting, wherein the positive pole of D2 connects a D3.3V power supply, the positive pole of D3 connects button S1, and the negative pole of D2 and D3 all is connected to the Vdd end of the chip U2 that resets.
4. a kind of controlled on/off circuit according to claim 3, it is characterized in that: this on/off circuit also comprises a NPN triode Q3, the base earth of described triode Q3, collector electrode connects described power button S1, and emitter is connected to the positive pole of D3 in the input of described first reset circuit and the latching circuit respectively.
5. a kind of controlled on/off circuit according to claim 1, it is characterized in that: this on/off circuit also comprises the input port INT6 of a CPU and the delivery outlet PA7 of a CPU, and PA7 is a high-impedance state at system's powered on moment, described INT6 connects the collector electrode of Q6, and described PA7 connects the emitter of described Q4.
6. a kind of controlled on/off circuit according to claim 2 is characterized in that: reset chip U1, U2 are the R3112N241A chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910215284A CN101783663B (en) | 2009-12-29 | 2009-12-29 | Controllable on/off circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910215284A CN101783663B (en) | 2009-12-29 | 2009-12-29 | Controllable on/off circuit |
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| Publication Number | Publication Date |
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| CN101783663A true CN101783663A (en) | 2010-07-21 |
| CN101783663B CN101783663B (en) | 2012-09-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910215284A Expired - Fee Related CN101783663B (en) | 2009-12-29 | 2009-12-29 | Controllable on/off circuit |
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| CN102053701A (en) * | 2010-12-28 | 2011-05-11 | 东莞常禾电子有限公司 | Microprocessor sleeping and awakening circuit |
| CN102508536A (en) * | 2011-10-28 | 2012-06-20 | 惠而邦电子衡器（昆山）有限公司 | One-button startup and shutdown circuit in embedded system and control method thereof |
| CN102780478A (en) * | 2012-06-06 | 2012-11-14 | 江苏中科天安智联科技有限公司 | Vehicle-mounted keying circuit structure |
| CN103095264A (en) * | 2011-10-28 | 2013-05-08 | 成都高新区尼玛电子产品外观设计工作室 | Opening and closing machine circuit adopting two triodes |
| CN103226337A (en) * | 2013-05-03 | 2013-07-31 | 深圳市科曼医疗设备有限公司 | Startup and shutdown circuit |
| CN103293986A (en) * | 2012-03-02 | 2013-09-11 | 深圳市蓝韵实业有限公司 | One-key startup and shutdown control device for digital X-ray photography system |
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| CN105549707A (en) * | 2015-12-15 | 2016-05-04 | 上海斐讯数据通信技术有限公司 | Reset circuit and reset method for preventing device startup failure |
| CN107425835A (en) * | 2016-05-23 | 2017-12-01 | 中兴通讯股份有限公司 | A kind of on/off circuit |
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| CN102053701B (en) * | 2010-12-28 | 2012-09-26 | 东莞常禾电子有限公司 | Microprocessor sleeping and awakening circuit |
| CN102053701A (en) * | 2010-12-28 | 2011-05-11 | 东莞常禾电子有限公司 | Microprocessor sleeping and awakening circuit |
| CN103095264A (en) * | 2011-10-28 | 2013-05-08 | 成都高新区尼玛电子产品外观设计工作室 | Opening and closing machine circuit adopting two triodes |
| CN102508536A (en) * | 2011-10-28 | 2012-06-20 | 惠而邦电子衡器（昆山）有限公司 | One-button startup and shutdown circuit in embedded system and control method thereof |
| CN103293986B (en) * | 2012-03-02 | 2015-09-23 | 深圳市蓝韵实业有限公司 | One-key startup and shutdown control device for digital X-ray photography system |
| CN103293986A (en) * | 2012-03-02 | 2013-09-11 | 深圳市蓝韵实业有限公司 | One-key startup and shutdown control device for digital X-ray photography system |
| CN102780478B (en) * | 2012-06-06 | 2014-11-19 | 江苏中科天安智联科技有限公司 | Vehicle-mounted keying circuit structure |
| CN102780478A (en) * | 2012-06-06 | 2012-11-14 | 江苏中科天安智联科技有限公司 | Vehicle-mounted keying circuit structure |
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| CN105549707A (en) * | 2015-12-15 | 2016-05-04 | 上海斐讯数据通信技术有限公司 | Reset circuit and reset method for preventing device startup failure |
| CN105549707B (en) * | 2015-12-15 | 2019-07-16 | 上海斐讯数据通信技术有限公司 | A kind of reset circuit and repositioning method preventing device power-up failure |
| CN107425835A (en) * | 2016-05-23 | 2017-12-01 | 中兴通讯股份有限公司 | A kind of on/off circuit |
| CN107425835B (en) * | 2016-05-23 | 2023-01-17 | 中兴通讯股份有限公司 | Startup and shutdown circuit |
| CN107584046A (en) * | 2017-08-25 | 2018-01-16 | 苏州惠华电子科技有限公司 | A kind of duration measuring and calculating formula wire harness translation smart-cut device |
| CN108052047A (en) * | 2018-01-17 | 2018-05-18 | 攀枝花学院 | Microcontroller automatic shutdown circuitry |
| CN110292306A (en) * | 2019-06-26 | 2019-10-01 | 九阳股份有限公司 | A kind of heating means and insulating pot of insulating pot |
| CN116111992A (en) * | 2022-12-30 | 2023-05-12 | 中科可控信息产业有限公司 | Switching circuit and switching device |
| CN116111992B (en) * | 2022-12-30 | 2024-07-23 | 中科可控信息产业有限公司 | Switching circuit and switching device |
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| CN101783663B (en) | 2012-09-19 |
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Denomination of invention: Controllable on/off circuit Effective date of registration: 20131011 Granted publication date: 20120919 Pledgee: Fujian Straits bank, Limited by Share Ltd, Fuzhou science and Technology Branch Pledgor: Fujian Xinnuo Communication Technology Co., Ltd. Registration number: 2013350000034 |
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Denomination of invention: Controllable on/off circuit Effective date of registration: 20150216 Granted publication date: 20120919 Pledgee: Fujian Straits bank, Limited by Share Ltd, Fuzhou science and Technology Branch Pledgor: Fujian Xinnuo Communication Technology Co., Ltd. Registration number: 2015350000009 |
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