CN101783292A - Method for reworking metal layer - Google Patents
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- CN101783292A CN101783292A CN200910045592A CN200910045592A CN101783292A CN 101783292 A CN101783292 A CN 101783292A CN 200910045592 A CN200910045592 A CN 200910045592A CN 200910045592 A CN200910045592 A CN 200910045592A CN 101783292 A CN101783292 A CN 101783292A
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Abstract
The invention provides a method for reworking a metal layer, which is applied in the field of integrated circuit manufacture. The method comprises the following steps: carrying out chemical mechanical lapping treatment on the metal layer, and removing a waveform structure and partial metal from the surface of the metal layer to form a globally planarized metal layer; depositing a passivation layer on the metal layer; and carrying out chemical mechanical lapping treatment on the structure, and removing the passivation layer and partial metal to form a planarized metal layer. The method for reworking the metal layer can greatly reduce surface defect caused by a normal chemical mechanical lapping process, such as the defects of metal, chemical, grinding fluid residue, microparticle residue and the like, even metal surface corrosion and crater defect, can remarkably improve the defect after the chemical mechanical lapping process, and increase the rate of good products.
Description
Technical field
The present invention relates to semiconductor product and make the field, and be particularly related to a kind of rework method that is applied in the chemical mechanical milling tech.
Background technology
Adopting for the first time cmp (CMP) in the interconnection process is in tungsten plug (WPlug) flatening process of Al interconnection.But along with reducing of device size, structure becomes increasingly complex, and the shortcoming of aluminum steel is more and more obvious, comprises that operating lag (characterizing with RC) increases.Because copper has excellent conducting performance and excellent electromigration characteristic, copper-connection has replaced the aluminium interconnection gradually, and process for copper cmp (CuCMP) causes the industry attention gradually simultaneously.In general, the copper metal damascene structure comprises Semiconductor substrate, is deposited on the Semiconductor substrate upper dielectric layer, and wherein dielectric layer etch has a plurality of grooves, and barrier deposition is on the said structure surface, and layer metal deposition is on the barrier layer.
Cu CMP technology generally included for three steps.Phase I of Cu CMP technology (Platen1, P1), the waveform configurations of removing a large amount of metallic coppers and surface by bigger MRR (Material Removal rate, material removing rate) form preliminary planarization; Second stage (Platen2, P2), remove remaining metallic copper by the method that reduces grinding rate with less relatively MRR, and make to grind with accurate control grinding endpoint by endpoint detecting technology (Endpoint) and be parked on the barrier layer, when arriving grinding endpoint,, the metallic copper on all dielectric surfaces reaches the isolation purpose in order to ensure all being removed, also to carry out excessive polishing (over polish, OP) processing of certain hour; Final buffer (buff) stage (Platen3 P3) removes barrier layer (Ta/TaN) and a certain amount of dielectric with further raising flattening surface degree, the minimizing defective, and with a large amount of deionized waters (DIW) cleaning grinding pad and wafer.
In actual production, can produce a lot of defectives after the CMP technology, modal is that metal, chemicals, lapping liquid and particulate (particle) are residual, and corrosion (corrosion) and crater (crater) defective etc.At this time, just need carry out heavy industry to it, heavy industry is exactly to process again, promptly carries out the grinding of certain hour again or directly removes by cleaning in CMP second stage and phase III, and wherein the length of this milling time is decided according to the thickness of the remaining metal of reality.Existing heavy industry technology is very easy to cause the metal surface to corrode and the metal infringement when removing above-mentioned defective, when removing native defect, bring many more corrosion and metal infringement defective, so the risk of heavy industry failure is very big, the regular chip rejection that causes, effect is very undesirable (to please refer to Fig. 1 a and Fig. 1 b, Fig. 1 a and Fig. 1 b are depicted as the defective effect comparison diagram that the rework method that adopts prior art is handled wafer), therefore need badly and a kind ofly the risk of processed wafer again can be reduced to minimum rework method.
Summary of the invention
The present invention proposes a kind of method for reworking metal layer, and it can significantly reduce the chip surface defective, reduces the wafer learies and improves the final yield of chip.
In order to achieve the above object, the present invention proposes a kind of method for reworking metal layer, is applied to integrated circuit and makes the field, and this method comprises the following steps:
Described metal level is carried out cmp handle, remove the waveform configuration of layer on surface of metal and the metal level that part metals forms overall planarization;
Deposit passivation layer on above-mentioned metal level;
Said structure is carried out cmp handle, remove the metal level that passivation layer and part metals form planarization.
Optionally, described metal level is a copper metal layer.
Optionally, described passivation layer is silicon nitride layer or silicon dioxide layer.
Optionally, the thickness of described passivation layer is 200 dusts～3000 dusts.
Optionally, the cmp speed that forms the metal level of overall planarization be 1000 dusts/minute～8800 dusts/minute, the time is 30 seconds～300 seconds.
Optionally, the cmp speed of removing passivation layer and part metals step be 350 dusts/minute～4500 dusts/minute, the time is 20 seconds～300 seconds.
In order to achieve the above object, the present invention more proposes a kind of method for reworking metal layer that is applied in the metal damascene structure chemical mechanical milling tech, described metal damascene structure comprises Semiconductor substrate, dielectric layer is deposited on the described Semiconductor substrate, described dielectric layer etch has a plurality of grooves, barrier deposition is on the said structure surface, and layer metal deposition is on described barrier layer, and wherein this method for reworking metal layer comprises the following steps:
Described metal level is carried out cmp handle, remove the waveform configuration of layer on surface of metal and the metal damascene structure that part metals forms overall planarization;
Deposit passivation layer on the process metal damascene structure of above-mentioned processing;
Said structure is carried out cmp once more handle, remove the metal damascene structure that passivation layer and part metals form planarization.
Optionally, described metal level is a copper metal layer.
Optionally, described passivation layer is silicon nitride layer or silicon dioxide layer.
Optionally, the thickness of described passivation layer is 200 dusts～3000 dusts.
Optionally, the cmp speed that forms the metal damascene structure of overall planarization be 1000 dusts/minute～8800 dusts/minute, the time is 30 seconds～300 seconds.
Optionally, the cmp speed of removing passivation layer and part metals step be 350 dusts/minute～4500 dusts/minute, the time is 20 seconds～300 seconds.
The method for reworking metal layer that the present invention proposes, deposit passivation layer on the metal level of overall planarization is carried out cmp afterwards and is handled, and removes passivation layer and part metals and forms the metal level of planarization.This method can significantly reduce the blemish that may cause behind the normal chemical mechanical milling tech: comprise defective even corrosion and crater defectives such as metal, chemicals, lapping liquid and particulate be residual, can significantly improve the defective behind the chemical mechanical milling tech, improve the final yield of chip.
Rework method of the present invention at first carries out cmp to the copper metal layer on the wafer to be handled, form overall planarization, increase the milling time of cmp phase III then behind deposited silicon nitride layer on the copper metal layer or silicon dioxide layer, wherein silicon nitride layer or silicon dioxide layer use as passivation layer in follow-up grinding processing procedure.Remove silicon nitride or silica membrane earlier and then grind away a part of copper metal layer; metal residue is because be standing shape; be wrapped in than copper metal layer surface height and by silicon nitride or silica membrane; therefore metal residue can be removed with silicon nitride or silica membrane; in the process of removing silicon nitride layer and part ditch buried copper metal; defectives such as metal/chemicals/lapping liquid or particulate are residual; even corrosion and crater defective can be removed together; because there is the protection of passivation layer silicon nitride film on the surface, thereby can not cause corroding or the generation of metal damage.
Description of drawings
Fig. 1 a and Fig. 1 b are depicted as and adopt existing rework method to handle the defective effect comparison diagram of wafer.
Figure 2 shows that the flow chart of preferred embodiment method for reworking metal layer of the present invention.
Figure 3 shows that the flow chart that is applied to the method for reworking metal layer in the metal damascene structure chemical mechanical milling tech of preferred embodiment of the present invention.
Fig. 4 a and Fig. 4 b are depicted as the defective effect comparison diagram that adopts rework method of the present invention to handle wafer.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate institute's accompanying drawing to be described as follows.
The present invention proposes a kind of method for reworking metal layer, and it can significantly reduce the metal residue defective, improves chip yield and reduces the wafer learies.
Please refer to Fig. 2, Figure 2 shows that the flow chart of preferred embodiment method for reworking metal layer of the present invention.As can be seen from Figure 2, the present invention proposes a kind of method for reworking metal layer, and it comprises the following steps:
Step S10: described metal level is carried out cmp handle, remove the waveform configuration of layer on surface of metal and the metal level that part metals forms overall planarization;
Step S20: deposit passivation layer on above-mentioned metal level;
Step S30: said structure is carried out cmp handle, remove the metal level that passivation layer and part metals form planarization.
Please refer to Fig. 3 again, Figure 3 shows that the flow chart that is applied to the method for reworking metal layer in the metal damascene structure chemical mechanical milling tech of preferred embodiment of the present invention.As can be seen from Figure 3, the present invention more proposes a kind of method for reworking metal layer that is applied in the metal damascene structure chemical mechanical milling tech, described metal damascene structure comprises Semiconductor substrate, dielectric layer is deposited on the described Semiconductor substrate, described dielectric layer etch has a plurality of grooves, barrier deposition is on the said structure surface, and layer metal deposition is on described barrier layer, and wherein this method for reworking metal layer comprises the following steps:
Step S100: described metal level is carried out cmp handle, remove the waveform configuration of layer on surface of metal and the metal damascene structure that part metals forms overall planarization;
Step S200: deposit passivation layer on the process metal damascene structure of above-mentioned processing;
Step S300: said structure is carried out cmp once more handle, remove the metal damascene structure that passivation layer and part metals form planarization.
The preferred embodiment according to the present invention, described metal level are copper metal layer, and described passivation layer can be silicon nitride layer, silicon dioxide layer or fluorinated silica layer, and the thickness of passivation layer is 200 dusts～3000 dusts.
To handle (Cu CMP) at the cmp of copper metal layer is example, in the practical operation engineering, when desire is carried out the chemical grinding processing to the wafer that is electroplate with copper metal layer, phase I (the Platen1 that keeps the Cu CMP technology in the prior art, P1), by bigger MRR (Material Removal rate, material removing rate) removes the metal damascene structure that a large amount of copper and surperficial waveform configuration form overall planarization, wherein grinding rate can be 1000 dusts/minute～8800 dusts/minute between, the time is 30 seconds～300 seconds; Deposit passivation layer on the metal damascene structure of overall planarization then, present embodiment is that example describes with the silicon nitride layer, the thickness of the silicon nitride layer that is deposited is 200 dusts～3000 dusts, and is good with the thickness of 500 dusts, and silicon nitride layer uses as passivation layer in follow-up grinding processing procedure; Afterwards the above-mentioned wafer that deposits silicon nitride layer being carried out cmp handles; remove the metal damascene structure of silicon nitride layer and part copper metal formation planarization with less relatively MRR by the method that reduces grinding rate; wherein grinding rate be 350 dusts/minute～4500 dusts/minute; time is 20 seconds～300 seconds; metal residue is because be standing shape; be wrapped in than copper metal layer surface height and by silicon nitride film; therefore metal residue can be removed with silicon nitride film; in the process of removing silicon nitride layer and part ditch buried copper metal; defectives such as metal/chemicals/lapping liquid or particulate are residual; even corrosion and crater defective can be removed together; because there is the protection of passivation layer silicon nitride film on the surface, thereby can not cause corroding or the generation of metal damage.Use a large amount of deionized waters (DIW) cleaning grinding pad and wafer at last, finish at the cmp of copper metal layer and handle.
Please refer to Fig. 4 a and Fig. 4 b again, Fig. 4 a and Fig. 4 b are depicted as the defective effect comparison diagram that adopts rework method of the present invention to handle wafer.From Fig. 4 a and Fig. 4 b as can be seen, adopt the rework method that is applied in the chemical mechanical milling tech of the present invention to handle after, the metal residue on the wafer significantly reduces before handling, visible the present invention has the good technical effect.
In sum, the present invention proposes is applied to rework method in the chemical mechanical milling tech, deposit passivation layer on the metal damascene structure of overall planarization is carried out cmp afterwards and is handled, and removes the metal damascene structure that passivation layer and part metals form planarization.This method can significantly reduce the blemish that may cause behind the normal chemical mechanical milling tech: comprise metal, chemicals, defective even corrosion and crater defectives such as lapping liquid and particulate are residual, can significantly improve the defective behind the chemical mechanical milling tech, improve the final yield of chip.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (12)
1. a method for reworking metal layer is applied to integrated circuit and makes the field, it is characterized in that this method comprises the following steps:
Described metal level is carried out cmp handle, remove the waveform configuration of layer on surface of metal and the metal level that part metals forms overall planarization;
Deposit passivation layer on above-mentioned metal level;
Said structure is carried out cmp handle, remove the metal level that passivation layer and part metals form planarization.
2. method for reworking metal layer according to claim 1 is characterized in that described metal level is a copper metal layer.
3. method for reworking metal layer according to claim 1 is characterized in that described passivation layer is silicon nitride layer or silicon dioxide layer.
4. method for reworking metal layer according to claim 1, the thickness that it is characterized in that described passivation layer are 200 dusts～3000 dusts.
5. method for reworking metal layer according to claim 1, the cmp speed that it is characterized in that forming the metal level of overall planarization be 1000 dusts/minute～8800 dusts/minute, the time is 30 seconds～300 seconds.
6. method for reworking metal layer according to claim 1, the cmp speed that it is characterized in that removing passivation layer and part metals step be 350 dusts/minute～4500 dusts/minute, the time is 20 seconds～300 seconds.
7. method for reworking metal layer that is applied in the metal damascene structure chemical mechanical milling tech, described metal damascene structure comprises Semiconductor substrate, dielectric layer is deposited on the described Semiconductor substrate, described dielectric layer etch has a plurality of grooves, barrier deposition is on the said structure surface, layer metal deposition is characterized in that this method for reworking metal layer comprises the following steps: on described barrier layer
Described metal level is carried out cmp handle, remove the waveform configuration of layer on surface of metal and the metal damascene structure that part metals forms overall planarization;
Deposit passivation layer on the process metal damascene structure of above-mentioned processing;
Said structure is carried out cmp once more handle, remove the metal damascene structure that passivation layer and part metals form planarization.
8. method for reworking metal layer according to claim 7 is characterized in that described metal level is a copper metal layer.
9. method for reworking metal layer according to claim 7 is characterized in that described passivation layer is silicon nitride layer or silicon dioxide layer.
10. method for reworking metal layer according to claim 7, the thickness that it is characterized in that described passivation layer are 200 dusts～3000 dusts.
11. method for reworking metal layer according to claim 7, the cmp speed that it is characterized in that forming the metal damascene structure of overall planarization be 1000 dusts/minute～8800 dusts/minute, the time is 30 seconds～300 seconds.
12. method for reworking metal layer according to claim 7, the cmp speed that it is characterized in that removing passivation layer and part metals step be 350 dusts/minute～4500 dusts/minute, the time is 20 seconds～300 seconds.
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| CN200910045592A CN101783292A (en) | 2009-01-20 | 2009-01-20 | Method for reworking metal layer |
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| CN200910045592A CN101783292A (en) | 2009-01-20 | 2009-01-20 | Method for reworking metal layer |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102371534A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method for surface of wafer |
| CN102543856A (en) * | 2012-01-20 | 2012-07-04 | 上海华力微电子有限公司 | Method for repairing aluminum etching graph defects |
| CN102543842A (en) * | 2010-12-23 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for removing impurity pollution of integrated circuit device with metal interconnection structure |
| CN102909646A (en) * | 2011-08-01 | 2013-02-06 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical grinding method |
| CN103426812A (en) * | 2012-05-18 | 2013-12-04 | 无锡华润上华科技有限公司 | Aluminum wire reworking method |
-
2009
- 2009-01-20 CN CN200910045592A patent/CN101783292A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102371534A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method for surface of wafer |
| CN102371534B (en) * | 2010-08-24 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical polishing method for surface of wafer |
| CN102543842A (en) * | 2010-12-23 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for removing impurity pollution of integrated circuit device with metal interconnection structure |
| CN102909646A (en) * | 2011-08-01 | 2013-02-06 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical grinding method |
| CN102909646B (en) * | 2011-08-01 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Chemical mechanical grinding method |
| CN102543856A (en) * | 2012-01-20 | 2012-07-04 | 上海华力微电子有限公司 | Method for repairing aluminum etching graph defects |
| CN102543856B (en) * | 2012-01-20 | 2014-09-03 | 上海华力微电子有限公司 | Method for repairing aluminum etching graph defects |
| CN103426812A (en) * | 2012-05-18 | 2013-12-04 | 无锡华润上华科技有限公司 | Aluminum wire reworking method |
| CN103426812B (en) * | 2012-05-18 | 2016-08-03 | 无锡华润上华科技有限公司 | Aluminum steel bar reworking method |
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Application publication date: 20100721 |