CN101783171A - Burst write method for phase change memory - Google Patents
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Abstract
The invention discloses a burst write method for a phase change memory, which comprises the following steps that: each concurrent write bit is configured with an independent first in first out stack (FIFO); an external bus of the phase change memory inputs written data into the FIFO corresponding to each concurrent write bit at a set frequency; each concurrent write bit reads the data to be written out from the corresponding FIFOs and performs write operations; each concurrent write bit reads the next piece of data to be written out from the corresponding FIFOs instantly when finishing the current write operations; and if in the write process, the FIFO corresponding to any concurrent write bit is in a to-be-full state, the phase change memory sends a signal to inform an external bus controller of transmitting the data at a frequency required by SET until the FIFOs corresponding to each concurrent write bit is not in the to-be-full state. The burst write method has the advantages of shortening waiting time after a RESET operation and improving the writing speed of the phase change memory.
Description
Technical field
The invention belongs to the micro-nano electronic technology field, relate to a kind of phase transition storage, relate in particular to a kind of burst write method of phase transition storage.
Background technology
The phase transition storage technology is based on Ovshinsky at late 1960s (Phys.Rev.Lett., 21,1450～1453,1968) beginning of the seventies (Appl.Phys.Lett., 18,254～257,1971) phase-change thin film of Ti Chuing can be applied to that the conception of phase change memory medium sets up, and is the memory device of a kind of low price, stable performance.Phase transition storage can be made on the silicon wafer substrate, its critical material is that the research focus of recordable phase-change thin film, heating electrode material, thermal insulation material and extraction electrode material also just launches around its device technology: the physical mechanism research of device comprises how reducing device material etc.The ultimate principle of phase transition storage is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude can realize writing, wipe and read operation of information.
Phase transition storage owing to have reads at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, is thought flash memories that most possible replacement is present by international semiconductor TIA and becomes following storer main product and become the device of commercial product at first.
The reading and writing of phase transition storage, wiping operation apply the voltage or the current pulse signal of different in width and height exactly on device cell: wipe operation (RESET), after phase-change material temperature in adding a weak point and strong pulse enable signal device cell is elevated to more than the temperature of fusion, through thereby cooling realization phase-change material polycrystalline attitude is to amorphous conversion fast, promptly one state is to the conversion of " 0 " attitude again; Write operation (SET), when apply one long and pulse enable signal phase-change material temperature medium tenacity is raised under the temperature of fusion, on the Tc after, and keep a period of time to impel nucleus growth, thus realize the conversion of amorphous state to the polycrystalline attitude, promptly " 0 " attitude is to the conversion of one state; Read operation after adding a very weak pulse signal that can not exert an influence to the state of phase-change material, is read its state by the resistance value of measuring element unit.
Although the phase transition storage great application prospect, and attracted industry to pay close attention to widely, still there are several gordian technique points not to be well solved.Wherein, the writing speed of phase transition storage is the problem that industry is concerned about most.Because phase transition storage SET is different with RESET speed, usually, SET speed is less than RESET speed.At traditional concurrent writing, carry out in the ablation process at phase transition storage so, what really determine phase transition storage speed is SET speed but not RESET speed.Industry proposed certain methods and optimized the phase transition storage writing mode, as patent 02826572.6, and SET one monoblock phase transition storage in advance, thus be to carry out the RESET operation when writing data.This mode preferably resolves speed issue, has but attracted power consumption and chip area problem.SET one monoblock phase transition storage need expend a large amount of power consumptions in advance, and aforesaid way must leave a blank phase change memory piece as redundancy, has then wasted chip area.And for example patent 200810041415.8, propose to carry out simultaneously at SET with pipeline system the RESET operation of RESET next bit.But the method need have strict requirement to the address that front and back two secondary data write, thereby has limited its usable range.
Because RESET is different with the SET required time, the SET time is long than the RESET time, so be written in parallel in the process at phase transition storage, the required time that writes of each byte was determined by the SET time, and the position of carrying out the RESET operation is in waiting status, thereby has wasted the writing speed of phase transition storage.
Thus, be necessary the phase transition storage writing speed is optimized.
Summary of the invention
Technical matters to be solved by this invention is: a kind of burst write method of phase transition storage is provided, can improves the phase transition storage writing speed.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of burst write method of phase transition storage, described method is equipped with an independently first-in first-out storehouse FIFO to each that is written in parallel to; Utilize the buffer memory of FIFO as phase transition storage SET/RESET running time difference.Particularly, described method comprises the steps:
A, phase transition storage adopt concurrent writing;
Each of B, concurrent write is equipped with an independently first-in first-out storehouse FIFO;
C, phase transition storage external bus will write data with the frequency of setting and be input among each corresponding FIFO of concurrent write;
Each of D, concurrent write is read the data that will write from the FIFO of correspondence, and carries out write operation;
Each of E, concurrent write is finished current write operation and read later on the data that write that the next one will carry out at once from the FIFO of correspondence, and carries out next step write operation;
If F is in ablation process, the FIFO of any correspondence of concurrent write is in " will expire " state, " will expire " state refers to can only write the one digit number certificate again among the FIFO, phase transition storage sends the signalisation external bus controller so, requires bus controller with the required frequency sending data of SET; Each corresponding FIFO up to concurrent write is not in " will expire " state, and then phase transition storage sends the signalisation external bus controller, requires bus controller to recover original frequency sending data;
If G is in ablation process, the FIFO of any correspondence of concurrent write is in " sky " state, does not promptly have data among the FIFO, then stops this write operation, up to the FIFO of correspondence data is arranged, and then reads these data at once, carries out write operation.
As a preferred embodiment of the present invention, the frequency of described setting is the required frequency of phase transition storage one writing operation, or writes the required frequency of " 0 " operation, or between the two.
As a preferred embodiment of the present invention, one writing is operating as the RESET operation, writes " 0 " and is operating as the SET operation.
As a preferred embodiment of the present invention, described phase transition storage comprises several storage wings plane; Described plane comprises n storage block block and n first-in first-out storehouse FIFO, the corresponding FIFO of each block; Wherein, n is a phase transition storage concurrent reading and concurrent writing figure place; Rely on data bus, address bus and control bus to be connected between plane and the plane; Described block comprises storage array, ranks code translator and driving circuit.
As a preferred embodiment of the present invention, described storer is made of GeSbTe, SiSbTe, SiGe, SbTe or SiSb material, is to become the storer of mechanism mutually.
As a preferred embodiment of the present invention, in phase transition storage inside, phase transition storage is split into several pieces block, and each block has and have only one to write driving circuit, and has independently decoding scheme; Be that each of concurrent writing writes be in the different block of phase transition storage, to carry out.
As a preferred embodiment of the present invention, described block includes a FIFO.
As a preferred embodiment of the present invention, each cell fifo is for not only preserving the current information that writes data, but also preserving the current address information that writes data; Perhaps cell fifo is for only preserving the current information that writes data.
As a preferred embodiment of the present invention, described external bus and external bus controller possess the ability of regulating bus frequency according to control signal.
Beneficial effect of the present invention is: the burst write method of the phase transition storage that the present invention proposes, can improve the phase transition storage writing speed.
At first,, do not influence, reduced the RESET operation stand-by period afterwards thus so each when carrying out RESET or SET operation, can not be subjected to other positions whether to carry out SET as conventional concurrent writing because each obtains data independently from FIFO;
Secondly, as a whole, RESET is identical with the probability that SET takes place.Promptly write fashionable (being under the burst write mode) in mass data, each RESET that carries out is the same with the number of times that SET takes place.The whole time of each write operation is roughly the same.So the writing rate of the method is the mean value of RESET speed and SET speed as a whole, relying on SET speed fully than conventional concurrent writing has had greatly raising;
Once more,, require to reduce bus transfer rate, overflow, cause data to fail to write situation, so FIFO is in the whole writing rate of time effects of " will expire " state to prevent FIFO because the present invention will propose when FIFO " will expire " state.If it is bigger that FIFO sets, then FIFO be in " will expire " state time must be shorter, whole writing rate is very fast, but chip area is bigger, cost is higher; If it is less that FIFO sets, then FIFO be in " will expire " state time must be longer, whole writing rate is slower, but chip area is less, cost is lower.This just provides line of products than horn of plenty for the phase transition storage product, with the different application of correspondence;
The 4th, according to the present invention, if write in the data in integral body, RESET operation takes place more, and that the SET operation takes place is less, then can the accelerate bus frequency, improve whole writing speed.This optimization that just writes data for the upper strata provides may.And traditional approach must be written in parallel to the position and all carries out RESET operation and just might realize quickening, and this almost is impossible realize.
Description of drawings
Fig. 1 is the phase change memory array synoptic diagram.
Fig. 2 is a phase change memory piece synoptic diagram.
Fig. 3 realizes synoptic diagram for code translator.
Fig. 4 realizes synoptic diagram for driving circuit.
Fig. 5 is a phase change memory wing synoptic diagram.
Fig. 6 is the conventional concurrent writing synoptic diagram.
Fig. 7 a is a writing mode synoptic diagram of the present invention.
Fig. 7 b is in the writing mode process of the present invention, the FIFO situation of change that each is corresponding.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Embodiment one
The present invention is directed to phase transition storage and burst and write (burst write) mode, propose a kind of method that can quicken whole burst write speed.So-called burst write mode, promptly the outside has mass data to deposit in the storer.In this manner, generally be that external bus controller is sent to data to be written on the external bus with certain frequency, storer obtains write command from external bus, writes data and writes the address, carries out write operation.Because data volume is very big, so do not consider the speed of independent write-once data in this manner usually, but considers the whole speed that writes data, and use concurrent writing to carry out multidigit usually to write.
The present invention has at first disclosed a kind of phase transition storage, and in phase transition storage inside, phase transition storage is split into several pieces block, and each block has and have only one to write driving circuit, and has independently decoding scheme; Be that each of concurrent writing writes be in the different block of phase transition storage, to carry out.Described block includes a FIFO.
See also Fig. 5, described phase transition storage comprises several storage wings plane; Described plane comprises n storage block block and n first-in first-out storehouse FIFO, the corresponding FIFO of each block; Wherein, n is a phase transition storage concurrent reading and concurrent writing figure place; Rely on data bus, address bus and control bus to be connected between plane and the plane; Data bus transmits and writes data or sense data, the address bus transfer address, and control bus transmits read-write.Described block comprises storage array, ranks code translator and driving circuit.In plane inside, FIFO accepts read-write from bus.
When write signal arrived, FIFO downloaded data to be written and address from bus; Each cell fifo is for not only preserving the current information that writes data, but also preserving the current address information that writes data; Perhaps cell fifo is for only preserving the current information that writes data.Block carries out write operation according to fifo status.This system can utilize FIFO to eliminate the mistiming that phase transition storage is write " 0 " and one writing, makes whole writing speed be improved.
See also Fig. 1, phase change memory array is arranged in mode as shown in Figure 1, and word line and bit line are crisscross, and each point of crossing is a phase-change memory cell 111.
Phase change memory piece block can make up in mode as shown in Figure 2.The periphery of ranks code translator and read-write drive arrangement and storage array, and mate with memory array size.Each storage block all has independent rows column decoding and driving circuit.
Fig. 3 has represented a kind of ranks design of encoder mode.A, B are input port, and O1, O2, O3, O4 are output port.
Fig. 4 has represented a kind of design of drive circuit mode of writing.Constituted one group of current mirror by PMOS pipe 204,205 and current source 206; The drain terminal of PMOS pipe 205 provides drive current to operating unit.
For convenience of explanation, suppose that now the mode that phase transition storage adopts 4 bit parallels to write makes up.Fig. 5 is a storage wing plane of phase transition storage, comprises 4 block, 4 corresponding FIFO, and write control module.A plane realizes data write by data bus, address bus and control bus.Whole phase transition storage can have a plurality of plane, and all plane link together by bus.In burstwrite, can only choose a plane to carry out write operation.
For block inside, writing mode carries out according to following rule:
(1) if FIFO is " sky " state (not having data among the FIFO), then this block does not carry out write operation.
(2) if FIFO is not " sky " state, block is sense data from FIFO, carries out write operation.
(3) after current write operation is finished, read data fifo immediately.As FIFO is empty, operates with reference to (1); As not operating with reference to (2) for empty.
For FIFO, in ablation process, control according to following rule:
(a) external control bus notice FIFO begins burst write operation.FIFO downloads data to be written and address from data bus and address bus immediately, and deposits cell fifo in.
(b) if FIFO is not " will expire " state (having only a cell fifo is to be written into data), then FIFO constantly downloads data to be written and address, and deposits cell fifo in according to bus clock from external bus.
(c) if FIFO is " will expire " state, FIFO downloads data to be written and address from external bus, deposits cell fifo in, and sending signal, the notice external bus controller requires external bus controller to adjust bus clock, make it identical, to guarantee not fail to write data with the SET operating frequency.
In the present embodiment, suppose that the SET required time is 3 times of RESET required time.
Fig. 6 is according to conventional concurrent writing, carries out the sequential of 3 secondary data write operations.Suppose to write data and be respectively " 0111 ", " 1011 ", " 1101 ", then as shown in the figure, the time that at every turn writes data was as the criterion with the SET time, needed 9 RESET cycles altogether.
Fig. 7 a is according to burst write mode of the present invention, carries out same data and writes.As shown in the figure, after the present bit write operation is finished, directly carry out the write operation of next bit, only need 5 RESET cycles, saved 4 RESET cycles.Fig. 7 b is for when carrying out burst write mode of the present invention, the variation of data among the corresponding FIFO.Omitted empty cell fifo among the figure.During the cycle, data are " 0111 " among the FIFO at first RESET.Each block begins corresponding operation.Second RESET finished the RESET operation for the 1st, 2,3 in the cycle, carries out writing of next data, and the 0th still carried out SET operation, so the 0th is filled data for FIFO has two cell fifos.Operation afterwards by that analogy, does not repeat them here.When data volume is very big, particularly under the more situation of RESET operand, have bigger advantage.Since burst write mode at be that mass data writes.So method of the present invention will embody greater advantages.
In addition, described storer is made of GeSbTe, SiSbTe, SiGe, SbTe or SiSb material, to become the storer of mechanism mutually.
More than introduced phase transition storage of the present invention, the present invention has also disclosed the burst write method of above-mentioned phase transition storage when disclosing above-mentioned phase transition storage.
The inventive method gives each outfit that is written in parallel to an independent F IFO.Utilize the buffer memory of FIFO, after having operated with elimination phase transition storage RESET, wait for the time of other SET operations, quicken the whole writing speed of phase transition storage as phase transition storage SET/RESET running time difference.Particularly, described method comprises the steps:
A, phase transition storage adopt concurrent writing;
Each of B, concurrent write is equipped with an independently first-in first-out storehouse FIFO;
C, phase transition storage external bus will write data with the frequency of setting and be input among each corresponding FIFO of concurrent write; The frequency of described setting can be the required frequency of phase transition storage one writing (RESET), or writes " 0 " (SET) required frequency, or between the two;
Each of D, concurrent write is read the data that will write from the FIFO of correspondence, and carries out write operation;
Each of E, concurrent write is finished current write operation and read later on the data that write that the next one will carry out at once from the FIFO of correspondence, and carries out next step write operation;
If F is in ablation process, the FIFO of any correspondence of concurrent write is in " will expire " state, " will expire " state refers to can only write the one digit number certificate again among the FIFO, phase transition storage sends the signalisation external bus controller so, requires bus controller with the required frequency sending data of SET; Each corresponding FIFO up to concurrent write is not in " will expire " state, and then phase transition storage sends the signalisation external bus controller, requires bus controller to recover original frequency sending data;
If G is in ablation process, the FIFO of any correspondence of concurrent write is in " sky " state, does not promptly have data among the FIFO, then stops this write operation, up to the FIFO of correspondence data is arranged, and then reads these data at once, carries out write operation.
Described external bus and external bus controller possess the ability of regulating bus frequency according to control signal.
In sum, the phase transition storage that the present invention proposes can improve the phase transition storage writing speed.
At first,, do not influence, reduced the RESET operation stand-by period afterwards thus so each when carrying out RESET or SET operation, can not be subjected to other positions whether to carry out SET as conventional concurrent writing because each obtains data independently from FIFO;
Secondly, as a whole, RESET is identical with the probability that SET takes place.Promptly write fashionable (being under the burst write mode) in mass data, each RESET that carries out is the same with the number of times that SET takes place.The whole time of each write operation is roughly the same.So the writing rate of the method is the mean value of RESET speed and SET speed as a whole, relying on SET speed fully than conventional concurrent writing has had greatly raising;
Once more,, require to reduce bus transfer rate, overflow, cause data to fail to write situation, so FIFO is in the whole writing rate of time effects of " will expire " state to prevent FIFO because the present invention will propose when FIFO " will expire " state.If it is bigger that FIFO sets, then FIFO be in " will expire " state time must be shorter, whole writing rate is very fast, but chip area is bigger, cost is higher; If it is less that FIFO sets, then FIFO be in " will expire " state time must be longer, whole writing rate is slower, but chip area is less, cost is lower.This just provides line of products than horn of plenty for the phase transition storage product, with the different application of correspondence;
The 4th, according to the present invention, if write in the data in integral body, RESET operation takes place more, and that the SET operation takes place is less, then can the accelerate bus frequency, improve whole writing speed.This optimization that just writes data for the upper strata provides may.And traditional approach must be written in parallel to the position and all carries out RESET operation and just might realize quickening, and this almost is impossible realize.
Embodiment two
The present invention is directed to phase transition storage and burst and write (burst write) mode, propose a kind of method that can quicken whole burst write speed.So-called burst write mode, promptly the outside has mass data to deposit in the storer.In this manner, generally be that external bus controller is sent to data to be written on the external bus with certain frequency, storer obtains write command from external bus, writes data and writes the address, carries out write operation.Because data volume is very big, so do not consider the speed of independent write-once data in this manner usually, but considers the whole speed that writes data, and use concurrent writing to carry out multidigit usually to write.
The present invention carries out phase transition storage burst write in the following way, specifically comprises the steps:
A, phase transition storage adopt concurrent writing;
Each of B, concurrent write is equipped with an independently first-in first-out storehouse (FIFO);
C, storer external bus will write data with certain frequency and be input among each corresponding FIFO of concurrent write, and this frequency can be the required frequency of phase transition storage one writing (RESET), or write " 0 " (SET) required frequency, or between the two;
Each of D, concurrent write is read the data that will write from the FIFO of correspondence, and carries out write operation;
Each of E, concurrent write is finished current write operation and read later on the data that write that the next one will carry out at once from the FIFO of correspondence, and carries out next step write operation;
If F is in ablation process, the FIFO of any correspondence of concurrent write is in " will expire " state (can only write the one digit number certificate among the FIFO again), phase transition storage sends the signalisation external bus controller so, requires bus controller with the required frequency sending data of SET.Each corresponding FIFO up to concurrent write is not in " will expire " state, and then phase transition storage sends the signalisation external bus controller, requires bus controller to recover original frequency sending data.
If G is in ablation process, the FIFO of any correspondence of concurrent write is in " sky " state (not having data among the FIFO), then stops this write operation, up to the FIFO of correspondence data is arranged, and then reads these data at once, carries out write operation.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change are possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or essential characteristic, and the present invention can be with other form, structure, layout, ratio, and realize with other assembly, material and parts.Under the situation that does not break away from the scope of the invention and spirit, can carry out other distortion and change here to disclosed embodiment.
Claims (10)
1. the burst write method of a phase transition storage is characterized in that, described method is equipped with an independently first-in first-out storehouse FIFO to each that is written in parallel to; Utilize the buffer memory of FIFO as phase transition storage SET/RESET running time difference.
2. the burst write method of phase transition storage according to claim 1 is characterized in that, described method comprises the steps:
A, phase transition storage adopt concurrent writing;
Each of B, concurrent write is equipped with an independently first-in first-out storehouse FIFO;
C, phase transition storage external bus will write data with the frequency of setting and be input among each corresponding FIFO of concurrent write;
Each of D, concurrent write is read the data that will write from the FIFO of correspondence, and carries out write operation;
Each of E, concurrent write is finished current write operation and read later on the data that write that the next one will carry out at once from the FIFO of correspondence, and carries out next step write operation;
If F is in ablation process, the FIFO of any correspondence of concurrent write is in " will expire " state, " will expire " state refers to can only write the one digit number certificate again among the FIFO, phase transition storage sends the signalisation external bus controller so, requires bus controller with the required frequency sending data of SET; Each corresponding FIFO up to concurrent write is not in " will expire " state, and then phase transition storage sends the signalisation external bus controller, requires bus controller to recover original frequency sending data;
If G is in ablation process, the FIFO of any correspondence of concurrent write is in " sky " state, does not promptly have data among the FIFO, then stops this write operation, up to the FIFO of correspondence data is arranged, and then reads these data at once, carries out write operation.
3. the burst write method of phase transition storage according to claim 1 is characterized in that:
Among the step C, the frequency of described setting is the required frequency of phase transition storage one writing operation, or writes the required frequency of " 0 " operation, or between the two.
4. the burst write method of phase transition storage according to claim 3 is characterized in that:
One writing is operating as the RESET operation, writes " 0 " and is operating as the SET operation.
5. the burst write method of phase transition storage according to claim 1 is characterized in that:
Described phase transition storage comprises several storage wings plane;
Described plane comprises n storage block block and n first-in first-out storehouse FIFO, the corresponding FIFO of each block; Wherein, n is a phase transition storage concurrent reading and concurrent writing figure place; Rely on data bus, address bus and control bus to be connected between plane and the plane;
Described block comprises storage array, ranks code translator and driving circuit.
6. the burst write method of phase transition storage according to claim 1 is characterized in that:
Described storer is made of GeSbTe, SiSbTe, SiGe, SbTe or SiSb material, is to become the storer of mechanism mutually.
7. the burst write method of phase transition storage according to claim 1 is characterized in that:
In phase transition storage inside, phase transition storage is split into several pieces block, and each block has and have only one to write driving circuit, and has independently decoding scheme; Be that each of concurrent writing writes be in the different block of phase transition storage, to carry out.
8. the burst write method of phase transition storage according to claim 7 is characterized in that:
Described block includes a FIFO.
9. the burst write method of phase transition storage according to claim 1 is characterized in that:
Each cell fifo is for not only preserving the current information that writes data, but also preserving the current address information that writes data; Perhaps cell fifo is for only preserving the current information that writes data.
10. the burst write method of phase transition storage according to claim 1 is characterized in that:
Described external bus and external bus controller possess the ability of regulating bus frequency according to control signal.
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| CN104424108A (en) * | 2013-09-05 | 2015-03-18 | 华为技术有限公司 | Write operation method and device |
| CN107451074A (en) * | 2016-06-01 | 2017-12-08 | 忆锐公司 | Memory Controller and memory module and the processor for including it |
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| JP3057498B2 (en) * | 1989-08-02 | 2000-06-26 | 富士通株式会社 | Array disk device and data reading method thereof |
| JP2001357681A (en) * | 2000-06-12 | 2001-12-26 | Sony Corp | Semiconductor storage device and its driving method |
| CN101359504B (en) * | 2008-08-05 | 2011-08-10 | 中国科学院上海微系统与信息技术研究所 | High speed recording phase change memory and high speed recording method thereof |
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| CN104424108A (en) * | 2013-09-05 | 2015-03-18 | 华为技术有限公司 | Write operation method and device |
| CN104424108B (en) * | 2013-09-05 | 2017-12-15 | 华为技术有限公司 | Write operation method and device |
| CN107451074A (en) * | 2016-06-01 | 2017-12-08 | 忆锐公司 | Memory Controller and memory module and the processor for including it |
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