CN101777489A - Method for automatically controlling stability of ion injection process - Google Patents
Method for automatically controlling stability of ion injection process Download PDFInfo
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- CN101777489A CN101777489A CN200910045247A CN200910045247A CN101777489A CN 101777489 A CN101777489 A CN 101777489A CN 200910045247 A CN200910045247 A CN 200910045247A CN 200910045247 A CN200910045247 A CN 200910045247A CN 101777489 A CN101777489 A CN 101777489A
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Abstract
The invention provides a method for automatically controlling stability of an ion injection process, which comprises the following steps: setting a qualified range and a safe range according to process requirements, measuring the line width of a polysilicon gate, judging whether the width of the polysilicon gate line is within the qualified range; and judging whether the measured value is within the safe range, if the measured value is within the safe range, switching to ion injection of a slightly doped drain electrode, if the measured value is beyond the upper limit value of the safe range, increasing the ion injection amount before ion injection, and if the measured value is lower than the lower limit value of the safe range, reducing the ion injection amount before ion injection; and finally carrying out annealing treatment. The invention reduces the odds that the electrical parameters of the product exceed the specifications, and makes the product support more stable.
Description
Technical field
The present invention relates to a kind of semiconductor technology, relate in particular to a kind of method of automatic control stability of ion injection process.
Background technology
In the 0.18um logic processing procedure of standard, the ion that has four times lightly doped drain (LDD) after polysilicon grid etching injects, and is in order to prevent that assembly from producing a technology of hot carrier's effect.In the 0.18um logic processing procedure of current standard, the polysilicon gate live width is important in a whole processing procedure parameter, its size can cause the variation of a plurality of electrical parameters of whole device, weigh the important parameter saturation current of device operating rate such as conduct commonly used, the size of its value is big or small very sensitive to the polysilicon gate live width just.Though during the product volume production, taked a series of measure to carry out strict control for the polysilicon gate live width on the technology, but the polysilicon gate live width situation bigger than normal or less than normal with respect to the standard live width can take place unavoidably, can cause the variation of a plurality of electrical parameters that comprise saturation current thus, if saturation current instability, in the time of then can causing the operation of the internal processing unit of device and interface unit, speed does not each other match, thereby cause chip not work normally, that is to say, when the polysilicon gate live width is bigger than normal or less than normal, do not take any correction measure, can finally cause the quality of chip to descend, when serious, can cause chip rejection.Fig. 1 is the graph of a relation of the yield loss of testing electrical property parameter and product, the testing electrical property parameter is the cut-in voltage of device 3.3V NMOS, from Fig. 1 can be apparent in view find out, increase along with testing electrical property parameter cut-in voltage, the yield loss of product is also increasing, and promptly the yield of product is more and more lower.
Take place for fear of the situation that causes the chip cisco unity malfunction because of the polysilicon gate live width is bigger than normal or less than normal, on the technology at this situation, can inject by the amount that increases or reduce the ion injection at the ion of next procedure lightly doped drain and eliminate the influence that produces bigger than normal or less than normal of polysilicon gate live width, promptly when the polysilicon gate live width is bigger than normal, the ion implantation dosage of lightly doped drain just increases accordingly, when the polysilicon gate live width is less than normal, the ion implantation dosage of lightly doped drain just reduces accordingly, finally make the internal processing unit of device and the operating rate of interface unit be complementary, work normally to guarantee chip.Yet, a kind of technology that increases or reduce the ion implantation dosage of lightly doped drain like this, at present entirely by manually finishing, do not set any standard, and, rely on fully under the situation of experience, only just can take measures at the obvious a lot of situation a lot of or less than normal bigger than normal of polysilicon gate live width, a kind of so manual operation is easy to produce bigger error, is unfavorable for the raising of chip production quality, in addition, for the polysilicon gate size not the situation within specification do not select directly to scrap yet, strengthen when ion injects or reduce the amount of injecting but still be chosen in, the product yield that final production is come out is very low, so not only wasted follow-up technology, and make yield reduce, therefore, close for the polysilicon gate size and defectively must judge earlier.
Summary of the invention
Cause supporting problem of unstable in order to overcome the manual adjustment ion implantation dosage that exists in the prior art, the invention provides a kind of method that can judge and adjust ion implantation dosage automatically.
To achieve these goals, the present invention proposes a kind of method of automatic control stability of ion injection process, may further comprise the steps: step S1: require to set interval of acceptance and security interval according to processing procedure; Step S2: measure the polysilicon gate live width, and judge whether the polysilicon gate live width of surveying is comprised in the described interval of acceptance,, then change step S4 over to,, then scrap described polysilicon if do not comprised if comprised; Step S3: judge whether measured value is comprised in the described security interval,, then change step S6 over to,, then change step S4 over to,, then change step S5 over to if be lower than the lower limit of described security interval if exceed the higher limit of described security interval if comprised; Step S4: increase ion implantation dosage, change step S6 over to; Step S5: reduce ion implantation dosage, change step S6 over to; Step S6: the ion that carries out lightly doped drain injects; Step S7: annealing in process.
Optionally, described processing procedure is the logic processing procedure of 0.18um for the grid live width.
Optionally, described security interval is included in the described interval of acceptance.
Optionally, interval of acceptance is 0.165um to 0.195um.
Optionally, described security interval is 0.175um to 0.185um
Optionally, to inject number of times be four times for described lightly doped drain ion.
Optionally, the type of four lightly doped drain ion injections is followed successively by the injection of N type lightly doped drain ion, the injection of P type lightly doped drain ion, N type lightly doped drain ion injects and P type lightly doped drain ion injects.
The useful technique effect that the present invention controls the method for stability of ion injection process automatically is: the present invention is by differentiating the size of polysilicon gate size automatically, select to keep, increase or reduce ion implantation dosage according to differentiating the result, thereby reach the purpose of the operating rate of adjusting device, the speed that finally reaches between each parts of device is complementary, reduced the probability that the product electrical parameter exceeds specification, make that also the processing procedure of product is more stable, improved the yield of product.
Description of drawings
Fig. 1 is the graph of a relation of product yield loss and testing electrical property parameter;
Fig. 2 is a schematic flow sheet of the present invention;
Fig. 3 is the result schematic diagram of prior art;
Fig. 4 is a result schematic diagram of the present invention.
Embodiment
Be described in further detail below in conjunction with the method for the drawings and specific embodiments automatic control stability of ion injection process of the present invention.
At first, please refer to Fig. 2, Fig. 2 is a schematic flow sheet of the present invention, as we can see from the figure, the method of a kind of automatic control stability of ion injection process of the present invention, may further comprise the steps: step 111: require to set interval of acceptance and security interval according to processing procedure, the meaning of setting interval of acceptance is to need only the polysilicon gate live width of measurement in interval of acceptance, though and point tolerance arranged between the standard size, but can be tolerated, also can adjust such as increasing or reduce ion implantation dosage by additive method, electrical parameter error with the product avoiding producing is excessive, and exceeded this interval of acceptance, just be regarded as waste product, standard polysilicon gate live width in the present embodiment is 0.18um, the interval of acceptance of setting is between the 0.165um to 0.195um, and security interval, then be included within the interval of acceptance, the higher limit of security interval is less than the higher limit of interval of acceptance, and the lower limit of security interval is greater than the lower limit of interval of acceptance, therefore the size in the security interval at first all will guarantee it is all qualified, secondly, the polysilicon gate live width is positioned at security interval, then do not need the ion implantation dosage of step is made any modification, inject according to the amount of routine and to get final product, because it is impossible wanting complete conformance with standard live width, the error that the polysilicon gate live width is little allows, nor can produce big influence to the electrical parameter of product in the future, therefore, have only the grid live width to exceed security interval and be positioned at the polysilicon of interval of acceptance, just can enter the flow process of the next one judgement of present embodiment, the security interval of setting in the present embodiment is 0.175um to 0.185um; Step 112: measure the polysilicon gate live width, and judge whether the polysilicon gate live width of surveying is comprised in the described interval of acceptance, be in the 0.165um to 0.195um, if not in described interval of acceptance, then change step 113 over to: scrap described polysilicon, illustrate that polysilicon in this case can not retrieve by PROCESS FOR TREATMENT; If in described interval of acceptance, then change step 114 over to: relatively whether the polysilicon gate live width of surveying is included in the described security interval, be 0.175um to 0.185um, this is further to judge and the qualification polysilicon gate live width of surveying, if still at security interval, illustrate that the polysilicon gate live width meets the requirements, then directly change step 117 over to: the ion that carries out lightly doped drain injects, step 118 afterwards: annealing in process, because after ion injects, can stay the injection damage, therefore, need repair damage by annealing in process, this is one a necessary technology after ion injects, under the normal condition, the ion that generally will carry out 4 lightly doped drains on the technology injects, and type is followed successively by N type lightly doped drain ion and injects, P type lightly doped drain ion injects, N type lightly doped drain ion injects and P type lightly doped drain ion injects, after each ion injects, all will carry out annealing in process, the back also can be described in detail this process.If measured value is not included in the described security interval, then have only two kinds of situations to occur, the one, greater than the higher limit of described security interval, the one, less than the lower limit of described security interval, when greater than the higher limit of described security interval, change step 115 over to, increase ion implantation dosage, change step 117 afterwards over to: the ion that carries out lightly doped drain injects, again after step 118: annealing in process; If during less than the lower limit of described security interval, change step 116 over to, reduce ion implantation dosage, change step 117 afterwards over to: the ion that carries out lightly doped drain injects, step 118 again: annealing in process increases and the amplitude and the situation that reduce below will be done concrete introduction about ion implantation dosage.
The standard polysilicon gate live width of present embodiment is 0.18um, the security interval of setting is 0.175um to 0.185um, the interval of acceptance of setting is 0.165um to 0.195um, polysilicon gate live width in security interval, directly carrying out the lightly doped drain ion injects, the ion that will carry out 4 lightly doped drains on the technology injects, type is followed successively by N type lightly doped drain ion and injects, P type lightly doped drain ion injects, N type lightly doped drain ion injects and P type lightly doped drain ion injects, the first road N type lightly doped drain ion injects, injecting particle is arsenic, injecting energy is 003K, and implantation dosage is 80E4; The second road P type lightly doped drain ion injects, and injecting particle is fluorine, and injecting energy is 005K, and implantation dosage is 20E4; The 3rd road N type lightly doped drain ion injects, and injecting particle is fluorine, and injecting energy is 040K, and implantation dosage is 30E3; The 4th road P type lightly doped drain ion injects, and injecting particle is phosphorus, and injecting energy is 040K, and implantation dosage is 40E3.
An existing polysilicon, through step 111, measuring its grid live width is 0.17um, can analyze thus and draw, its grid live width drops in the interval of acceptance, but not in security interval, therefore, next step ion implantation dosage need adjust, find the lower limit 0.175um of 0.17um again, therefore need to reduce ion implantation dosage less than the safety zone, and the kind of corresponding each injection particle and injection energy, be the same with polysilicon gate live width in the security interval, the just implantation dosage of change.For the grid live width is the situation of 0.17um, inject at the first road N type lightly doped drain ion, implantation dosage reduces to 70E4 from 80E4, the second road P type lightly doped drain ion injects, implantation dosage reduces to 15E4 from 20E4, and the 3rd road N type lightly doped drain ion injects, and implantation dosage reduces to 25E3 from 30E3, the 4th road P type lightly doped drain ion injects, and implantation dosage reduces to 35E3 from 40E3.
An existing polysilicon, through step 111, measuring its grid live width is 0.19um, can analyze thus and draw, its grid live width drops in the interval of acceptance, but not in security interval, therefore, next step ion implantation dosage need adjust, find the higher limit 0.185um of 0.19um greater than the safety zone again, therefore needing increases ion implantation dosage, and the kind of corresponding each injection particle and injection energy, be the same with polysilicon gate live width in the security interval, the just implantation dosage of change.For the grid live width is the situation of 0.19um, inject at the first road N type lightly doped drain ion, implantation dosage is increased to 90E4 from 80E4, the second road P type lightly doped drain ion injects, implantation dosage is increased to 25E4 from 20E4, and the 3rd road N type lightly doped drain ion injects, and implantation dosage is increased to 35E3 from 30E3, the 4th road P type lightly doped drain ion injects, and implantation dosage is increased to 45E3 from 40E3.
An existing polysilicon, through step 111, measuring its grid live width is 0.20um, can analyze thus to draw, its grid live width does not drop in the interval of acceptance, therefore takes steps 113: scrap described polysilicon.
An existing polysilicon, through step 111, measuring its grid live width is 0.16um, can analyze thus to draw, its grid live width does not drop in the interval of acceptance, therefore takes steps 113: scrap described polysilicon.
At last, please refer to Fig. 3 and Fig. 4, Fig. 3 is the result schematic diagram of prior art; Fig. 4 is a result schematic diagram of the present invention, abscissa among Fig. 3 and Fig. 4 is represented be wafer type or batch, ordinate is represented is saturation current value on the unit length of grid of wafer, unit is UA/UM, contrast two figures on the whole, can draw a conclusion very intuitively, that is exactly the amplitude that the amplitude of fluctuation up and down of the curve among Fig. 4 will be significantly less than the curve fluctuation of Fig. 3, and this also just means after having taked method of the present invention, the trend of the saturation current of product tends to be steady more, the very high or very low situation of saturation current among Fig. 3 seldom appears, and therefore the saturation current reference value that to be the product electrical parameter change just means also that the amplitude of variation of the electrical parameter of product thinks more to tend towards stability after having adopted method of the present invention.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (7)
1. automatic method of control stability of ion injection process is characterized in that may further comprise the steps:
Step S requires to set interval of acceptance and security interval according to processing procedure;
Step S2: measure the polysilicon gate live width, and judge whether the polysilicon gate live width of surveying is comprised in the described interval of acceptance,, then change step S4 over to,, then scrap described polysilicon if do not comprised if comprised;
Step S3: judge whether the polysilicon gate live width of surveying is comprised in the described security interval,, then change step S6 over to if comprised, if exceed the higher limit of described security interval, then change step S4 over to,, then change step S5 over to if be lower than the lower limit of described security interval;
Step S4: increase ion implantation dosage, change step S6 over to;
Step S5: reduce ion implantation dosage, change step S6 over to;
Step S6: the ion that carries out lightly doped drain injects;
Step S7: annealing in process.
2. the method for automatic control stability of ion injection process according to claim 1 is characterized in that described processing procedure is the logic processing procedure of 0.18um for the grid live width.
3. the method for automatic control stability of ion injection process according to claim 1 is characterized in that described security interval is included in the described interval of acceptance.
4. the method for automatic control stability of ion injection process according to claim 1 is characterized in that interval of acceptance is 0.165um to 0.195um.
5. the method for automatic control stability of ion injection process according to claim 1 is characterized in that described security interval is 0.175um to 0.185um.
6. the method for automatic control stability of ion injection process according to claim 1 is characterized in that it is four times that described lightly doped drain ion injects number of times.
7. the method for automatic control stability of ion injection process according to claim 6 is characterized in that the type of four lightly doped drain ion injections is followed successively by the injection of N type lightly doped drain ion, the injection of P type lightly doped drain ion, N type lightly doped drain ion injects and P type lightly doped drain ion injects.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102800607A (en) * | 2012-08-29 | 2012-11-28 | 上海宏力半导体制造有限公司 | Method for improving process capability |
| CN105573273A (en) * | 2015-12-15 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Method for improving semiconductor device performance fluctuation |
| CN106206303A (en) * | 2015-04-30 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of N-type fin formula field effect transistor |
| CN110112070A (en) * | 2019-04-28 | 2019-08-09 | 上海华虹宏力半导体制造有限公司 | MOS transistor and forming method thereof |
| CN112259448A (en) * | 2020-10-14 | 2021-01-22 | 上海华力集成电路制造有限公司 | Ion implantation method after grid formation |
Family Cites Families (4)
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| US6664172B2 (en) * | 2002-01-22 | 2003-12-16 | United Microelectronics Corp. | Method of forming a MOS transistor with improved threshold voltage stability |
| US20070029608A1 (en) * | 2005-08-08 | 2007-02-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Offset spacers for CMOS transistors |
| CN101106089A (en) * | 2006-07-13 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | A compensation injection method for effectively reducing LDNMOS cut-off current and avoiding dual peak feature and its application |
| US7456066B2 (en) * | 2006-11-03 | 2008-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Variable width offset spacers for mixed signal and system on chip devices |
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2009
- 2009-01-13 CN CN2009100452474A patent/CN101777489B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800607A (en) * | 2012-08-29 | 2012-11-28 | 上海宏力半导体制造有限公司 | Method for improving process capability |
| CN106206303A (en) * | 2015-04-30 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of N-type fin formula field effect transistor |
| CN106206303B (en) * | 2015-04-30 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | The forming method of N-type fin formula field effect transistor |
| CN105573273A (en) * | 2015-12-15 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | Method for improving semiconductor device performance fluctuation |
| CN105573273B (en) * | 2015-12-15 | 2018-08-14 | 上海华虹宏力半导体制造有限公司 | The method for improving performance of semiconductor device fluctuation |
| CN110112070A (en) * | 2019-04-28 | 2019-08-09 | 上海华虹宏力半导体制造有限公司 | MOS transistor and forming method thereof |
| CN112259448A (en) * | 2020-10-14 | 2021-01-22 | 上海华力集成电路制造有限公司 | Ion implantation method after grid formation |
| CN112259448B (en) * | 2020-10-14 | 2022-11-29 | 上海华力集成电路制造有限公司 | Ion implantation method after grid formation |
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