CN101770953B - Forming method of PLDD (Pocket Light Doped Drain) doped region and manufacture method of PMOS (P-channel Metal Oxide Semiconductor) device - Google Patents
Forming method of PLDD (Pocket Light Doped Drain) doped region and manufacture method of PMOS (P-channel Metal Oxide Semiconductor) device Download PDFInfo
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Abstract
The invention relates to a forming method of a PLDD (Pocket Light Doped Drain) doped region. The method comprises the following steps of: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a grid electrode and has an initial temperature; carrying out a light doping process on substrate areas on the periphery of the grid electrode, wherein a doped impurity is boron; after carrying out the light doping process, rising the temperature of the semiconductor substrate to a first temperature and keeping the first temperature of the semiconductor substrate for at least one second; rising the temperature of the semiconductor substrate from the first temperature to a peak temperature; and dropping the temperature of the semiconductor substrate from the peak temperature to the initial temperature, wherein the first temperature is lower than or equal to 550 DEG C. The invention also provides a manufacture method of a PMOS (P-channel Metal Oxide Semiconductor) device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the particularly a kind of formation method of PLDD doped region and the manufacturing approach of PMOS device.
Background technology
Metal-oxide semiconductor (MOS) (MOS) device is owing to characteristics such as its low-power consumption, quick response are widely used in fields such as computer, communication.Typical MOS device comprises grid, source electrode and drain electrode, also is formed with lightly doped region (LDD zone) in source electrode and the zone that drains near gate bottom.
Along with integrated level is increasingly high, size of devices constantly reduces, and conducting channel is also shorter and shorter, and short-channel effect is also more and more obvious to the Effect on Performance of MOS device.For this reason, industry improves the performance of MOS device through suppressing short-channel effect such as means such as forming shallow junction, low-resistivity LDD doped region.
For the PMOS device, in carrying out the PLDD ion implantation technology, the ion of injection is a P type ion boron.Because the boron ion has stronger diffusion effect, the PLDD junction depth of formation is wayward, makes to form comparatively difficulty of shallow junction PLDD.At present, main through suppressing the boron ions diffusion like surperficial pre-amorphous, the N type ion bag methods such as (Pocket implant) of mixing, form shallow junction PLDD.For example, number be CN1167113C at Granted publication, the day for announcing is just to disclose a kind of manufacturing approach with mos device of ultra-shallow junction extending area in the Chinese patent document on September 15th, 2004.When its disclosed method was made shallow junction, first shape pouch doped region was then carried out LDD and is mixed, and carries out rapid thermal anneal process then and activates the ion that LDD mixes.
Yet above-mentioned method all need be introduced extra processing step and suppress the boron ions diffusion, to improve short-channel effect, for example, in the surperficial pre-amorphous technology, need before the PLDD ion injects, carry out surperficial amorphisation to the surface of injection zone; And, need extra bag doping step for the bag doping process.Make processing step complicated.
Summary of the invention
The present invention provides a kind of formation method of PLDD doped region and the manufacturing approach of PMOS device, and processing step of the present invention is simple.
The formation method of a kind of PLDD doped region provided by the invention comprises:
Semiconductor substrate is provided, on said Semiconductor substrate, has grid, said Semiconductor substrate has initial temperature; Area around the said grid is carried out light dope technology, and the impurity that mixes is boron; Carry out after the said light dope technology, said Semiconductor substrate temperature to the first temperature that raises, and keep said Semiconductor substrate in said first temperature at least 1 second; Said Semiconductor substrate temperature is increased to peak temperature by said first temperature; Said Semiconductor substrate is cooled to initial temperature by peak temperature; Wherein, said first temperature is less than or equal to 550 ℃.
Optional, said first temperature is 500 ℃.
Optional, keeping said Semiconductor substrate is 10 seconds to 30 seconds in the time of said first temperature.
Optional, keeping said Semiconductor substrate is 15 seconds in the time of said first temperature.
Optional, said Semiconductor substrate is increased to the programming rate of peak temperature greater than the programming rate that is increased to first temperature by initial temperature by first temperature.
Optional, said peak temperature is 900 ℃ to 1000 ℃.
The present invention also provides a kind of manufacturing approach of PMOS device, comprising:
Semiconductor substrate is provided, on said Semiconductor substrate, has grid, said Semiconductor substrate has initial temperature;
Area around the said grid is carried out light dope technology, and the impurity that mixes is boron;
Carry out after the said light dope technology, said Semiconductor substrate temperature to the first temperature that raises, and keep said Semiconductor substrate in said first temperature at least 1 second;
Said Semiconductor substrate temperature is increased to peak temperature by said first temperature;
Said Semiconductor substrate is cooled to initial temperature by peak temperature;
Be cooled to after the initial temperature, form side wall layer at said gate lateral wall;
Area around said side wall layer is carried out P type heavy doping technology, forms heavily doped region;
Semiconductor substrate to being formed with said heavily doped region is carried out annealing process;
Wherein, said first temperature is less than or equal to 550 ℃.
Optional, said annealing process is the spike rapid thermal annealing, comprises the steps:
Said Semiconductor substrate to the second temperature that raises, and kept said second temperature at least 1 second;
Said Semiconductor substrate temperature is increased to second peak temperature by said second temperature;
Said Semiconductor substrate is reduced to initial temperature by peak temperature; Wherein, said second temperature is less than or equal to 550 ℃.
Optional, said second temperature is 500 ℃.
Optional, keeping said Semiconductor substrate is 10 seconds to 30 seconds in the time of said second temperature.
Optional, said first temperature is 500 ℃.
Optional, keeping said Semiconductor substrate is 10 seconds to 30 seconds in the time of said first temperature.
Optional, keeping said Semiconductor substrate is 15 seconds in the time of said first temperature.
Compared with prior art, one of them of technique scheme has the following advantages at least:
After executing PLDD light dope technology, earlier the Semiconductor substrate temperature is increased to first temperature, and kept at least 1 second in first temperature; Said first temperature is less than or equal to 550 ℃; Then, said Semiconductor substrate is increased to peak temperature by first temperature, is cooled to initial temperature then; In the above-mentioned technology, the purpose that kept at least 1 second is whole semiconductor substrate surface temperature to be reached unanimity or more consistent; And be provided with said first temperature be less than or equal to 550 ℃ of instantaneous enhancing diffusion that can be used for suppressing dopant ion (Transient Enhanced Diffusion, TED) effect, thereby can improve the short-channel effect of the device of formation; Activate through the process that is increased to peak temperature and drops to initial temperature dopant ion PLDD; Above-mentioned method has only been adjusted the PLDD doping process temperature of annealing process afterwards; Just can suppress the TED effect of PLDD dopant ion, improve short-channel effect, improve the performance of the device that forms; And do not increase other extra processing step, make processing step oversimplify.
Description of drawings
Fig. 1 is the flow chart of embodiment of the formation method of PLDD doped region of the present invention;
Fig. 2 is the generalized section of structure with Semiconductor substrate of grid;
Fig. 3 is for mixing impurity generalized section afterwards in the substrate around the grid shown in Figure 2;
Fig. 4 is to the generalized section behind the semiconductor structure execution annealing process shown in Figure 3;
Fig. 5 is the flow chart of embodiment of the manufacturing approach of PMOS device of the present invention;
Fig. 6 is the generalized section after the gate lateral wall of semiconductor structure shown in Figure 4 forms side wall layer;
Fig. 7 carries out heavy doping generalized section afterwards to the substrate around the sidewall of semiconductor structure shown in Figure 6.
Embodiment
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Annealing is mainly used in to activate and mixes the impurity in the Semiconductor substrate after carrying out PLDD light dope technology, forms the PLDD doped region, and annealing simultaneously also can be repaired lattice defect and the damage that in Semiconductor substrate, causes when mixing.
The impurity that mixes in the PLDD doping process is generally the boron ion, like B+ or BF
2+, and boron has stronger diffusion effect when heat treatment; That is to say that the annealing after the PLDD also makes the boron impurity diffusion that is incorporated in the Semiconductor substrate, causes junction depth to be deepened.Inventor of the present invention is through discovering; At 600 ℃ or the higher above-mentioned annealing process of temperature execution; The instantaneous enhancing diffusion of boron impurity (Transient Enhanced Diffusion, TED) comparatively serious, the short-channel effect of the device that this can aggravate to form; When 550 ℃ even lower annealing temperature, the TED effect not too obviously even do not have.
Based on this, the present invention proposes a kind of manufacturing approach of PLDD doped region.In the method for the invention; After carrying out PLDD light dope technology; Carry out annealing process, and annealing process is carried out through following steps: the Semiconductor substrate temperature that at first will execute said PLDD light dope technology rises to first temperature by initial temperature, and keeps at least 1 second in first temperature; Then, said Semiconductor substrate is increased to peak temperature by first temperature; Then, the temperature with said Semiconductor substrate drops to initial temperature by said peak temperature; Wherein, said first temperature is less than or equal to 550 ℃.
In above-mentioned method; After executing PLDD light dope technology, earlier the Semiconductor substrate temperature is increased to first temperature, and kept at least 1 second in first temperature; Said first temperature is less than or equal to 550 ℃; Then, said Semiconductor substrate is increased to peak temperature by first temperature, is cooled to initial temperature then; In the above-mentioned technology, the purpose that kept at least 1 second is whole semiconductor substrate surface temperature to be reached unanimity or more consistent; Be less than or equal to 550 ℃ of TED effects that can be used for suppressing dopant ion and said first temperature is set, thereby can improve the short-channel effect of the device of formation; Activate through the process that is increased to peak temperature and drops to initial temperature dopant ion PLDD; Above-mentioned method has only been adjusted the PLDD doping process temperature of annealing process afterwards; Just can suppress the TED effect of PLDD dopant ion, improve short-channel effect, improve the performance of the device that forms; And do not increase other extra processing step, make processing step oversimplify.
In addition, above-mentioned method can not influence peak temperature, thereby can not influence the activation of annealing process to the PLDD dopant ion.
Fig. 1 is the flow chart of the embodiment of PLDD formation method of the present invention.
Please refer to Fig. 1, step S100 provides Semiconductor substrate, on said Semiconductor substrate, has grid.
Step S110 carries out light dope technology to the area around the said grid, and the impurity that mixes is boron.
Step S120 carries out after the said light dope technology, said Semiconductor substrate temperature to the first temperature that raises, and keep said Semiconductor substrate in said first temperature at least 1 second; Wherein, said first temperature is less than or equal to 550 ℃.
Step S130 is increased to peak temperature with said Semiconductor substrate temperature by said first temperature.
Step S140 is cooled to initial temperature with said Semiconductor substrate by peak temperature.
Wherein, said first temperature can be 500 ℃.Keep said Semiconductor substrate in the time of said first temperature can be 10 seconds to 30 seconds, concrete, can be 15 seconds.
Be elaborated below in conjunction with the formation method of specific embodiment to PLDD doped region of the present invention.
Please refer to Fig. 2, Semiconductor substrate 100 is provided, on said Semiconductor substrate, have grid 108a, between said grid 108a and Semiconductor substrate 100, have gate dielectric layer 106a.
Wherein, said Semiconductor substrate 100 can be silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate 100 can also have epitaxial loayer or insulating barrier silicon-on.
In said Semiconductor substrate 100, can also have N trap 102.Said N trap forms through ion implantation technology, and step can be following: the photoresist pattern (not shown) that at first forms the N well region through photoetching process.Inject not carried out ion by the Semiconductor substrate 100 of said photoresist pattern covers then, form N trap 102, the ion of injection is N type ion, for example phosphorus.
Then remove said photoresist pattern through ashing and wet-cleaned.
In addition; Before forming said N trap 102 backs, removing said photoresist pattern; In said N trap 102, carry out second again and go on foot and the 3rd step ion implantation technology, with breakdown characteristics that improves the device that forms and the threshold voltage of adjusting the device that forms, the ion of injection can be a phosphorus.
In said Semiconductor substrate 100, has fleet plough groove isolation structure 104.It can form through conventional fleet plough groove isolation structure manufacturing process.
In addition, said gate dielectric layer 106a can be silica or silicon oxynitride.The method that forms said silica can be high temperature furnace pipe oxidation, rapid thermal oxidation, original position steam generation (In-Situ Stream Generation; ISSG) a kind of in the oxidizing process; Said silica is carried out nitrogen treatment can form silicon oxynitride, said nitrogenation treatment technology can be a kind of in boiler tube nitrogenize, Rapid Thermal Nitrided, the pecvd nitride (for example DPN).
Said grid 108a is a polysilicon, for the resistivity of the grid of the metal oxide semiconductor device that reduce to form, can in said polysilicon gate 108a, mix impurity.The impurity that mixes can be boron.
Please refer to Fig. 3, the Semiconductor substrate around the said grid 108a 100 is carried out P type light dope technology, in the N trap 102 around the said grid 108a, form lightly doped region 110a.Said light dope technology is ion implantation technology.
Wherein, as the mask barrier layer, carry out by autoregistration with said grid 108a for said light dope technology.
Among the embodiment therein, the impurity that this P type light dope technology is mixed is boron, and the energy of injection is 0.5KeV, and dosage is e
5Cm
-2
After accomplishing described P type light dope technology; Said Semiconductor substrate 100 is carried out annealing process; This annealing process is used for activating the foreign ion of lightly doped region 110a; And spread in the feasible N trap of foreign ion below said gate dielectric layer 106a that mixes, in addition, can also repair the implant damage that in above-mentioned P type light dope technology, Semiconductor substrate 100 is caused through described annealing process.
Wherein, said annealing can be rapid thermal annealing (RTA), further, can be spike rapid thermal annealing (spike anneal).Concrete step can be following:
At first, Semiconductor substrate 100 temperature that execute said PLDD light dope technology are risen to first temperature by initial temperature, and kept at least 1 second in first temperature; Wherein, said first temperature is less than or equal to 550 ℃.It is 10 to 30 seconds that said Semiconductor substrate 100 remains on first temperature-time.
Wherein, Need said Semiconductor substrate 100 to continue the regular hour in first temperature; Such as at least 1 second; So that whole Semiconductor substrate 100 zoness of different all have roughly the same or identical temperature, whole Semiconductor substrate 100 each regional temperature are near identical, can improve in the whole Semiconductor substrate 100 zones of different at the follow-up heat treatment that receives uniformity comparatively.
In addition; The purpose that makes the temperature of described Semiconductor substrate 100 rise to first temperature mainly is for the ease of in the subsequent technique conductor temperature being increased to peak temperature fast by first temperature; From this angle; Said first temperature is approaching more apart from peak temperature, and follow-up temperature-rise period is controlled more easily.
If that this first temperature is set is higher, no doubt can be so that follow-up temperature-rise period is convenient to control, but since when temperature is higher the PLDD dopant ion for example the TED of boron should become comparatively serious.Thereby, consider follow-up intensification control at the same time and suppress first temperature being set being less than or equal to 550 ℃, and can select suitable temperature on the basis of TED effect of PLDD dopant ion according to the device technology needs; For example, relatively pay close attention to the TED effect and not too pay attention to follow-up intensification control technology, can select the first lower temperature, otherwise, first temperature selected near (but being less than or equal to) 550 ℃ of zones.
For example, in the present embodiment, said first temperature can be 500 ℃ or 550 ℃.For example, said Semiconductor substrate 100 was kept 10 seconds or 15 seconds in the time of 500 ℃, or kept 10 seconds at 550 ℃.
That is to say, first temperature is set is less than or equal to 550 ℃ and can suppresses the TED effect, thereby improve the short-channel effect of the device that forms, improve the performance of the device that forms.
Then, said Semiconductor substrate is increased to peak temperature by first temperature; Then, the temperature with said Semiconductor substrate drops to initial temperature by said peak temperature.Be increased to peak temperature and drop to the dopant ion that the process of initial temperature is mainly used in PLDD and activate, and the lattice defect in the Semiconductor substrate 100 is repaired.
Wherein, Rising to peak temperature by first temperature and drop to the pairing time interval of temperature that peak temperature on the temperature curve of initial temperature deducts at 50 o'clock in described Semiconductor substrate 100 is peak position residence time ((Residence Time; T-50, wherein T is a peak temperature).Estimate the degree that the PLDD dopant ion in 100 in the Semiconductor substrate is activated with said peak position residence time.That is to say that when peak temperature was fixed value, the peak position residence time can influence the activation degree of PLDD dopant ion, and then the resistivity of the PLDD doped region of influence formation.In addition, also influential because peak temperature is higher to the diffusion of PLDD dopant ion, so the length of this peak position residence time also can influence the diffusion of PLDD dopant ion.
The peak position residence time depends on the speed that heats up and lower the temperature.Can make said Semiconductor substrate 100 quicken cooling through process for cooling, to reduce the peak value residence time to PLDD dopant ion diffusion influence.In the present embodiment, said peak temperature can be 900 ℃ to 1000 ℃, concrete, can be 950 ℃, the peak position residence time can be 1.75 seconds to 1.77 seconds.
After said Semiconductor substrate 100 is cooled to initial temperature, promptly form PLDD doped region 110 as shown in Figure 4.
In the above-mentioned method; After executing PLDD light dope technology, earlier the Semiconductor substrate temperature is increased to first temperature, and kept at least 1 second in first temperature; Said first temperature is less than or equal to 550 ℃; Then, said Semiconductor substrate is increased to peak temperature by first temperature, is cooled to initial temperature then; In the above-mentioned technology, the purpose that kept at least 1 second is whole semiconductor substrate surface temperature to be reached unanimity or more consistent; Be less than or equal to 550 ℃ of TED effects that can be used for suppressing dopant ion and said first temperature is set, thereby can improve the short-channel effect of the device of formation; Activate through the process that is increased to peak temperature and drops to initial temperature dopant ion PLDD; Above-mentioned method has only been adjusted the PLDD doping process temperature of annealing process afterwards; Just can suppress the TED effect of PLDD dopant ion, improve short-channel effect, improve the performance of the device that forms; And do not increase other extra processing step, make processing step oversimplify.
Need to prove; Description to some details in the above embodiments only is schematic; It should not limit the protection range of claim improperly, and those skilled in the art can make corresponding modification, deletion and replacement under the situation that does not break away from spirit of the present invention and essence.
In addition, the present invention also provides a kind of manufacturing approach of PMOS device.Fig. 5 is the flow chart of the manufacturing approach of PMOS device of the present invention.
Please refer to Fig. 5, step S200 provides Semiconductor substrate, on said Semiconductor substrate, has grid.
Step S210 carries out light dope technology to the area around the said grid, and the impurity that mixes is boron.
Step S220 carries out after the said light dope technology, said Semiconductor substrate temperature to the first temperature that raises, and keep said Semiconductor substrate in said first temperature at least 1 second; Wherein, said first temperature is less than or equal to 550 ℃.
Step S230 is increased to peak temperature with said Semiconductor substrate temperature by said first temperature.
Step S240 is cooled to initial temperature with said Semiconductor substrate by peak temperature.
Wherein, step S200 can repeat no more with reference to the embodiment of the formation method of above-mentioned PLDD doped region to step S240 here.
Step S250 is cooled to after the initial temperature, forms side wall layer at said gate lateral wall.Please refer to generalized section shown in Figure 6, form side wall layer 116 at grid 108a sidewall, wherein, said side wall layer 116 can be silica or silicon nitride or both combinations.
Please continue with reference to figure 5, step S260, the area around said side wall layer is carried out P type heavy doping technology, forms heavily doped region.
Please refer to Fig. 7, carry out heavy doping technology, in the Semiconductor substrate 100 around the said side wall layer 116, mix p type impurity, form heavily doped region 118.Wherein, the foreign ion that mixes can be a boron.
Please continue with reference to figure 5, step S270 carries out annealing process to the Semiconductor substrate that is formed with said heavily doped region, forms source region and drain region.
Wherein, described annealing process can be rapid thermal annealing, and is concrete, can the time spike rapid thermal annealing.
Said spike rapid thermal annealing can comprise the steps:
Said Semiconductor substrate 100 to second temperature that raise, and kept said second temperature at least 1 second; Wherein, said second temperature is less than or equal to 550 ℃, and is concrete, and said second temperature is 500 ℃.Keep said Semiconductor substrate 100 can be 10 seconds to 30 seconds in the time of said second temperature.
Then, said Semiconductor substrate 100 temperature are increased to second peak temperature by said second temperature.
Then, said Semiconductor substrate 100 is reduced to initial temperature by peak temperature.
In addition, this annealing process can be with reference to above-mentioned to the annealing process after the PLDD light dope, and changes technological parameter as required, is not described in detail here, and those skilled in the art can make corresponding change and replacement according to the instruction of the foregoing description.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (13)
1. the formation method of the LDD of a PMOS device is characterized in that, comprising:
Semiconductor substrate is provided, on said Semiconductor substrate, has grid, said Semiconductor substrate has initial temperature;
Area around the said grid is carried out light dope technology, and the impurity that mixes is boron;
Carry out after the said light dope technology, said Semiconductor substrate temperature to the first temperature that raises, and keep said Semiconductor substrate in said first temperature at least 1 second;
Said Semiconductor substrate temperature is increased to peak temperature by said first temperature;
Said Semiconductor substrate is cooled to initial temperature by peak temperature;
Wherein, said first temperature is less than or equal to 550 ℃.
2. the formation method of the LDD of PMOS device as claimed in claim 1 is characterized in that: said first temperature is 500 ℃.
3. the formation method of the LDD of PMOS device as claimed in claim 2 is characterized in that: keeping said Semiconductor substrate is 10 seconds to 30 seconds in the time of said first temperature.
4. the formation method of the LDD of PMOS device as claimed in claim 3 is characterized in that: keeping said Semiconductor substrate is 15 seconds in the time of said first temperature.
5. like claim 1 or 2 or the formation method of the LDD of 3 or 4 described PMOS devices, it is characterized in that: said Semiconductor substrate is increased to the programming rate of peak temperature greater than the programming rate that is increased to first temperature by initial temperature by first temperature.
6. like claim 1 or 2 or the formation method of the LDD of 3 or 4 described PMOS devices, it is characterized in that: said peak temperature is 900 ℃ to 1000 ℃.
7. the manufacturing approach of a PMOS device is characterized in that, comprising:
Semiconductor substrate is provided, on said Semiconductor substrate, has grid, said Semiconductor substrate has initial temperature;
Area around the said grid is carried out light dope technology, and the impurity that mixes is boron;
Carry out after the said light dope technology, said Semiconductor substrate temperature to the first temperature that raises, and keep said Semiconductor substrate in said first temperature at least 1 second;
Said Semiconductor substrate temperature is increased to peak temperature by said first temperature;
Said Semiconductor substrate is cooled to initial temperature by peak temperature;
Be cooled to after the initial temperature, form side wall layer at said gate lateral wall;
Area around said side wall layer is carried out P type heavy doping technology, forms heavily doped region;
Semiconductor substrate to being formed with said heavily doped region is carried out annealing process;
Wherein, said first temperature is less than or equal to 550 ℃.
8. the manufacturing approach of PMOS device as claimed in claim 7 is characterized in that, said annealing process is the spike rapid thermal annealing, comprises the steps:
Said Semiconductor substrate to the second temperature that raises, and kept said second temperature at least 1 second;
Said Semiconductor substrate temperature is increased to second peak temperature by said second temperature;
Said Semiconductor substrate is reduced to initial temperature by peak temperature; Wherein, said second temperature is less than or equal to 550 ℃.
9. the manufacturing approach of PMOS device as claimed in claim 8 is characterized in that: said second temperature is 500 ℃.
10. like the manufacturing approach of claim 8 or 9 described PMOS devices, it is characterized in that: keeping said Semiconductor substrate is 10 seconds to 30 seconds in the time of said second temperature.
11. the manufacturing approach like claim 7 or 8 or 9 described PMOS devices is characterized in that: said first temperature is 500 ℃.
12. the manufacturing approach like claim 7 or 8 or 9 described PMOS devices is characterized in that: keeping said Semiconductor substrate is 10 seconds to 30 seconds in the time of said first temperature.
13. the manufacturing approach like claim 7 or 8 or 9 described PMOS devices is characterized in that: keeping said Semiconductor substrate is 15 seconds in the time of said first temperature.
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| WO2005057663A2 (en) * | 2003-12-10 | 2005-06-23 | Koninklijke Philips Electronics N.V. | Method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices |
| CN101320692A (en) * | 2007-06-08 | 2008-12-10 | 联华电子股份有限公司 | Method for producing high pressure metal-oxide-semiconductor element |
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| WO2005057663A2 (en) * | 2003-12-10 | 2005-06-23 | Koninklijke Philips Electronics N.V. | Method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices |
| CN101320692A (en) * | 2007-06-08 | 2008-12-10 | 联华电子股份有限公司 | Method for producing high pressure metal-oxide-semiconductor element |
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