CN101762796A - Magnetic field detector - Google Patents
Magnetic field detector Download PDFInfo
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- CN101762796A CN101762796A CN200810044169A CN200810044169A CN101762796A CN 101762796 A CN101762796 A CN 101762796A CN 200810044169 A CN200810044169 A CN 200810044169A CN 200810044169 A CN200810044169 A CN 200810044169A CN 101762796 A CN101762796 A CN 101762796A
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Abstract
The invention discloses a magnetic field detector comprising a Hall disc which is used for detecting induced voltage generated by a magnetic field, the induced voltage is sent to a computing amplifier CPAI through a first-stage modulator, and then the amplified induced voltage is inputted to a low-pass filter LF1 through a second-stage modulator by the CPAI to eliminate the offset voltage influence of the CPAI and finally is inputted to a comparer COMP1 to be compared with the output voltage of a temperature and voltage self-compensating circuit so that the final output voltage is obtained. The invention not also increases the reliability of the circuit, but also lowers the complicate degree of the circuit and reduces the cost.
Description
Technical field
The present invention relates to the SIC (semiconductor integrated circuit) field, relate in particular to a kind of magnetic field detector.
Background technology
In modern industry, the field of using switch type magnetic field detecting device and linear magnetic field detecting device is more and more.Mainly be automotive electronics and consumer electronics field, various application scenarios have different requirements to the precision of magnetic field detector with reliability.
In the prior art, magnetic field detector has the following disadvantages: the first since the Primary Component that is used to detect magnetic field intensity suddenly the resistance of ear dish can be subjected to the influence of temperature and voltage, thereby the error of total system is strengthened.Second, high-end linear magnetic field detecting device can be in chip integrated very complicated multistage temperature-compensation circuit eliminate the temperature error of total system, complex circuit design can cause the cost of chip significantly to rise, thereby can only be applied on the platform of comparison costliness, has limited the scope of using.The 3rd: the fairly simple switch type magnetic field detecting device of circuit structure then seldom compensates for the consideration of chip cost, makes most switch type magnetic field detecting device can only be used on more less demanding low-grade platforms.
And, as shown in Figure 8, the circuit more complicated of Hall disc and offset voltage compensating circuit and first order modulator in the prior art.
The linear magnetic field detecting device is on the high side, and common switch type magnetic field detector performance is not fully up to expectations, and making much needs to use the industrial product of magnetic field detector to be difficult to choice, has influenced the expansion of magnetic field detector to more industrial circle.
Summary of the invention
Technical matters to be solved by this invention provides a kind of magnetic field detector, can reduce the influence that is subjected to temperature and voltage of Hall disc, reduces the error of total system, also can eliminate the temperature error of system simultaneously.
For solving the problems of the technologies described above, the technical scheme of magnetic field detector of the present invention is, comprise Hall disc, Hall disc detects the induced voltage of magnetic field generation and delivers among the operational amplifier CPA1 by first order modulator, induced voltage after CPA1 will amplify is eliminated the offset voltage influence of CPA1 by second level modulator and low-pass filter LF1, and obtain needing voltage relatively by the switched-capacitor circuit among the low-pass filter LF1, the output voltage that is input to comparator C OMP1 neutral temperature and voltage self-compensation circuit at last compares and obtains final output.
Be that described Hall disc is connected with the offset voltage compensating circuit as a further improvement on the present invention.
As another kind of further improvement of the present invention be, described temperature and voltage self-compensation circuit are made up of the divider resistance ladder, between VDD and GND, comprise R10, R20, R30, R40 successively, wherein R10 and R40 are the N trap resistance with the identical implantation concentration of Hall disc, R20 and R30 are polysilicon resistance, and resistance R 10 and R40 be close ear dish suddenly on domain, thereby make when carrying out that ion injects identically, and obtain and duplicate temperature of ear dish and voltage characteristic suddenly with the implantation concentration of Huo Erpan.
The output of temperature of the present invention and voltage self-compensation circuit can change along with the variation of temperature and voltage, thereby eliminated of the influence of the resistance of Hall disc HP1 with temperature and change in voltage, and utilizing increases electric capacity to operational amplifier CPA1 improvement phase compensation, increased the stability of CPA1, in addition, by second level modulator and low-pass filter LF1 are merged into one group of switching capacity voltage, thereby in the offset voltage of eliminating operational amplifier CPA1, obtain the input of COMP1, and, the present invention is by controlling first order modulator and make first order modulator to merge with ear dish offset voltage compensating circuit suddenly with controlling suddenly the clock of ear dish offset voltage compensating circuit, reduce the complexity of circuit, reduced cost.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is a magnetic field detector structural representation of the present invention;
Fig. 2 is Hall disc structural representation among the present invention; (what write originally is the end points connection diagram)
Fig. 3 is Hall disc and clock signal connection diagram among the present invention;
Fig. 4 is operational amplifier structural representation among the present invention;
Fig. 5 is temperature and voltage self-compensation circuit figure;
Fig. 6 is modulator and low-pass filter circuit figure among the present invention;
Fig. 7 is the sequential chart of each control signal among the present invention;
Fig. 8 is Hall disc in the prior art, offset voltage compensating circuit and first order modulator circuit figure;
Fig. 9 is the present invention control offset voltage compensating circuit clock control first order modulator circuit figure.
Reference numeral is that offset voltage compensating circuit module is 1 among the figure, and the Hall disc module is 2, and first order modulator is 3, and operational amplifier CPA1 is 4, and second level modulator is 5, and low-pass filter is 6, and comparator C OMP1 is 7, and temperature and voltage supplementary circuitry are 8.
Embodiment
As shown in Figure 1, magnetic field detector of the present invention comprises with the lower part:
As shown in Figure 2, in the present invention, Hall disc is a kind of N trap of special implantation concentration, and four ends of Hall disc replace in twos.And, as shown in Figure 3, the HPA end of described Hall disc meets VDD, meets VIN by clock control signal CK2 by clock control signal CK1, the HPB end of Hall disc meets VDD, meets VIP by clock control signal CK1 by clock control signal CK2, the HPC end of Hall disc meets GND, meets VIP by clock control signal CK2 by clock control signal CK1, the HPD end of Hall disc meets GND, meets VIN by clock control signal CK1 by clock control signal CK2, and the phase place of clock control signal CK1 and CK2 is opposite.
The phase place of clock control signal CK1 and CK2 is opposite.At CK1 constantly, HPA end and the HPC end of HP1 add VDD and GND, this moment, HPB end and HPD end induced Hall voltage, at CK2 constantly, HPB end and the HPD end of HP1 add VDD and GND, this moment, HPC end and HPA end induced Hall voltage, and alternately the mode of output can be with HP1 because the offset voltage that process deviation causes drops to minimum in twos by this four ends.
Also adopted improved phase compensating method among the present invention at operational amplifier CPA1, as shown in Figure 4, operational amplifier CPA1 comprises that two identical operational amplifier A MP1 and AMP2 amplify AINP and AINN respectively, the input termination AINP of operational amplifier A MP1, output terminal is VOP, 2 liang of resistance R terminate between the output terminal VOP and feedback end of operational amplifier A MP1, capacitor C 1 and resistance R 2 also are connected between operational amplifier A MP1 output terminal VOP and the feedback end, resistance R 1 one ends are connected with the feedback end of operational amplifier A MP1, the other end is connected with resistance R 1 ', resistance R 2 ' is connected with the other end of resistance R 1 ', the input termination AINN of operational amplifier A MP2, output terminal is VON, resistance R 2 ' is between its feedback end and output terminal VON, capacitor C 2 is connected with resistance R 2 ', is connected in parallel between the feedback end and output terminal of operational amplifier A MP2.
And, in the present invention, C1=C2=1pF, the gain of CPA1 is (R2+R1)/R1.Adopt two the same operational amplifier A MP1 and AMP2 respectively VINP and VINN to be amplified, C1 and C2 improve the building-out capacitor that the back adds, usually the building-out capacitor of operational amplifier can be added between the partial input and output of operational amplifier, can charge to building-out capacitor when but second level input and output voltage difference is big during owing to operational amplifier work, operational amplifier speed be reduced so excessive building-out capacitor can cause discharging and recharging overlong time.And two operational amplifier loads of another operational amplifier each other in work make the phase margin decline of operational amplifier cause circuit oscillation, the electric capacity that the present invention adds a 1pF at the output terminal and the feedback input end of each operational amplifier, so not only improved the phase margin of operational amplifier but also, also just can not influence the speed of operational amplifier owing to the very little problem that discharges and recharges that do not exist of electric capacity both end voltage difference.
In addition, the present invention also compensates the temperature and the voltage characteristic of Hall disc resistance by temperature and voltage compensating circuit.Generally, when magnetic field intensity during greater than working point (operating point, be called for short BOP), the output of chip will become low level by high level, when magnetic field intensity during less than release value BRP (releasepoint, be called for short BRP), magnetic field intensity will become high level from low level.As shown in Figure 5, temperature and voltage self-compensation circuit are exactly a divider resistance ladder that adopts dissimilar resistance to form, because Hall disc HP1 is the N trap of a special implantation concentration, so the resistance of Hall disc HP1 can change with the variation with temperature and VDD, spend when 125 spend from-40 when temperature, the resistance of Hall disc HP1 also has-30% to 50% variation.For example when temperature for-40 when spending, the resistance decreasing of Hall disc HP1, induced voltage increases, if this moment VL-VC and the value of VC-VH constant, the output of magnetic field intensity detecting device when also not reaching BOP and BRP will be overturn.With should high temperature the time, magnetic field intensity be greater than BOP and during less than BRP the output of detecting device just can overturn, so just caused two values of BOP and BRP accurate inadequately.In Fig. 5, R10 and R40 are N trap resistance, and R20 and R30 are polysilicon resistance.Among the present invention R10 and R40 changed into N trap resistance with the identical implantation concentration of Hall disc HP1, and on domain, make these two resistance as far as possible near Hall disc HP1, the resistance of R10 and R40 also can have the variation with HP1 resistance same ratio along with the variation of temperature and voltage like this, like this can be reduce during at high temperature so that the absolute value of VL-VC and VC-VH increases when low temperature, just offset the variation of the hall sensing voltage that the HP1 resistance variations causes, thus make the value of BOP and BRP become more stable accurately.In like manner, the influence that changes with VDD of HP1 resistance also can change with VDD with R10 and R40 and offsets.Promptly temperature during with change in voltage because the variation of the resistance value of R10 and R40 and the variation ratio of ear dish resistance value is identical suddenly, thereby the absolute value of VL-VC and VH-VC also produces variation in proportion, thereby balanced out the influence of temperature and change in voltage generation.
Shown in Fig. 6,7, in the present invention, modulator and low-pass filter LF1 merge into one group of switched-capacitor circuit, and this group switched-capacitor circuit can be finished the elimination of CPA1 offset voltage simultaneously and comparator C OMP1 is provided the function of input voltage.
The voltage that has added a VOS at the input end of CPA1 is represented the offset voltage voltage of CPA1, and the gain of establishing CPA1 is A, and COMP1 initially is output as low level, is the moment of high level at CP1, C3, and the quantity of electric charge Q3 on C4 and the C5 positive plate, Q4 and Q5 are respectively:
Q3＝A(VIP-VIN+VOS)C；Q4＝0；Q5＝2(VL-VC)C
When CP2 is high level, Q3, Q5 is constant, Q4 becomes A (VIP-VIN-VOS) C, this moment C3, the total charge dosage on C4 and the C5 is:
Q3+Q4+Q5=2A (VIP-VIN) C+2 (VL-VC) C formula (1)
By formula (1) as seen, just just can eliminate the offset voltage of CPA1 after the electric charge addition on three electric capacity.When the STRB signal was high level, though the voltage on the positive plate of three electric capacity has all become VX, because principle of charge conservation, total electric weight did not change, and can get:
(VX-VC) (C3+C4+C5)=4 (VX-VC) C=Q3+Q4+Q5 formula (2)
Can get by formula (2) and formula (1):
VX-VC=[A (VIP-VIN)+(VL-VC)]/2 formulas (3)
The principle of work of comparator C OMP1 is exactly that COMP1 is output as high level when VX-VC＞0, and when VX-VC＜0, COMP1 is output as low level.
A (VIP-VIN) is that process CPA1 amplifies the induced voltage after A times, because VL-VC is a negative value, so A (VIP-VIN) must greater than | VL-VC| just can make VX-VC＞0, also just can make the output of COMP1 become height, the output of magnetic field detector could be low by hypermutation, and this magnetic field intensity constantly is exactly BOP, with should magnetic field by by force to a little less than when reducing, the output that A (VIP-VIN) is less than magnetic field detector after this negative value of VC-VH could be uprised by low, and the magnetic field intensity of this moment is exactly BRP.As can be seen, switched-capacitor circuit is sampled to the output of CPA1 and the output of temperature and voltage self-compensation circuit respectively at CP1 and two moment of CP2, carries out the value that VX-VC is eliminated the offset voltage of CPA1 and obtain simultaneously in the electric charge computing constantly at STRB.
As shown in Figure 9, in the present invention with the clock control first order modulator of controlling the offset voltage compensating circuit.Because first order modulator 1 is mainly used to the output of HP1 is sampled, so the sampling clock CP1 of control first order modulator 1 and CP2 can replace with the clock CK1 and the CK2 of control offset voltage compensating circuit, thereby further one group of switch in the offset voltage compensating circuit and first order modulator 1 can be carried out multiplexingly, under the situation that does not influence the subsequent conditioning circuit sequential, reduce the complexity of circuit.
The present invention by the R10 in temperature and the voltage self-compensation circuit and R40 are used N trap resistance and on the domain and Hall disc HP1 as far as possible near after, R10, the temperature of R40 and HP1 is consistent basically with voltage characteristic, can produce good compensating action with the variation of temperature and voltage to HP1 resistance.In addition, two-stage modulator and low-pass filter also can well be eliminated the voltage imbalance of the CPM of operational amplifier.Building-out capacitor newly-increased among the CPA1 can make that also CPA1 has better phase margin and stability.
Claims (8)
1. magnetic field detector, it is characterized in that, comprise Hall disc, Hall disc detects the induced voltage of magnetic field generation and delivers among the operational amplifier CPA1 by first order modulator, induced voltage after CPA1 will amplify is eliminated the offset voltage influence of CPA1 by second level modulator and low-pass filter LF1, and obtain needing voltage relatively by the switched-capacitor circuit among the low-pass filter LF1, the output voltage that is input to comparator C OMP1 neutral temperature and voltage self-compensation circuit at last compares and obtains final output.
2. magnetic field detector according to claim 1 is characterized in that described Hall disc is connected with the offset voltage compensating circuit.
3. magnetic field detector according to claim 1, it is characterized in that, described temperature and voltage self-compensation circuit are made up of the divider resistance ladder, between VDD and GND, comprise R10, R20, R30, R40 successively, wherein R10 and R40 are the N trap resistance with the identical implantation concentration of Hall disc, R20 and R30 are polysilicon resistance, and resistance R 10 and R40 be close ear dish suddenly on domain, thereby make when carrying out that ion injects identically, and obtain and duplicate temperature of ear dish and voltage characteristic suddenly with the implantation concentration of Huo Erpan.
4. magnetic field detector according to claim 1 is characterized in that, four ends of described Hall disc replace in twos, is one group with HPA and HPC, and HPB and HPD are one group, and two groups replace.
5. magnetic field detector according to claim 4, it is characterized in that, the HPA end of described Hall disc meets VDD by clock control signal CK1, CK2 meets VIN by clock control signal, the HPB end of Hall disc meets VDD by clock control signal CK2, CK1 meets VIP by clock control signal, the HPC end of Hall disc meets GND by clock control signal CK1, CK2 meets VIP by clock control signal, the HPD end of Hall disc meets GND by clock control signal CK2, CK1 meets VIN by clock control signal, the phase place of clock control signal CK1 and CK2 is opposite, at CK1 is the high moment, HPA meets VDD, HPC meets GND, and HPB and HPD are as the output terminal of induced voltage; At CK2 is the high moment, and HPB meets VDD, and HPD meets GND, and HPA and HPC are as the output terminal of induced voltage.
6. magnetic field detector according to claim 1, it is characterized in that, operational amplifier CPA1 comprises that two identical operational amplifier A MP1 and AMP2 amplify AINP and AINN respectively, the input termination AINP of operational amplifier A MP1, output terminal is VOP, 2 liang of resistance R terminate between the output terminal VOP and feedback end of operational amplifier A MP1, capacitor C 1 and resistance R 2 also are connected between operational amplifier A MP1 output terminal VOP and the feedback end, resistance R 1 one ends are connected with the feedback end of operational amplifier A MP1, the other end is connected with resistance R 1 ', resistance R 2 ' is connected with the other end of resistance R 1 ', the input termination AINN of operational amplifier A MP2, output terminal is VON, resistance R 2 ' is between its feedback end and output terminal VON, capacitor C 2 is connected with resistance R 2 ', is connected in parallel between the feedback end and output terminal of operational amplifier A MP2.
7. magnetic field detector according to claim 1 is characterized in that, second level modulator and low-pass filter LF1 merge into one group of switched-capacitor circuit, and switched-capacitor circuit provides the input voltage of comparator C OMP1 when eliminating the CPA1 offset voltage.
8. magnetic field detector according to claim 2 is characterized in that, with the clock control first order modulator of control offset voltage compensating circuit.
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| CN 200810044169 CN101762796B (en) | 2008-12-24 | 2008-12-24 | Magnetic field detector |
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| CN102340299A (en) * | 2011-04-27 | 2012-02-01 | 灿瑞半导体(上海)有限公司 | Complementary metal oxide semiconductor (CMOS)-process-based Hall switch offset voltage elimination method and circuit |
| CN102997942A (en) * | 2011-09-16 | 2013-03-27 | 英飞凌科技股份有限公司 | Hall sensors having forced sensing nodes |
| US9018948B2 (en) | 2012-07-26 | 2015-04-28 | Infineon Technologies Ag | Hall sensors and sensing methods |
| US9164155B2 (en) | 2013-01-29 | 2015-10-20 | Infineon Technologies Ag | Systems and methods for offset reduction in sensor devices and systems |
| US9170307B2 (en) | 2012-09-26 | 2015-10-27 | Infineon Technologies Ag | Hall sensors and sensing methods |
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| CN113114120A (en) * | 2021-04-12 | 2021-07-13 | 上海传泰电子科技有限公司 | Hall sensor signal processing circuit |
| CN113274517A (en) * | 2021-05-19 | 2021-08-20 | 深圳瑞格泰科医疗科技有限公司 | Self-adaptive magnetic field intensity non-magnetic ultraviolet disinfection system |
| CN114073412A (en) * | 2020-07-31 | 2022-02-22 | 浙江绍兴苏泊尔生活电器有限公司 | Temperature detection circuit and method and cooking utensil |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2861581B2 (en) * | 1991-06-04 | 1999-02-24 | 日本鋼管株式会社 | Magnetic detection method and device |
| EP0793075B1 (en) * | 1996-03-02 | 2002-09-25 | Micronas GmbH | Monolithic integrated sensor circuit |
| EP1637898A1 (en) * | 2004-09-16 | 2006-03-22 | Liaisons Electroniques-Mecaniques Lem S.A. | Continuously calibrated magnetic field sensor |
| JP4901720B2 (en) * | 2005-02-08 | 2012-03-21 | ローム株式会社 | Magnetic sensor circuit and portable terminal having the magnetic sensor circuit |
-
2008
- 2008-12-24 CN CN 200810044169 patent/CN101762796B/en active Active
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| CN102340299B (en) * | 2011-04-27 | 2013-11-13 | 灿瑞半导体(上海)有限公司 | Complementary metal oxide semiconductor (CMOS)-process-based Hall switch offset voltage elimination method and circuit |
| CN102340299A (en) * | 2011-04-27 | 2012-02-01 | 灿瑞半导体(上海)有限公司 | Complementary metal oxide semiconductor (CMOS)-process-based Hall switch offset voltage elimination method and circuit |
| CN102997942A (en) * | 2011-09-16 | 2013-03-27 | 英飞凌科技股份有限公司 | Hall sensors having forced sensing nodes |
| US9024629B2 (en) | 2011-09-16 | 2015-05-05 | Infineon Technologies Ag | Hall sensors having forced sensing nodes |
| CN102997942B (en) * | 2011-09-16 | 2015-08-19 | 英飞凌科技股份有限公司 | There is the Hall element forcing sensing node |
| US9018948B2 (en) | 2012-07-26 | 2015-04-28 | Infineon Technologies Ag | Hall sensors and sensing methods |
| US9170307B2 (en) | 2012-09-26 | 2015-10-27 | Infineon Technologies Ag | Hall sensors and sensing methods |
| US9720050B2 (en) | 2013-01-29 | 2017-08-01 | Infineon Technologies Ag | Systems and methods for offset reduction in sensor devices and systems |
| US9164155B2 (en) | 2013-01-29 | 2015-10-20 | Infineon Technologies Ag | Systems and methods for offset reduction in sensor devices and systems |
| US9605983B2 (en) | 2014-06-09 | 2017-03-28 | Infineon Technologies Ag | Sensor device and sensor arrangement |
| US9891295B2 (en) | 2014-06-09 | 2018-02-13 | Infineon Technologies Ag | Sensor device and sensor arrangement |
| US9823168B2 (en) | 2014-06-27 | 2017-11-21 | Infineon Technologies Ag | Auto tire localization systems and methods utilizing a TPMS angular position index |
| CN106990370A (en) * | 2017-04-01 | 2017-07-28 | 张子仪 | A kind of isolated superconducting magnetic energy storage system quenches detection device |
| CN108519115A (en) * | 2018-03-14 | 2018-09-11 | 无锡思泰迪半导体有限公司 | A kind of offset voltage bearing calibration applied to hall device |
| CN108519115B (en) * | 2018-03-14 | 2020-09-15 | 无锡思泰迪半导体有限公司 | Offset voltage correction method applied to Hall device |
| CN114073412A (en) * | 2020-07-31 | 2022-02-22 | 浙江绍兴苏泊尔生活电器有限公司 | Temperature detection circuit and method and cooking utensil |
| CN114073412B (en) * | 2020-07-31 | 2023-05-09 | 浙江绍兴苏泊尔生活电器有限公司 | Temperature detection circuit and method and cooking utensil |
| CN113114120A (en) * | 2021-04-12 | 2021-07-13 | 上海传泰电子科技有限公司 | Hall sensor signal processing circuit |
| CN113274517A (en) * | 2021-05-19 | 2021-08-20 | 深圳瑞格泰科医疗科技有限公司 | Self-adaptive magnetic field intensity non-magnetic ultraviolet disinfection system |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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