CN101752455B - Manufacturing method of solar cell - Google Patents
Manufacturing method of solar cell Download PDFInfo
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- CN101752455B CN101752455B CN2008102046220A CN200810204622A CN101752455B CN 101752455 B CN101752455 B CN 101752455B CN 2008102046220 A CN2008102046220 A CN 2008102046220A CN 200810204622 A CN200810204622 A CN 200810204622A CN 101752455 B CN101752455 B CN 101752455B
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a manufacturing method of a solar cell, which comprises the following steps: depositing a polycrystalline silicon layer on a single crystal substrate; injecting hydrogen ions from one side of the polycrystalline silicon layer to the single crystal substrate and forming a cavity in the single crystal substrate; forming a P type polycrystalline silicon layer and an N type polycrystalline silicon layer contacted with each other through ion injection; forming a first electrode on the side of the single crystal substrate away from the polycrystalline silicon layer; thermally annealing the single crystal substrate and the polycrystalline silicon layer; stripping the single crystal substrate; and forming a second electrode structure on the side of the polycrystalline silicon layer which is stripped from the single crystal substrate and is away from the first electrode. Compared with the prior art, the PN junction of the solar cell in the invention can grow on the single crystal substrate. Due to the optimal matching of the lattice constant, the grain size in the grown polycrystalline silicon layer is large, thereby improving the performance of the solar cell. Moreover, the single crystal substrate can be stripped, thereby reducing the manufacturing cost.
Description
Technical field
The application relates to field of semiconductor manufacture, relates in particular to the manufacture method of solar cell.
Background technology
In view of the finiteness of conventional energy resource supply and the increase of environmental protection pressure, many in the world countries have started the upsurge of development and utilization new forms of energy.In new forms of energy, solar energy is a kind of cleaning, pollution-free, inexhaustible green energy resource, and countries in the world all take much count of and done a large amount of research to this, and in the energy world today in short supply day by day, solar energy has boundless development prospect.
The structure of existing solar battery cell as shown in Figure 1.Have lightly doped shallow diffusion region 102 on the Semiconductor substrate 100, and the groove 106 and 110 of the dark diffusion of the heavy doping that varies in size.Be formed with metal material 104 and 108 in the groove 106 and 110 respectively, as emitter electrode or bus (Bus-Bar).Thin metal material 108 is as emitter electrode, collects the PN junction place by electric current that photo-generated carrier produced; And thick metal material 104 is not only as emitter electrode, collects the PN junction place by the electric current that photo-generated carrier produced, also as the bus of the external output current of solar battery cell.
In the prior art, produce solar module and mainly adopt silicon materials, comprise monocrystalline silicon and polysilicon, can be used for absorbing the luminous energy of sunlight and be converted into electric energy as substrate.But along with the continuous expansion of semiconductor manufacturing industry, supply falls short of demand for the silicon substrate material on the market in recent years, and price climbs up and up.Therefore, the manufacture method of solar cell changes thin-film solar cells manufacture method at deposition on glass polysilicon substrate into by complete silicon substrate again.For example, Chinese invention patent disclose for No. 200610154424.9 a kind of on glass substrate depositing hydrogenized non-crystal silicon carbon alloy film make the method for solar cell.
But glass is noncrystal, discovers, because the reason of lattice constant match (lattice constant match) is difficult to form bigger polysilicon grain on non-silicon substrate, and forms the space at intercrystalline easily.This is unfavorable for improving Solar cell performance, for example the raising of solar energy converting efficient.Usually earlier on substrate, deposit the thin amorphous silicon layer of one deck with LPCVD, again this layer amorphous silicon layer is annealed, obtain bigger crystal grain, and then on this layer seed crystal the polysilicon membrane of deposition of thick.Its effect is come well less than direct deposit spathic silicon on monocrystalline substrate certainly.If utilize monocrystalline substrate and rotate back into, cost is too high again.Therefore, how can improve Solar cell performance, can reduce the difficult problem that manufacturing cost becomes industry again by increasing the polysilicon lattice dimensions.
Summary of the invention
Technical problem to be solved by this invention is how can improve Solar cell performance by increasing the polysilicon lattice dimensions, can reduce manufacturing cost again.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of solar cell, comprise step: deposit spathic silicon layer on single crystalline substrate; Carry out ion from polysilicon layer one side direction single crystalline substrate and inject, in described single crystalline substrate, form the cavity; Be infused in P type polysilicon layer and the N type polysilicon layer that formation is in contact with one another in the described polysilicon layer by ion; Form first electrode at described polysilicon layer on away from a side of described single crystalline substrate; Described single crystalline substrate and polysilicon layer are carried out thermal annealing; Peel off described single crystalline substrate; Form second electrode structure at the polysilicon layer of having peeled off single crystalline substrate on away from a side of described first electrode.
It is alternatively, described that to carry out the ion that ion injects from polysilicon layer one side direction single crystalline substrate be hydrogen ion and/or helium ion.
Alternatively, described thermal annealing carries out in the atmosphere of hydrogen.
Alternatively, the temperature of described thermal annealing is 300 ℃ to 900 ℃, and the thermal annealing time is 10 seconds to 60 minutes.
Alternatively, the temperature of described thermal annealing is 300 ℃ to 400 ℃, and the thermal annealing time is 30 seconds to 2 minutes.
Alternatively, described single crystalline substrate is a monocrystalline substrate.
Alternatively, described P type polysilicon layer contacts with single crystalline substrate.
Alternatively, the method for deposit spathic silicon layer is a physical vaporous deposition on single crystalline substrate.
Alternatively, the thickness of described polysilicon layer is 1 μ m to 10 μ m.
Alternatively, described cavity is 1nm to 100nm apart from single crystalline substrate and polysilicon layer interface.
Alternatively, injecting hydrionic energy is 800KeV to 8MeV, and dosage is 1E15/cm2 to 1E17/cm2.
Alternatively, forming the ion that P type polysilicon layer injected is boron ion or boron difluoride ion.
Alternatively, injecting boron ion or boron difluoride energy of ions is 100KeV to 1MeV, and dosage is 1E15/cm2 to 1E16/cm2.
Alternatively, forming the ion that n type polysilicon layer injected is arsenic ion or phosphonium ion.
Alternatively, the energy that injects arsenic ion or phosphonium ion is 400KeV to 2MeV, and dosage is 1E15/cm2 to 1E16/cm2.
Alternatively, described first electrode is the aluminium electrode.
Alternatively, the thickness of described first electrode is 20 μ m to 50 μ m.
Alternatively, also comprise step: remove residual monocrystalline silicon on the polysilicon layer.
Alternatively, form second electrode structure and specifically comprise step: described polysilicon layer away from a side of described first electrode on deposit passivation layer; Graphical described passivation layer forms groove; In passivation layer surface and described groove, form plating seed layer; Form the photoresist layer that exposes described groove; In described groove, electroplate second electrode material to filling up described groove at least; Remove the plating seed layer of photoresist layer and described passivation layer surface.
Alternatively, described second electrode material is a silver.
Compared with prior art, the polysilicon layer that the present invention will form the solar cell PN junction is grown on the single crystalline substrate by the method for physical vapor deposition (PVD), because lattice constant match is better, thereby crystallite dimension is bigger in the polysilicon layer that grows, can improve Solar cell performance, and single crystalline substrate can be peeled off, thereby can reduce manufacturing cost.
Description of drawings
The solar battery structure schematic diagram that Fig. 1 makes for prior art;
Fig. 2 makes the flow chart of solar cell for one embodiment of the invention;
Fig. 3 to Figure 13 is a schematic diagram of making solar cell according to flow process shown in Figure 2.
Embodiment
In embodiment, provide a kind of based single crystal substrate to make the method for polysilicon solar cell.In the method, the polysilicon layer of formation solar cell PN junction is grown on the single crystalline substrate by the method for physical vapor deposition (PVD), because lattice constant match is better, thereby crystallite dimension is bigger in the polysilicon layer that grows, and can improve Solar cell performance.Below will be elaborated to particular content of the present invention.
As shown in Figure 2, according to one embodiment of present invention, provide a kind of manufacture method of solar cell, comprise step:
S101, deposit spathic silicon layer on single crystalline substrate;
S102 injects hydrogen ion from polysilicon layer one side direction single crystalline substrate;
S103 forms P type and N type polysilicon layer in polysilicon layer;
S104 forms first electrode on polysilicon layer;
S105 carries out thermal annealing to single crystalline substrate and polysilicon layer;
S106 peels off single crystalline substrate;
S107, deposit passivation layer on polysilicon layer;
S108, graphical passivation layer forms groove;
S109 forms plating seed layer on the inwall of passivation layer surface and groove;
S110 forms the photoresist layer that exposes groove;
S111 electroplates second electrode material in groove;
S112, the plating seed layer of removal photoresist layer and described passivation layer surface forms second electrode structure.
Execution in step S101 at first, as shown in Figure 3, deposit spathic silicon layer 202 on single crystalline substrate 201.The material of the single crystalline substrate 201 here can be silicon, III-V family or II-VI compound semiconductor, because being widely used of monocrystalline substrate, output is big, price is lower, and the lattice constant match of monocrystalline silicon and polysilicon is better, thereby in one embodiment of the invention, preferably adopt monocrystalline silicon to form monocrystalline substrate 201.
The method of deposit spathic silicon layer 202 can be the method for PVD.Because compare the method for utilizing silane to form polysilicon layer, utilize the cost of PVD deposit spathic silicon layer 202 lower.
The pressure of deposit spathic silicon layer 202 is less than 100mTorr, form polysilicon layer 202 thickness preferably at 1 μ m to 10 μ m, such thickness can guarantee follow-uply can form enough thick P type and N type polysilicon layer, satisfies the PN junction of solar cell needs in order to formation.Under this sedimentary condition, because lattice constant match more, the crystallite dimension beguine of the polysilicon layer 202 of formation is bigger according to the crystallite dimension that prior art forms polysilicon layer, and then can improve Solar cell performance.
Execution in step S102 injects hydrogen ion from polysilicon layer 202 1 side direction single crystalline substrate 201 then, forms cavity 203 on the position at polysilicon layer 202 close polysilicon layers 202 and single crystalline substrate 201 interfaces, promptly forms structure as shown in Figure 4.
Injecting hydrionic energy is 800KeV to 8MeV, and the dosage of injection is 1E15/cm
2To 1E17/cm
2Such hydrogen ion injection technology can guarantee after the technology through subsequent thermal annealing, forms empty 203 on the position apart from single crystalline substrate 201 and the interface 1nm to 100nm of polysilicon layer 202 single crystalline substrate 201 in.
The purpose that forms cavity 203 is conveniently in the subsequent technique process single crystalline substrate 201 and polysilicon layer 202 to be peeled away.Those skilled in the art will know that, single crystalline substrate 201 is very frangible, step S102 forms a large amount of cavities 203 in single crystalline substrate 201, destroyed the internal structure of single crystalline substrate 201, make the structural strength that forms empty 203 places significantly reduce, thereby can guarantee under the single crystalline substrate 201 chip-proof situations, single crystalline substrate 201 and polysilicon layer 202 are peeled off.
In this embodiment, it is example to inject hydrogen ion only that the ion of step S102 injects, but the invention is not restricted to this.Because carry out the purpose of ion injection in step S102 is in order to destroy the internal crystal framework structure of single crystalline substrate 201, to form the cavity, being beneficial to the follow-up single crystalline substrate 201 of peeling off.So the ion that injects in step S102 also can be the less ion of other radiuses, for example helium ion.And the mode of injection also is not limited to inject separately hydrogen ion or helium ion etc., can adopt the mode of injecting of mixing, and for example mixes and injects hydrogen ion and helium ion.
Follow execution in step S103, as shown in Figure 5, the side near single crystalline substrate 201 in polysilicon layer 202 forms P type polysilicon layer 204, and the side away from single crystalline substrate 201 forms N type polysilicon layer 205 in polysilicon layer 202.
The technology that forms P type polysilicon layer 204 is: inject boron ion or boron difluoride ion from polysilicon layer 202 away from a side of single crystalline substrate 201, the injection energy is 100KeV to 1MeV, and implantation dosage is 1E15/cm
2To 1E16/cm
2The technology that forms N type polysilicon layer 205 is: inject arsenic ion or phosphonium ion from polysilicon layer 202 away from a side of single crystalline substrate 201, the injection energy is 400KeV to 2MeV, and implantation dosage is 1E15/cm
2To 1E16/cm
2According to above-mentioned injection technology, can in polysilicon layer 202, form the P type polysilicon layer 204 and the N type polysilicon layer 205 that are in contact with one another, promptly form the needed PN junction of solar cell.
Execution in step S104 then, as shown in Figure 6, in polysilicon layer 202 away from forming first electrode 206 on the surface of single crystalline substrate 201.The thickness of first electrode 206 can be 20 μ m to 50 μ m.The material that forms first electrode 206 is metal preferably, and more excellent selection is an aluminium in the metal, because the mechanical strength of aluminium is better and with low cost.
The step that forms first electrode 206 is placed on the follow-up step of peeling off single crystalline substrate 201 reason is arranged before.First electrode 206 except the effect of playing electrode, also has another effect here, promptly forms the support to polysilicon layer 202.As previously mentioned, the thickness of polysilicon layer 202 only has 1 μ m to 10 μ m, and follow-up step will be peeled off single crystalline substrate 201, and in stripping process, first electrode 206 just plays the support to polysilicon layer 202.
Execution in step S105 carried out thermal annealing 10 seconds to 60 minutes to single crystalline substrate 201 and polysilicon layer 202 then, and preferred annealing time is 30 seconds to 2 minutes.The temperature of thermal annealing is 300 ℃ to 900 ℃, and preferred annealing temperature is 300 ℃ to 400 ℃.Thermal annealing can carry out under the atmosphere of hydrogen.
Here carry out thermal annealing two purposes are arranged, the first is in order to strengthen the effect that aforementioned hydrogen ion injects, in single crystalline substrate 201, form hydrogen and cause the sheet defective, thereby can form microdischarge cavities (microcavity) layer in the single crystalline substrate 201, such microdischarge cavities layer helps follow-up the carrying out that peels off single crystalline substrate 201; Purpose two is the crystallite dimensions that increase polysilicon layer 202 for further, and carries out thermal annealing under the atmosphere of hydrogen, can realize increasing the purpose of crystallite dimension, thereby improve the photoelectric conversion efficiency of made solar cell.
Then execution in step S106 peels off single crystalline substrate 201.The process of peeling off single crystalline substrate 201 promptly applies the process of pulling force or shearing force to single crystalline substrate 201.As previously mentioned, hydrogen ion injects and makes single crystalline substrate 201 form a large amount of cavities 203, thereby destroyed the internal structure of single crystalline substrate 201, make the structural strength that forms empty 203 places significantly reduce, thereby can guarantee under the single crystalline substrate 201 chip-proof situations, single crystalline substrate 201 and polysilicon layer 202 are peeled off.
As shown in Figure 7, after single crystalline substrate 201 was stripped from, residual monocrystalline silicon 207 surfaces on polysilicon layer 202 can be very coarse, and this is beneficial for improving Solar cell performance, specifically will describe in subsequent process steps.
The single crystalline substrate 201 of being stripped from can be reused.Each repeated application, single crystalline substrate 201 are only lost hundreds of nanometers to several microns thickness, thereby repeated use that can be repeatedly, have significantly reduced the manufacturing cost of solar cell.And, because the rough surface that polysilicon layer 202 contacts with single crystalline substrate 201 is beneficial for improving Solar cell performance.Therefore, can save the step that the one side that single crystalline substrate 201 is stripped from is carried out smoothing processing at this, when forming polysilicon layer on single crystalline substrate 201 surfaces once more next time, because the rough surface of single crystalline substrate 201, the surface that the polysilicon layer of deposition contacts with single crystalline substrate 201 also can correspondingly become coarse, and this also is an advantage of the present invention.
After peeling off single crystalline substrate 201, the step of removing residual monocrystalline silicon 207 can also be arranged.Residual monocrystalline silicon 207 can be removed with the method for plasma etching.Because residual monocrystalline silicon 207 surfaces are very coarse, therefore in the process of residual monocrystalline silicon 207 being removed fully with plasma, the surface etch of polysilicon layer 202 will inevitably be got very coarse.As previously mentioned, this is beneficial for improving Solar cell performance, thereby has saved specially the step with the surface roughening of polysilicon layer 202.Therefore, this also is an advantage of the present invention.
Execution in step S107 then, as shown in Figure 8, by thermal oxidation deposit passivation layer 208 on polysilicon layer 202.The thickness of the passivation layer 208 that deposition forms can be 100nm to 300nm.The material that forms passivation layer can be a silicon nitride.Make the silicon dangling bonds saturated by thermal oxidation, the recombination velocity at Si-SiO2 interface is descended greatly, its passivation effect depends on surface concentration, interface state density and the electronics of emitter region, the floating section in hole.And annealing can make passivation effect more obvious in nitrogen atmosphere.Adopt PECVD deposit silicon nitride effect better, because in the process of film forming, have the effect of hydrogenation.The passivation layer 208 that this external application silicon nitride forms also plays anti-reflective film.
Follow execution in step S108, as shown in Figure 9, graphical passivation layer 208 forms groove 209.Here the groove of Xing Chenging will become the basis of filling second electrode 212 (with reference to Figure 12) at subsequent step.The degree of depth of groove 209 needs to expose at least fully P type polysilicon layer 204.That is to say that the bottom of groove 209 is wanted fully in " embedding " P type polysilicon layer 204, to realize effective connection of second electrode and P type polysilicon layer 204.
Then execution in step S109 as shown in figure 10, forms plating seed layer 210 in passivation layer 208 surfaces and groove 209.The inwall and the bottom of plating seed layer 201 covering groove 209 in groove 209.The method that forms plating seed layer 210 can be sputtered titanium tungsten alloy and/or silver.The concrete technological parameter that forms plating seed layer 210 is well known to those skilled in the art, does not repeat them here.
Execution in step S110 as shown in figure 11, forms the photoresist layer 211 that exposes groove 209 then.The method that forms the photoresist layer 211 that exposes groove 209 can be that first spin coating photoresist is being left through hole by the method for photoetching on the photoresist layer 211 again on the position of groove 209 correspondences, thereby exposes groove 209.The reason that forms the photoresist layer 211 that exposes groove 209 is to stop the plating seed layer 210 on passivation layer 208 surfaces and contacting of electroplate liquid, prevents to form second electrode 212 at the plating seed layer 210 on passivation layer 208 surfaces.
Then execution in step S111 as shown in figure 12, electroplates in groove 209 and forms second electrode 212.Therefore electroplate second electrode 212 and need fill up groove 209 at least, after follow-up removal photoresist layer 211, an end of second electrode 212 can be higher than passivation layer 208, could form like this and node that external circuit is interconnected.Owing to have photoresist layer 211 to cover on the plating seed layer 210 on passivation layer 208 surfaces, therefore electroplate 212 at second electrode that forms and to be formed in the groove 209.The material that forms second electrode 212 is preferably silver-colored, and its reason is that the contact resistance of silver is little.
Last execution in step S112 as shown in figure 13, removes the plating seed layer 210 on photoresist layer 211 and passivation layer 208 surfaces.Like this, just on P type polysilicon layer 204, formed second electrode structure of being formed by passivation layer 208, plating seed layer 210 and second electrode 212.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (19)
1. the manufacture method of a solar cell is characterized in that, comprises step:
Deposit spathic silicon layer on single crystalline substrate;
Carry out ion from polysilicon layer one side direction single crystalline substrate and inject, in described single crystalline substrate, form the cavity;
Be infused in P type polysilicon layer and the N type polysilicon layer that formation is in contact with one another in the described polysilicon layer by ion;
Form first electrode at described polysilicon layer on away from a side of described single crystalline substrate;
Described single crystalline substrate and polysilicon layer are carried out thermal annealing;
Peel off described single crystalline substrate;
Remove residual single crystalline substrate material on the polysilicon layer by plasma etching, make the polysilicon layer surface roughening;
Form second electrode structure at the polysilicon layer of having peeled off single crystalline substrate on away from a side of described first electrode.
2. the manufacture method of solar cell as claimed in claim 1 is characterized in that: described to carry out the ion that ion injects from polysilicon layer one side direction single crystalline substrate be hydrogen ion and/or helium ion.
3. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: described thermal annealing carries out in the atmosphere of hydrogen.
4. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: the temperature of described thermal annealing is 300 ℃ to 900 ℃, the thermal annealing time is 10 seconds to 60 minutes.
5. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: the temperature of described thermal annealing is 300 ℃ to 400 ℃, the thermal annealing time is 30 seconds to 2 minutes.
6. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: described single crystalline substrate is a monocrystalline substrate.
7. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: described P type polysilicon layer contacts with single crystalline substrate.
8. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: the method for deposit spathic silicon layer is a physical vaporous deposition on single crystalline substrate.
9. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: the thickness of described polysilicon layer is 1 μ m to 10 μ m.
10. the manufacture method of solar cell as claimed in claim 1, it is characterized in that: described cavity is 1nm to 100nm apart from single crystalline substrate and polysilicon layer interface.
11. the manufacture method of solar cell as claimed in claim 1 is characterized in that: described to carry out the ion that ion injects from polysilicon layer one side direction single crystalline substrate be hydrogen ion, and injecting hydrionic energy is 800KeV to 8MeV, and dosage is 1E15/cm
2To 1E17/cm
2
12. the manufacture method of solar cell as claimed in claim 1 is characterized in that: the ion that formation P type polysilicon layer is injected is boron ion or boron difluoride ion.
13. the manufacture method of solar cell as claimed in claim 12 is characterized in that: injecting boron ion or boron difluoride energy of ions is 100KeV to 1MeV, and dosage is 1E15/cm
2To 1E16/cm
2
14. the manufacture method of solar cell as claimed in claim 1 is characterized in that: the ion that formation n type polysilicon layer is injected is arsenic ion or phosphonium ion.
15. the manufacture method of solar cell as claimed in claim 14 is characterized in that: the energy that injects arsenic ion or phosphonium ion is 400KeV to 2MeV, and dosage is 1E15/cm
2To 1E16/cm
2
16. the manufacture method of solar cell as claimed in claim 1 is characterized in that: described first electrode is the aluminium electrode.
17. the manufacture method of solar cell as claimed in claim 1 is characterized in that: the thickness of described first electrode is 20 μ m to 50 μ m.
18. the manufacture method of solar cell as claimed in claim 1 is characterized in that, forms second electrode structure and specifically comprises step:
Described polysilicon layer away from a side of described first electrode on deposit passivation layer;
Graphical described passivation layer forms groove;
In passivation layer surface and described groove, form plating seed layer;
Form the photoresist layer that exposes described groove;
In described groove, electroplate second electrode material to filling up described groove at least;
Remove the plating seed layer of photoresist layer and described passivation layer surface.
19. the manufacture method of solar cell as claimed in claim 18 is characterized in that: described second electrode material is silver.
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| CN102376819A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Forming method of solar battery |
| CN102339898A (en) * | 2010-12-29 | 2012-02-01 | 宜兴市昱元能源装备技术开发有限公司 | Process for manufacturing p-n junction of large-area silicon-based solar cell by ion implantation method |
| KR101396444B1 (en) * | 2013-05-06 | 2014-05-22 | 한화케미칼 주식회사 | Method of preparing front electrode of solar cell and solar cell using the same |
| CN107464855A (en) * | 2016-06-02 | 2017-12-12 | 上海神舟新能源发展有限公司 | Silica-based solar cell N-type surface tunnel oxide passivation contact for producing method |
| CN107482078A (en) * | 2016-06-02 | 2017-12-15 | 上海神舟新能源发展有限公司 | Silica-based solar cell p-type surface tunnel oxide passivation contact for producing method |
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