CN101752379B

CN101752379B - Storage electrode structure of stack capacitor and manufacturing method thereof

Info

Publication number: CN101752379B
Application number: CN 200810185348
Authority: CN
Inventors: 吴晓婷
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2008-12-22
Filing date: 2008-12-22
Publication date: 2013-03-06
Anticipated expiration: 2028-12-22
Also published as: CN101752379A

Abstract

The invention discloses a storage electrode structure of a stack capacitor and a manufacturing method thereof. The storage electrode structure of a stack capacitor comprises a substrate on which a conductive region is arranged, an etch stop layer covering the conductive region, a conductive layer passing through the etch stop layer and electrically connected with the conductive region, an annular conductive clearance wall arranged on the sidewall of the conductive layer, and a storage electrode upper part stacked and arranged on a storage electrode pillar, wherein the conductive clearance wall is arranged on the etch stop layer, and the conductive layer and the conductive clearance wall form the storage electrode pillar.

Description

Storage electrode structure of stack capacitor and preparation method thereof

Technical field

The present invention relates to a kind of semiconductor memery device, particularly relate to storage electrode structure of a kind of stack capacitor and preparation method thereof.

Background technology

In recent years, cooperate the trend of various miniaturization of electronic products, the design of dynamic random access memory is also towards high integration and high-density development.Because each memory cell arrangement of high-density DRAM element is very close, thus almost can't increase in the horizontal capacity area, and certainly will on vertical direction, increase the height of electric capacity, increase thus capacity area and capacitance.

The manufacture method of the storage electrode of the known stack capacitor of Fig. 1 to Fig. 5 illustration (storage node).As shown in Figure 1, provide substrate 10, for example silicon base which is provided with conductive region 12a and 12b.In substrate 10, sequentially be formed with dielectric layer 14, for example silicon nitride layer, and dielectric layer 16, for example undoped silicon glass (undoped silicate glass, USG) layer.

As shown in Figure 2, then utilize photoetching process and dry etching process, in dielectric layer 14 and dielectric layer 16, etch hole 18a and the 18b of high-aspect-ratio (high aspect ratio).Cleaning procedure be can carry out subsequently,

hole

18a and 18b inside were gone up and remained in substrate that previous dry ecthing remains in 10 surfaces etch byproducts or contaminate particulate removed.

As shown in Figure 3, then utilize chemical vapour deposition (CVD) (chemical vapor deposition, CVD) technique, conformably on dielectric layer 16 surfaces and

hole

18a and 18b inwall deposition silicon layer 22, for example doped polycrystalline silicon.

As shown in Figure 4, utilize subsequently flatening process, for example chemico-mechanical polishing (chemicalmechanical polishing, CMP) technique, optionally will before be deposited on dielectric layer 16 lip-deep silicon layers 22 and grind removal, only stay the silicon layer 22 that is deposited on hole 18a and the 18b inwall.

Next, as shown in Figure 5, utilize wet etch process, for example use hydrofluoric acid (HF) and ammonium fluoride (NH ₄F) mixed liquor or other buffer-type oxide layer etching solutions (BOE) are got rid of dielectric layer 16, so form storage electrode structure 30a and 30b.The rough degree of depth that equals

hole

18a and 18b of the height H of storage electrode structure 30a and 30b, it is about about 1.6 microns to 1.7 microns usually.

When the shortcoming of above-mentioned Prior Art is included in the hole 18a of etching high-aspect-ratio and 18b, can't produce more straight side profile.In addition, because etched characteristic makes so, the hole 18a of high-aspect-ratio and 18b be downward convergent normally, cause at last the bottom critical size A of

hole

18a and 18b too small, this forms so-called storage electrode bridge joint (storage node bridging) phenomenon so that storage electrode structure 30a and 30b collapse easily in follow-up cleaning or drying process.

Summary of the invention

Main purpose of the present invention can effectively avoid storage electrode bridge joint phenomenon to occur at the storage electrode structure of the stack capacitor that a kind of improvement is provided.

Another object of the present invention is in the manufacture method of the storage electrode that a kind of stack capacitor is provided, with deficiency and the shortcoming that solves aforementioned Prior Art.

For reaching aforementioned purpose, the invention provides a kind of method of making the storage electrode of stack capacitor, including provides substrate, which is provided with conductive region, and etching stopping layer covers this conductive region, and the first dielectric layer, covers this etching stopping layer; In this etching stopping layer and this first dielectric layer, etch the first hole, expose this conductive region; In this first hole, form the first conductive layer, be electrically connected with this conductive region; Remove this first dielectric layer; Sidewall at this first conductive layer forms annular conductive gap wall, and wherein this conductive gap wall and this first conductive layer consist of the storage electrode pilum; At this substrate deposition the second dielectric layer; In this second dielectric layer, etch the second hole, expose this storage electrode pilum; Form the second conductive layer at this second hole inwall; And remove this second dielectric layer.

According to the preferred embodiment of the present invention, the invention provides a kind of storage electrode structure, include substrate, which is provided with conductive region; Etching stopping layer covers this conductive region; The first conductive layer passes this etching stopping layer, and is electrically connected with this conductive region; The conductive gap wall of annular is located on this first conductive layer sidewall, and wherein this conductive gap wall is positioned on this etching stopping layer, and this first conductive layer and this conductive gap wall formation storage electrode pilum; And columnar storage electrode top, be stacked on this storage electrode pilum.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred implementation cited below particularly, and cooperation institute accompanying drawing are described in detail below.Yet following preferred implementation and accompanying drawing are only for reference and the usefulness of explanation, and the present invention is limited.

Description of drawings

The manufacture method of the storage electrode of Fig. 1,2,3, the 4 and 5 known stack capacitors of illustration.

What Fig. 6,7,8,9,10,11,12,13 and 14 illustrated is the generalized section that the preferred embodiment of the present invention is made the storage electrode of stack capacitor.

Description of reference numerals

10:

substrate

12a, 12b: conductive region

14: dielectric layer 16: dielectric layer

18a, 18b: hole 22: silicon layer

30a, 30b: storage electrode structure 100: substrate

112a, 112b: conductive region 114: dielectric layer

122:

dielectric layer

128a, 128b: hole

130a, 130b: silicon layer 140: conductive layer

142a, 142b:

conductive gap wall

150a, 150b: storage electrode pilum

152: dielectric layer 162: dielectric layer

168a, 168b: hole 170: metal level

172a, 172b:

storage electrode top

180a, 180b: storage electrode

Embodiment

See also Fig. 6 to 14, what it illustrated is the generalized section that the preferred embodiment of the present invention is made the storage electrode of stack capacitor.As shown in Figure 6, provide substrate 100, for example silicon base which is provided with conductive region 112a and 112b.Sequentially be formed with dielectric layer 114 in substrate 100, for example silicon nitride layer is used as etching stopping layer, and dielectric layer 122, for example undoped silicon glass (USG) layer or Pyrex (BSG) layer.According to a preferred embodiment of the invention, the thickness of dielectric layer 122 is approximately between 0.6 μ m to 0.8 μ m.

As shown in Figure 7, then utilize photoetching process and dry etching process,

etch hole

128a and 128b in dielectric layer 114 and dielectric layer 122, it exposes respectively the upper surface of conductive region 112a and 112b.Cleaning procedure be can carry out subsequently,

hole

128a and 128b inside were gone up and remained in substrate that previous dry ecthing remains in 100 surfaces etch byproducts or contaminate particulate removed.Because dielectric layer 122 is not thick, therefore aforementioned dry etching process can become the sidewall etch of

hole

128a and 128b the profile of near vertical.

As shown in Figure 8, then carry out chemical vapour deposition (CVD) (CVD) technique and chemico-mechanical polishing (CMP) technique, in

hole

128a and 128b, form respectively

silicon layer

130a and 130b, doped polycrystalline silicon for example, and

silicon layer

130a and 130b are electrically connected with conductive region 112a and the 112b of below respectively.

As shown in Figure 9, then utilize etching mode, for example dry ecthing mode is removed dielectric layer 122 fully, exposes the sidewall of silicon layer 130a and 130b.Subsequently, depositing conducting layer 140 conformably on the upper surface of dielectric layer 114 surfaces and

silicon layer

130a and 130b and sidewall, for example, metal.According to a preferred embodiment of the invention, conductive layer 140 is the metallic alloy good with the silicon nitride property followed particularly, for example TiN or Ti/TiN.

As shown in figure 10, then carry out dry etching process, anisotropically etching conductive layer 140, form respectively conductive gap wall 142a and the 142b of annular at the sidewall of

silicon layer

130a and 130b, wherein, according to a preferred embodiment of the invention, conductive gap wall 142a and silicon layer 130a consist of storage electrode pilum (storage node pedestal) 150a, and conductive gap wall 142b and silicon layer 130b consist of storage electrode pilum 150b.The height of

storage electrode pilum

150a and 150b is approximately between 0.6 μ m to 0.8 μ m.

As shown in figure 11, carry out chemical vapor deposition method, comprehensive ground dielectric layer 152 in substrate 100, for example, undoped silicon glass (USG) layer or Pyrex (BSG) layer.Then utilize CMP (Chemical Mechanical Polishing) process, planarization dielectric layer 152, and expose

storage electrode pilum

150a and 150b partly.At this moment, remaining dielectric layer 152 fills up the gap between storage electrode pilum 150a and the 150b.Certainly, in other embodiments of the invention, be used for the CMP (Chemical Mechanical Polishing) process of planarization dielectric layer 152 also can omit, perhaps replace with other feasible flattening methods in addition.

As shown in figure 12, next, carry out chemical vapor deposition method, comprehensive ground dielectric layer 162 in substrate 100, for example, undoped silicon glass (USG) layer or Pyrex (BSG) layer.According to a preferred embodiment of the invention, the thickness of dielectric layer 162 is approximately between 0.6 μ m to 0.8 μ m.

As shown in figure 13, utilize photoetching process and dry etching process,

etch hole

168a and 168b in dielectric layer 162, it exposes respectively the upper surface of storage electrode pilum 150a and 150b.Cleaning procedure be can carry out subsequently,

hole

168a and 168b inside were gone up and remained in substrate that previous dry ecthing remains in 100 surfaces etch byproducts or contaminate particulate removed.Equally, because dielectric layer 162 is not thick, therefore aforementioned dry etching process can become the sidewall etch of

hole

168a and 168b the profile of near vertical.Then, depositing metal layers 170 conformably on dielectric layer 162 surfaces and

hole

168a and 168b inwall, for example, TiN, TaN.

As shown in figure 14, next, utilize CMP (Chemical Mechanical Polishing) process, get rid of the metal level 170 that is positioned at directly over the dielectric layer 162, expose thus dielectric layer 162, form columnar

storage electrode top

172a and 172b, height is between 0.6 μ m to 0.8 μ m.Then, utilize etching mode, for example the wet etching mode is removed

dielectric layer

162 and 152 fully, again exposes the sidewall of storage electrode pilum 150a and 150b.At this moment, storage electrode top 172a and storage electrode pilum 150a consist of storage electrode 180a, and storage electrode top 172b and storage electrode pilum 150b consist of storage electrode 180b.

The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.

Claims

1. the storage electrode structure of a stack capacitor is characterised in that to include:

Substrate which is provided with conductive region;

Etching stopping layer covers this conductive region;

Conductive layer passes this etching stopping layer, and directly is electrically connected with this conductive region;

The conductive gap wall of annular is located on this conductive layer sidewall and this etching stopping layer, and wherein this conductive layer and this conductive gap wall formation storage electrode pilum protrudes from this etching stopping layer; And

Storage electrode top is stacked on this storage electrode pilum.

2. the storage electrode structure of stack capacitor as claimed in claim 1 is characterized in that the height of this storage electrode pilum is between 0.6 μ m to 0.8 μ m.

3. the storage electrode structure of stack capacitor as claimed in claim 1 is characterized in that this conductive gap wall is made of metal.

4. the storage electrode structure of stack capacitor as claimed in claim 1 is characterized in that this storage electrode top is made of metal.

5. method of making the storage electrode of stack capacitor is characterised in that to include:

Provide substrate, the first dielectric layer which is provided with conductive region, covers the etching stopping layer of this substrate and this conductive region and cover this etching stopping layer;

In this etching stopping layer and this first dielectric layer, etch the first hole, expose this conductive region;

In this first hole, form the first conductive layer;

Remove this first dielectric layer;

Again this second conductive layer is carried out anisotropic etching to form the conductive gap wall of annular at the sidewall of this first conductive layer after conformably depositing the second conductive layer on the sidewall of this first conductive layer, wherein this conductive gap wall and this first conductive layer consist of the storage electrode pilum;

On this substrate and this storage electrode pilum, cover the second dielectric layer, carry out again glossing and expose this storage electrode pilum;

At this second dielectric layer and this storage electrode pilum deposition the 3rd dielectric layer, in the 3rd dielectric layer, etch the second hole, expose this storage electrode pilum of part;

Depositing metal layers conformably on the 3rd dielectric layer surface and this second hole inwall;

Removal is positioned at this metal level directly over the 3rd dielectric layer to form storage electrode top; And

Remove this second dielectric layer and the 3rd dielectric layer.

6. the method for the storage electrode of making stack capacitor as claimed in claim 5 is characterized in that this first conductive layer fills up this first hole, and is electrically connected with this conductive region.

7. the method for the storage electrode of making stack capacitor as claimed in claim 5 is characterized in that this annular conductive gap wall is formed on this etching stopping layer.

8. the method for the storage electrode of making stack capacitor as claimed in claim 5 is characterized in that the thickness of this first dielectric layer is between 0.6 μ m to 0.8 μ m.