CN101752328A - 半芯片封装结构及其制造方法 - Google Patents

半芯片封装结构及其制造方法 Download PDF

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Publication number
CN101752328A
CN101752328A CN200810185205A CN200810185205A CN101752328A CN 101752328 A CN101752328 A CN 101752328A CN 200810185205 A CN200810185205 A CN 200810185205A CN 200810185205 A CN200810185205 A CN 200810185205A CN 101752328 A CN101752328 A CN 101752328A
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China
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chip
heat
buffer layer
packaging structure
conducting buffer
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CN200810185205A
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Inventor
谢瑞青
张平
陈重德
潘力齐
王郁仁
王钦宏
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Priority to CN200810185205A priority Critical patent/CN101752328A/zh
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Abstract

一种芯片封装结构及其制造方法。芯片封装结构包括散热基板、芯片及异质接合导热缓冲层。芯片配置于散热基板上。异质接合导热缓冲层配置于散热基板与芯片之间。异质接合导热缓冲层包括多个垂直于散热基板配置的柱状体，且各柱状体的深宽比介于约3∶1到50∶1之间。

Description

半芯片封装结构及其制造方法
技术领域
本发明涉及一种半导体封装结构及其制造方法，且特别是涉及一种散热性佳且可吸收剪应力的芯片封装结构及其制造方法。
背景技术
在开源节流和发展无污染新能源工业技术的考量与需求下，可再生能源逐渐受到重视，尤其以太阳能电池最受瞩目。一般而言，III-V族太阳能电池芯片具有较高的光电转换效率，但其芯片成本甚高，因此通常会搭配大面积的聚光系统，以提高聚光倍率至千倍以上，然而，此种系统必须先解决散热的问题。另外，高功率光电二极管(LED)芯片也是日前常用的光电转换芯片之一，不过其同样也有散热不佳的问题。
在封装过程中，芯片通常是配置在基板上，且多以导热胶或锡球作为芯片与基板的接合介质。导热胶通常为树脂类，热传导系数较低，散热效果差。锡球的接合方式虽然成本低且容易制作，但接合介面的膨胀系数不同，系统操作时温度反复变化造成的疲劳效应，是形成芯片接合点破坏的主因。疲劳破坏可以分为机械式疲劳破坏或热疲劳破坏。机械式疲劳破坏乃因不断的形变与做动，造成机械强度的降低。热疲劳破坏则是因为两界面之间的热膨胀系数匹配不佳，造成高温及低温时产生微小形变而互相拉扯，长期影响下容易产生界面剥离的现象。如此一来，芯片和其下的基板都会受损，进而导致芯片封装结构的效能及可靠度的降低。另外，也有将芯片与次粘着基板(submount)相互接合等方式，芯片与次粘着基板的热膨胀系数相近，不过次粘着基板通常为陶瓷材料，例如Al2O3、AlN等，热传递过程必须包含次粘着基板，且存在有热传导系数较低与价格较高等问题。
发明内容
本发明提供一种芯片封装结构，其散热性佳，且可吸收剪应力，避免系统因温度变化造成的机械式疲劳破坏或热疲劳破坏。
本发明提供一种芯片封装结构的制造方法，利用微机电电铸技术制造上述的芯片封装结构，可提升芯片封装结构的效能及可靠度。
本发明提出一种芯片封装结构，包括散热基板、芯片及异质接合导热缓冲层。芯片配置于散热基板上。异质接合导热缓冲层配置于散热基板与芯片之间。异质接合导热缓冲层包括多个垂直于散热基板配置的柱状体，且各柱状体的深宽比介于约3∶1到50∶1之间。
在本发明的实施例中，上述的异质接合导热缓冲层的材料包括锡或铜。
在本发明的实施例中，上述的异质接合导热缓冲层的柱状体的截面包括圆形、方形、三角形或菱形。
在本发明的实施例中，上述的异质接合导热缓冲层的柱状体呈阵列分布。
在本发明的实施例中，上述的异质接合导热缓冲层的高度约为长度或宽度的1/5～1/10。
在本发明的实施例中，上述的异质接合导热缓冲层还包括连接层，连接柱状体的顶部。
在本发明的实施例中，上述的芯片封装结构还包括接合层，配置在芯片与异质接合导热缓冲层之间。
在本发明的实施例中，上述的接合层的材料和异质接合导热缓冲层的材料相同。
在本发明的实施例中，上述的接合层的材料和异质接合导热缓冲层的材料不同。
在本发明的实施例中，上述的接合层的材料包括锡、铜、金、银或金锡合金。
在本发明的实施例中，上述的芯片封装结构还包括填充物，配置在异质接合导热缓冲层的柱状体之间。
在本发明的实施例中，上述的填充物的材料包括金属粉粒材料或高分子材料。
在本发明的实施例中，上述的芯片包括太阳能电池芯片、发光二极管芯片或其他异质接合。
本发明又提出一种芯片封装结构的制造方法。首先，提供散热基板。接着，在散热基板上形成异质接合导热缓冲层，其中异质接合导热缓冲层包括垂直于散热基板配置的多个柱状体。然后，在异质接合导热缓冲层上接合芯片。
在本发明的又一实施例中，上述形成异质接合导热缓冲层的方法例如利用微机电电铸(electroforming)技术或纳米技术。
在本发明的又一实施例中，上述利用微机电电铸技术形成异质接合导热缓冲层的步骤，包括在散热基板上先形成金属种子层或者可略过这个步骤，再形成一层光致抗蚀剂层，其中光致抗蚀剂层具有多个开口，且各开口的深宽比介于约3∶1到50∶1之间。接着，对金属种子层进行第一次电铸工艺，以于光致抗蚀剂层的开口中形成柱状体。之后，移除光致抗蚀剂层，以形成异质接合导热缓冲层。
在本发明的又一实施例中，还可以对异质接合导热缓冲层进行第二次电镀工艺，以加粗异质接合导热缓冲层的各柱状体。
在本发明的又一实施例中，对上述的金属种子层进行第一次电镀工艺时，可选择增加电铸时间，使柱状体持续往光致抗蚀剂层的开口外生长，而在光致抗蚀剂层上形成连接柱状体的顶部的连接层。
在本发明的又一实施例中，上述的异质接合导热缓冲层的材料包括锡或铜。
在本发明的又一实施例中，上述的芯片包括太阳能电池芯片、发光二极管芯片或其他异质接合。
在本发明的又一实施例中，在上述的异质接合导热缓冲层上接合芯片之前，还包括于芯片的接合面上形成接合层。
在本发明的又一实施例中，上述的形成接合层的方法包括电镀。
在本发明的又一实施例中，上述的接合层的材料包括锡、铜、金、银或金锡合金。
在本发明的又一实施例中，在上述的异质接合导热缓冲层上接合芯片之前，还包括于异质接合导热缓冲层的柱状体之间形成填充物。
在本发明的又一实施例中，上述的填充物的材料包括金属粉粒材料或高分子材料。
在本发明的芯片封装结构中，配置在芯片与散热基板之间的异质接合导热缓冲层具有散热性佳且可吸收剪应力的特性，因此可避免系统因温度变化造成的机械式疲劳破坏或热疲劳破坏，提升芯片封装结构的效能及可靠度。
为让本发明的上述特征和优点能更明显易懂，下文特举优选实施例，并配合附图，作详细说明如下。
附图说明
图1为依据本发明实施例的一种芯片封装结构的剖面示意图。
图2A是图1中的异质接合导热缓冲层的立体示意图。
图2B是图1中的异质接合导热缓冲层的俯视示意图。
图2C是图2B中沿C-C线所绘示的异质接合导热缓冲层的剖面放大示意图。
图3A至3F为依据本发明的第一实施例的一种芯片封装结构的制造流程的剖面示意图。
图4A至4D为依据本发明的第二实施例的一种芯片封装结构的制造流程的剖面示意图。
图5A至5D为依据本发明的第三实施例的一种芯片封装结构的制造流程的剖面示意图。
图6为依据本发明的第四实施例的一种芯片封装结构的制造流程的剖面示意图。
图7是绘示芯片封装结构在有无本发明的异质接合导热缓冲层的情况下，受剪应力时的芯片的受力示意图。
图8是绘示芯片封装结构在有无本发明的异质接合导热缓冲层的情况下，受剪应力时的芯片的受力示意图。
附图标记说明
100、200a、200b：芯片封装结构
102、202、300：散热基板
103：焊垫
104、204、310、400、502：异质接合导热缓冲层
105：P电极
106、206、314：芯片
107：N电极
108、308：柱状体
110、210、316：接合层
112、312：填充物
302：金属种子层
304：光致抗蚀剂层
306：开口
500：连接层
具体实施方式
图1为依据本发明实施例的一种芯片封装结构的剖面示意图。图2A是图1中的异质接合导热缓冲层的立体示意图。图2B是图1中的异质接合导热缓冲层的俯视示意图。图2C是图2B中沿C-C线所绘示的异质接合导热缓冲层的剖面示意图。
请参照图1，芯片封装结构100包括散热基板102、异质接合导热缓冲层104及芯片106。散热基板102例如为金属核心印刷电路板(metal coreprinted circuit board；MCPCB)、散热器(heat sink)或陶瓷材料。金属核心印刷电路板的材料例如是铜或铝。
芯片106配置于散热基板102上。芯片106例如是具有P电极(P-electrode)105及N电极(N-electrode)107的LED芯片。芯片106也可以是太阳能电池芯片或其他光电转换芯片。
异质接合导热缓冲层104配置于散热基板102与芯片106之间。异质接合导热缓冲层104的材料包括锡、铜或其他高热传导的金属材料。在实施例中，散热基板102例如是具有位于其上的多个焊垫103，而异质接合导热缓冲层104例如是配置在散热基板102的焊垫103上。
接下来，请一并参照图1、2A至2C，将详细说明异质接合导热缓冲层104的结构。异质接合导热缓冲层104包括多个垂直于散热基板102配置的柱状体(pillar)108。各柱状体108的深度为D，宽度为W，且柱状体108之间的间隙为S。各柱状体108的深宽比(aspect ratio；depth-to-width ratio)例如是介于约3∶1到50∶1之间。在实施例中，D为30μm，W为10μm，S为10μm。在另一实施例中，D为100μm，W为2μm，S为2μm。W和S可以相同或不同。
另外，异质接合导热缓冲层104的柱状体108的截面例如是圆形，且柱状体108呈阵列分布，例如是正三角形的最密排列，如图2B所示。当然，本发明所属技术领域中普通技术人员应了解，异质接合导热缓冲层104的柱状体108的截面与阵列分布并不以图2B为限，可以依设计需求而加以调整。也就是说，异质接合导热缓冲层104的柱状体108的截面可以包括圆形、方形、三角形或菱形，且异质接合导热缓冲层104的柱状体108的阵列分布可以为规则排列或不规则排列。在实施例中，当异质接合导热缓冲层104为方形柱状体时，异质接合导热缓冲层104的高度为长度或宽度的1/5～1/10。
本发明的芯片封装结构100也可以包括接合层110及填充物(filler)112。接合层110配置在芯片106与异质接合导热缓冲层104之间。详而言之，接合层110配置在P电极105及N电极107的表面上。接合层110的材料可以和异质接合导热缓冲层104的材料相同或不同。接合层110的材料包括锡、铜、金、银或金锡合金。
填充物112配置在异质接合导热缓冲层106的柱状体108之间。填充物112的材料包括高分子材料如导热膏(thermal grease)、银胶等，或金属粉粒材料如非金属树脂混合金属粉粒。
在本发明的芯片封装结构100中，异质接合导热缓冲层104的柱状体108呈高密度排列以增加热传面积，且异质接合导热缓冲层104的柱状体108因深宽比高，具有柔软效果，可吸收剪应力。另外，异质接合导热缓冲层106的柱状体108之间配置的填充物112，也可以进一步地增加热传效果。也就是说，本发明的芯片封装结构100具有散热性佳且可吸收剪应力的特性，因此可避免系统因温度变化造成的机械式疲劳破坏或热疲劳破坏，提升芯片封装结构100的效能及可靠度。
以下，将列举多个实施例说明本发明的芯片封装结构的制造方法。
第一实施例
图3A至3F为依据本发明的第一实施例的一种芯片封装结构的制造流程的剖面示意图。
首先，请参照图3A，提供散热基板300。散热基板300例如为金属核心印刷电路板(metal core printed circuit board；MCPCB)、散热器(heat sink)或陶瓷材料。金属核心印刷电路板的材料例如是铜或铝。
然后，请参照图3B到3D，利用微机电电铸技术，在散热基板300上形成异质接合导热缓冲层。
接下来，将详细说明异质接合导热缓冲层的制造方法。请参照图3B，在散热基板300上形成金属种子层302。形成金属种子层302的方法例如是电镀、蒸镀或溅镀。然后，在金属种子层302上形成光致抗蚀剂层304。光致抗蚀剂层304具有多个开口306，且各开口306的深宽比例如是介于约3∶1到50∶1之间。
接着，请参照图3C，对金属种子层302进行第一次电铸工艺，以于光致抗蚀剂层304的开口306中形成柱状体308。
之后，请参照图3D，移除光致抗蚀剂层304，以形成异质接合导热缓冲层310。在此实施例中，异质接合导热缓冲层310包括金属种子层302及柱状体308。
继之，请参照图3E，选择性地对异质接合导热缓冲层310进行第二次电铸工艺，以加粗异质接合导热缓冲层310的各柱状体308。也就是说，第二次电铸工艺是用来提高填充因子(filling factor)、增加各柱状体308的深宽比及加厚金属种子层302的厚度。在此实施例中，光致抗蚀剂层304的各开口306的深宽比例如是约5∶1，经第一次电铸工艺后的各柱状体308的深宽比维持在约5∶1，但经第二次电铸工艺后的可增加各柱状体308的深宽比。接着，可以选择性地在异质接合导热缓冲层310的柱状体308之间形成填充物312。填充物312的材料包括高分子材料如导热膏、银胶等，或金属粉粒材料如非金属树脂混合金属粉粒。
除了上述微机电电铸技术之外，还可以应用目前所发展的纳米技术来形成异质接合导热缓冲层，使得所形成的柱状体308的深宽比增加到约50∶1。
在完成异质接合导热缓冲层310的制作以后，请参照图3F，在异质接合导热缓冲层310上接合芯片314。于异质接合导热缓冲层310上接合芯片314之前，也可以在芯片314的接合面上选择性地形成接合层316。形成接合层316的方法包括电镀、蒸镀或溅镀。接合层316的材料可以和异质接合导热缓冲层310的材料相同或不同。接合层316的材料包括锡、铜、金、银或金锡合金。
然后，将芯片314的接合层316接合到异质接合导热缓冲层310上。在实施例中，异质接合导热缓冲层310及接合层316的材料例如均为锡，则可以利用例如是250℃的回焊设备将异质接合导热缓冲层310与接合层316以共晶方式接合。在另一实施例中，异质接合导热缓冲层310及接合层316的材料例如均为铜，则可以利用例如是烧结的方式接合。
第二实施例
图4A至4D为依据本发明的第二实施例的一种芯片封装结构的制造流程的剖面示意图，其中使用与第一实施例相同的元件符号来表示相同的构件。
第二实施例与第一实施例的差异在于形成异质接合导热缓冲层的方法不同。以下，将说明第二实施例与第一实施例的不同处，相同处则不再赘述。
首先，请参照图4A，在散热基板300上形成具有多个开口306的光致抗蚀剂层304。在此步骤中，当散热基板300例如是铜材料的金属核心印刷电路板时，可以省去形成金属种子层(请见图3B的302)的步骤，直接在散热基板300上形成光致抗蚀剂层304。
接着，请参照图4B，对散热基板300进行第一次电铸工艺，以于光致抗蚀剂层304的开口306中形成柱状体308。
之后，请参照图4C，移除光致抗蚀剂层304，以形成异质接合导热缓冲层400。在此实施例中，异质接合导热缓冲层400仅包括柱状体308。
继的，请参照图4D，选择性地对异质接合导热缓冲层400进行第二次电铸工艺，以加粗异质接合导热缓冲层400的各柱状体308及加厚散热基板300的厚度。继之，在芯片314的接合面上形成接合层316，然后将芯片314接合到异质接合导热缓冲层400上。
第三实施例
图5A至5D为依据本发明的第三实施例的一种芯片封装结构的制造流程的剖面示意图，其中使用与第一实施例相同的元件符号来表示相同的构件。
第三实施例与第一实施例的差异在于形成异质接合导热缓冲层的方法不同。以下，将说明第三实施例与第一实施例的不同处，相同处则不再赘述。
首先，请参照图5A，在散热基板300上依序形成金属种子层302及光致抗蚀剂层304。接着，对金属种子层302进行第一次电铸工艺，以于光致抗蚀剂层304的开口306中形成柱状体308。在第三实施例中，此步骤还包括增加电铸时间，使柱状体308持续往光致抗蚀剂层304的开口306外生长，而在光致抗蚀剂层304上形成连接柱状体308的顶部的连接层500，以形成由金属种子层302、柱状体308与连接层500构成的异质接合导热缓冲层502。连接层500可以使后续异质接合导热缓冲层502与芯片接合时更为容易。在此实施例中，连接层500呈香菇头形状，也可以依设计需求，在连接层500中留一些开口(未绘示)，使后续的去除光致抗蚀剂层304的步骤更为容易。
然后，请参照图5B，移除光致抗蚀剂层304。
之后，请参照图5C，选择性地对异质接合导热缓冲层502进行第二次电铸工艺，以加粗异质接合导热缓冲层502的各柱状体308以及加厚连接层500和金属种子层502的厚度。接着，可以选择性地在异质接合导热缓冲层502的柱状体308之间形成填充物312。
继之，请参照图5D，在异质接合导热缓冲层502上接合芯片314。于异质接合导热缓冲层502上接合芯片314之前，也可以在芯片314的接合面上选择性地形成接合层316。然后，将芯片314的接合层316接合到异质接合导热缓冲层502的连接层500上。
第四实施例
图6为依据本发明的第四实施例的一种芯片封装结构的制造流程的剖面示意图，其中使用与第三实施例相同的元件符号来表示相同的构件。
第四实施例与第二和第三实施例类似，其差异在于形成异质接合导热缓冲层的方法不同。以下，将说明第四实施例与第二和第三实施例的不同处，相同处则不再赘述。
首先，请参照图6，在散热基板300上形成光致抗蚀剂层304。在此步骤中，当散热基板300例如是铜材料的金属核心印刷电路板时，可以省去形成金属种子层的步骤，直接在散热基板300上形成光致抗蚀剂层304。接着，对散热基板300进行第一次电铸工艺，以于光致抗蚀剂层304的开口306中形成柱状体308。在第四实施例中，此步骤还包括增加电铸时间，使柱状体308持续往开口306外生长，而在光致抗蚀剂层304上形成连接柱状体308的顶部的连接层500。
之后的步骤，请参照图5B～5D，在此不再赘述。
接下来，将以电脑模拟芯片封装结构200a与200b在有无本发明的异质接合导热缓冲层204的情况下，受剪应力时的芯片206的受力示意图，分别以图7及图8表示。其中，散热基板202、异质接合导热缓冲层204及接合层210的材料例如均为铜，芯片206的材料例如为硅。特别在图8中的芯片封装结构200b并没有接合层210。
图7及图8的横轴是芯片封装结构200的接合点离芯片206边缘的距离，一般而言，最靠近芯片206边缘的接合点受力最大，也最容易因系统操作时温度反复变化而造成的疲劳效应所破坏。在图7及图8中，芯片封装结构200的接合点最靠近芯片206边缘的距离标示为原点，接合点的距离随着越远离芯片边缘而递增。
如图7所示，在无本发明的异质接合导热缓冲层204的情况下(虚线)，散热基板202在最靠近芯片206边缘的接合点，其承受的剪应力急速增加，最大至300MPa左右。但存在有本发明的异质接合导热缓冲层204的情况下(实线)，异质接合导热缓冲层204因高深宽比造成的柔软效果，可以吸收剪应力并均匀分散到整片异质接合导热缓冲层204上，因此芯片206所承受的剪应力基本上呈小振幅波动，不会因为越靠近芯片206的边缘而遽增。
同样地，如图8所示，在无本发明的异质接合导热缓冲层204的情况下(虚线)，芯片206在最靠近芯片206边缘的接合点，其承受的剪应力急速增加，最大至600MPa左右。但存在有本发明的异质接合导热缓冲层204的情况下(实线)，异质接合导热缓冲层204因高深宽比造成的柔软效果，可以吸收剪应力并均匀分散到整片异质接合导热缓冲层204，因此芯片206所承受的剪应力基本上呈小振幅波动，不会因为越靠近芯片206的边缘而遽增。
综上所述，在本发明的芯片封装结构中，异质接合导热缓冲层以高热传导的金属材料(如锡或铜)取代已知的导热胶或锡球，并以高密度排列来增加热传面积。另外，异质接合导热缓冲层的柱状体因深宽比高，具有柔软效果，可吸收剪应力，避免系统因温度变化造成的机械式疲劳破坏或热疲劳破坏。此外，异质接合导热缓冲层的柱状体之间配置的填充物如金属粉粒材料或高分子材料，也可以进一步地增加热传效果。因此，本发明的芯片封装结构因散热性佳且可吸收剪应力的特性，适合大面积及高热量的LED封装照明或聚光型的太阳能电池封装的散热方案。
虽然本发明已以优选实施例披露如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的为准。

Claims (28)

1.一种芯片封装结构，其特征在于：该结构包括：
散热基板；
芯片，配置于该散热基板上；以及
异质接合导热缓冲层，配置于该散热基板与该芯片之间，其中该异质接合导热缓冲层包括多个垂直于该散热基板配置的柱状体，且各该柱状体的深宽比介于3∶1到50∶1之间。
2.如权利要求1所述的芯片封装结构，其特征在于：该异质接合导热缓冲层的材料包括锡或铜。
3.如权利要求1所述的芯片封装结构，其特征在于：该异质接合导热缓冲层的所述柱状体的截面包括圆形、方形、三角形或菱形。
4.如权利要求1所述的芯片封装结构，其特征在于：该异质接合导热缓冲层的所述柱状体呈阵列分布。
5.如权利要求1所述的芯片封装结构，其特征在于：该异质接合导热缓冲层的高度为长度或宽度的1/5～1/10。
6.如权利要求1所述的芯片封装结构，其特征在于：该异质接合导热缓冲层还包括连接层，连接所述柱状体的顶部。
7.如权利要求1所述的芯片封装结构，其特征在于：还包括接合层，配置在该芯片与该异质接合导热缓冲层之间。
8.如权利要求7所述的芯片封装结构，其特征在于：该接合层的材料和该异质接合导热缓冲层的材料相同。
9.如权利要求7所述的芯片封装结构，其特征在于：该接合层的材料和该异质接合导热缓冲层的材料不同。
10.如权利要求7所述的芯片封装结构，其特征在于：该接合层的材料包括锡、铜、金、银或金锡合金。
11.如权利要求1所述的芯片封装结构，其特征在于：还包括填充物，配置在该异质接合导热缓冲层的所述柱状体之间。
12.如权利要求11所述的芯片封装结构，其特征在于：该填充物的材料包括金属粉粒材料或高分子材料。
13.如权利要求1所述的芯片封装结构，其特征在于：该芯片包括太阳能电池芯片或发光二极管芯片。
14.一种芯片封装结构的制造方法，其特征在于：该制造方法包括：
提供散热基板；
于该散热基板上形成异质接合导热缓冲层，其中该异质接合导热缓冲层包括垂直于该散热基板配置的多个柱状体；以及
于该异质接合导热缓冲层上接合芯片。
15.如权利要求14所述的芯片封装结构的制造方法，其特征在于：形成该异质接合导热缓冲层的方法包括利用微机电电铸技术或纳米技术。
16.如权利要求15所述的芯片封装结构的制造方法，其特征在于：利用微机电电铸技术形成该异质接合导热缓冲层的步骤包括：
在该散热基板上形成金属种子层；
在该金属种子层上形成光致抗蚀剂层，该光致抗蚀剂层具有多个开口，且各开口的深宽比介于3∶1到50∶1之间；
对该金属种子层进行第一次电铸工艺，以于该光致抗蚀剂层的所述开口中形成所述柱状体；以及
移除该光致抗蚀剂层，以形成该异质接合导热缓冲层。
17.如权利要求16所述的芯片封装结构的制造方法，其特征在于：还包括对该异质接合导热缓冲层进行第二次电镀工艺，以加粗该异质接合导热缓冲层的各该柱状体。
18.如权利要求16所述的芯片封装结构的制造方法，其特征在于：对该金属种子层进行该第一次电镀工艺还包括增加电铸时间，使所述柱状体持续往该光致抗蚀剂层的所述开口外生长，而在该光致抗蚀剂层上形成连接所述柱状体的顶部的连接层。
19.如权利要求15所述的芯片封装结构的制造方法，其特征在于：利用微机电电铸技术形成该异质接合导热缓冲层的步骤包括：
在该散热基板上形成光致抗蚀剂层，该光致抗蚀剂层具有多个开口，且各开口的深宽比介于3∶1到50∶1之间；
对该散热基板进行第一次电铸工艺，以于该光致抗蚀剂层的所述开口中形成所述柱状体；以及
移除该光致抗蚀剂层，以形成该异质接合导热缓冲层。
20.如权利要求19所述的芯片封装结构的制造方法，其特征在于：还包括对该异质接合导热缓冲层进行第二次电镀工艺，以加粗该异质接合导热缓冲层的各该柱状体。
21.如权利要求19所述的芯片封装结构的制造方法，其特征在于：对该金属种子层进行该第一次电镀工艺还包括增加电铸时间，使所述柱状体持续往该光致抗蚀剂层的所述开口外生长，而在该光致抗蚀剂层上形成连接所述柱状体的顶部的连接层。
22.如权利要求14所述的芯片封装结构的制造方法，其特征在于：该异质接合导热缓冲层的材料包括锡或铜。
23.如权利要求14所述的芯片封装结构的制造方法，其特征在于：该芯片包括太阳能电池芯片或发光二极管芯片。
24.如权利要求14所述的芯片封装结构的制造方法，其特征在于：于该异质接合导热缓冲层上接合该芯片之前，还包括于该芯片的接合面上形成接合层。
25.如权利要求24所述的芯片封装结构的制造方法，其特征在于：形成该接合层的方法包括电镀。
26.如权利要求24所述的芯片封装结构的制造方法，其特征在于：该接合层的材料包括锡、铜、金、银或金锡合金。
27.如权利要求14所述的芯片封装结构的制造方法，其特征在于：于该异质接合导热缓冲层上接合该芯片之前，还包括于该异质接合导热缓冲层的所述柱状体之间形成填充物。
28.如权利要求27所述的芯片封装结构的制造方法，其特征在于：该填充物的材料包括金属粉粒材料或高分子材料。
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Application publication date: 20100623