CN101752012B - Error correcting controller, flash memory chip system thereof and error correcting method - Google Patents
Error correcting controller, flash memory chip system thereof and error correcting method Download PDFInfo
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- CN101752012B CN101752012B CN 200810182398 CN200810182398A CN101752012B CN 101752012 B CN101752012 B CN 101752012B CN 200810182398 CN200810182398 CN 200810182398 CN 200810182398 A CN200810182398 A CN 200810182398A CN 101752012 B CN101752012 B CN 101752012B
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Abstract
The invention relates to an error correcting controller that is connected between an old host controller with a low-order error correction function and a new flash memory with a high-order error correcting function. When the old host controller is to write data and old error correcting coding to the new flash memory, the error connecting controller generates new error correcting coding with the high-order error correcting function. Then, when the host controller is to read data and old error correcting coding from the new flash memory, the error correcting controller performs the error correcting procedure based on the new error correcting coding and transmits corresponding data based on the error correcting result and the error correcting ability of the old host controller. Accordingly, the invention ensures that the old host controller accesses the new flash memory without altering the framework of the old host controller.
Description
Technical field
The invention relates to a kind of flash memory chip system, and particularly relevant for flash memory chip system and error correcting controller and the error correcting method of a kind of tool error recovery (error correcting) function.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, make the consumer also increase rapidly the demand of Storage Media.Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and the characteristic of machinery-free structure etc., is fit to portable applications, the most suitable being used on the battery-powered product of this class Portable.For example, storage card is exactly a kind of with the storage device of nand flash memory as Storage Media, and has been widely used as the Storage Media of digital camera, mobile phone and MP3 player at present.
Due to nand flash memory can data writing after having the data of erasing take page as the unit data writing, take block as unit, each storage unit and need first erasing, block can because of repeatedly write the characteristic such as damage, therefore use nand flash memory must have as the console controller of the main frame (for example, digital camera, mobile phone and MP3 player) of Storage Media the block management function that can manage flash memory.Yet along with flash memory technology develops rapidly, the flash memory that capacity is larger is constantly weeded out the old and bring forth the new, and the user of old master's machine has the demand of the Storage Media of the larger storage volume of renewal.In general, new flash memory needs stronger block management function to operate, yet old master's machine controller often can't be supported new function.
For example, understand the data that the mistake in using correction program comes error recovery to read in the block management function of flash memory, and know the state (for example, whether block damages) of flash memory block according to the result of error recovery.(for example often can't support the required error correction capability of flash memory of new generation at the error correction capability that old master's machine controller possesses, when producing, old master's machine controller only configures the Error-Correcting Circuit that tool can detect 1 error bit ability of 2 error bit/error recoverys, yet when new flash memory needs the controller of enough 4 error bits of error recovery of prodigiosin can normal operation) time, this old master's machine controller can't be supported flash memory of new generation.Base this, having needs development one cover can make old master's machine controller not change under former hardware design framework the mechanism of coming the flash memory of access a new generation to meet the required error correction capability of flash memory of new generation.
Summary of the invention
The invention provides a kind of error correcting controller, it can make the flash memory of console controller access a new generation of old master's machine system.
The invention provides a kind of flash memory chip system, it can make the flash memory of console controller access a new generation of old master's machine system.
The invention provides a kind of error correcting method, it can make the flash memory of console controller access a new generation of old master's machine system.
The present invention proposes a kind of error correcting controller, and it comprises the first flash interface, the second flash interface, microprocessor unit, makes wrong unit and the first error correction unit.The first flash interface is to connect console controller.The second flash interface is to connect flash memory.Microprocessor unit is to be electrically connected to the first flash interface and the second flash interface.Making wrong unit is to be electrically connected to microprocessor unit.The first error correction unit is to be electrically connected to microprocessor unit, during wherein the first error correction unit can produce the first error recovery coding (error correcting code, ECC) and the data of wanting to write and the first error recovery coding that produces are stored in flash memory when console controller is wanted data writing to above-mentioned flash memory.in the present invention, when the console controller wish from flash memory during reading out data, microprocessor unit can read these data from flash memory can encode to judge whether the data that read have error bit and whether this error bit can be by error recovery according to first error recovery of reading with the first error recovery coding and first error correction unit of corresponding these data, the data that wherein read when the first error correction unit judgement have error bit and this error bit can be by error recovery the time, making wrong unit can produce and can be transmitted this misdata that can be corrected to above-mentioned console controller by the misdata of error recovery and microprocessor unit, wherein this can be to complete that data after error recovery produce and be to be come error recovery by console controller according to described the first error recovery coding by the misdata of error recovery.
In one embodiment of this invention, the data that read when the first error correction unit judgement have error bit and this error bit can't be by error recovery the time, microprocessor unit can transmit default misdata to above-mentioned console controller, and wherein above-mentioned console controller can judge that this default misdata has error bit and this error bit can't be by error recovery.
In one embodiment of this invention, above-mentioned console controller also includes the 3rd error correction unit.
In one embodiment of this invention, the maximum error recovery figure place of the 3rd above-mentioned error correction unit is less than the maximum error recovery figure place of above-mentioned the first error correction unit.
In one embodiment of this invention, above-mentioned data also comprise the second error recovery coding.
In one embodiment of this invention, above-mentioned error correcting controller also comprises the second error correction unit that is electrically connected to above-mentioned microprocessing unit, and wherein the maximum error recovery figure place of this second error correction unit is the maximum error recovery figure place that is same as above-mentioned the 3rd error correction unit.
In one embodiment of this invention, when above-mentioned console controller wish reads this data from above-mentioned flash memory, the second error correction unit can regenerate according to these data the second error recovery coding of corresponding these data.
In one embodiment of this invention, above-mentioned when console controller is wanted data writing to above-mentioned flash memory, above-mentioned the second error correction unit data that can encode error recovery to want to write according to this second error recovery.
In one embodiment of this invention, above-mentioned microprocessor unit will be stored in about the parameter information of above-mentioned the first error correction unit in a physical blocks of above-mentioned flash memory, and the physical blocks that will store this parameter information is labeled as and damages block.
In addition, the present invention also propose a kind of flash memory chip system that configures above-mentioned flash memory and above-mentioned error correcting controller with and error correcting method.
The present invention also proposes a kind of flash memory chip system, comprising: flash memory; and error correcting controller, be electrically connected to described flash memory, wherein this error correcting controller can produce the first error recovery coding and described data and described the first error recovery are encoded and be stored in described flash memory when described console controller is wanted data writing to described flash memory, wherein when described console controller wish reads described data from described flash memory, described error correcting controller can read described data and described the first error recovery coding from described flash memory, and encode to judge according to described the first error recovery whether the described data that read have at least one error bit and whether described at least one error bit can be by error recovery, the described data that wherein read when the judgement of described error correcting controller have described at least one error bit and described at least one error bit can be by error recovery the time, described error correcting controller can transmit and can be given described console controller by the misdata of error recovery, wherein said can be produce and can be come error recovery by described console controller according to the described data that described the first error recovery coding is completed after error recovery by the misdata of error recovery.
the present invention also proposes a kind of error correcting method, be applicable to the error recovery console controller to the data of flash memory institute access, described error correcting method comprises: produce the first error recovery coding and described data are encoded with described the first error recovery when described console controller is wanted data writing to described flash memory and be stored in described flash memory, and when described console controller wish reads described data from described flash memory, read described data and described the first error recovery coding and encode to judge according to described the first error recovery whether the described data that read have at least one error bit and whether described at least one error bit can be by error recovery from described flash memory, wherein there are described at least one error bit and described at least one error bit can be by error recovery the time when the described data that read of judgement, transmitting can be by the misdata of error recovery to described console controller, wherein said can be produce and can be come error recovery by described console controller according to the described data that described the first error recovery coding is completed after error recovery by the misdata of error recovery.
The present invention also proposes a kind of error correcting controller, and it comprises the first flash interface, the second flash interface, microprocessor unit and the first error correction unit.The first flash interface is to connect console controller.The second flash interface is to connect flash memory.Microprocessor unit is to be electrically connected to the first flash interface and the second flash interface.The first error correction unit is to be electrically connected to microprocessor unit, during wherein the first error correction unit can produce the first error recovery coding and the data of wanting to write and the first error recovery coding that produces are stored in flash memory when console controller is wanted data writing to above-mentioned flash memory.Impact damper is to be electrically connected to microprocessor unit and in order to temporal data.In the present invention, when the console controller wish from flash memory during reading out data, microprocessor unit can read these data first error recovery coding corresponding with it from flash memory, and the first error correction unit can be carried out error-correcting routine to the data that read according to the first error recovery coding, and microprocessor unit can send the data of error recovery to console controller, and wherein microprocessor unit can respond according to manufacturer's instruction (vendor command) the wrong figure place that judges in this error-correcting routine to console controller.
In addition, the present invention also propose a kind of flash memory chip system that configures above-mentioned flash memory and above-mentioned error correcting controller with and error correcting method.
the present invention also proposes a kind of flash memory chip system, comprising: flash memory, and error correcting controller, be electrically connected to described flash memory, wherein said error correcting controller can produce the first error recovery coding and described data and described the first error recovery are encoded and be stored in described flash memory when described console controller is wanted data writing to described flash memory, wherein when described console controller wish reads described data from described flash memory, described error correcting controller can read described data and described the first error recovery coding from described flash memory, according to described the first error recovery coding, the described data that read are carried out error-correcting routine, and the described data of error recovery send described console controller to, and wherein said error correcting controller can respond according to manufacturer's instruction at least one wrong figure place that judges at described error-correcting routine to described console controller.
The present invention also proposes a kind of error correcting method, be applicable to the error recovery console controller to the data of flash memory institute access, described error correcting method comprises: produce the first error recovery coding and described data are encoded with described the first error recovery when described console controller is wanted data writing to described flash memory and be stored in described flash memory; When described console controller wish reads described data from described flash memory, read described data and described the first error recovery coding from described flash memory, according to described the first error recovery coding, the described data that read are carried out error-correcting routine; Send the described data of error recovery to described console controller; And at least one wrong figure place that judges in described error-correcting routine is responded to described console controller according to manufacturer's instruction.
Based on above-mentioned, the present invention passes through to configure the error correcting controller that can support new flash memory between the console controller of old system and new flash memory, and error correcting controller is carried out error recovery coding and the error-correcting routine meet new flash memory thus, and this can make the flash memory of console controller access a new generation of old system base.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and coordinate appended graphic being described in detail below.
Description of drawings
Fig. 1 illustrates the summary calcspar of flash memory chip system according to first embodiment of the invention.
Fig. 2 illustrates the data flow diagram of console controller access flash memory chip system according to first embodiment of the invention.
Fig. 3 illustrates the process flow diagram of error recovery step according to first embodiment of the invention.
Fig. 4 illustrates the summary calcspar of flash memory chip system according to second embodiment of the invention.
Fig. 5 illustrates the data flow diagram of console controller access flash memory chip system according to second embodiment of the invention.
Fig. 6 illustrates the process flow diagram of error recovery step according to second embodiment of the invention.
[main element label declaration]
100: flash memory chip system
102: flash memory
102-1～102-N: physical blocks
104: error correcting controller
104a: microprocessor unit
104b: the first error correction unit
104c: impact damper
104d: the first flash interface
104e: the second flash interface
104f: make wrong unit
200: console controller
202: old error correction unit
DATA1, DATA2: data
ECC1, ECC2, ECC2 ': error recovery coding
S301, S303, S307, S309, S311, S313, S315, S317, S319, S321: the step of error recovery
400: flash memory chip system
402: flash memory
402-1～402-N: physical blocks
404: error correcting controller
404a: microprocessor unit
404b: the first error correction unit
404c: impact damper
404d: the first flash interface
404e: the second flash interface
404f: the second error correction unit
S601, S603, S607, S609, S611, S613, S615, S617, S619, S621, S623, S625, S627: the step of error recovery
Embodiment
The present invention's configuration between the console controller of old master's machine system and new flash memory can support the error correcting controller of new flash memory to come data execution error correction coding and the error-correcting routine to institute's access.Base this, can be under the framework that does not change former host computer system, make the console controller of old master's machine system can access the flash memory of a new generation.Below will describe the present invention in detail with several exemplary embodiment.
[the first embodiment]
Fig. 1 illustrates the summary calcspar of flash memory chip system according to first embodiment of the invention.
Please refer to Fig. 1, flash memory chip system 100 comprises flash memory 102 and error correcting controller 104.Flash memory chip system 100 can be connected with console controller 200, by console controller 200, it is carried out various access runnings.Particularly, console controller 200 has old error correction unit 202, and wherein old error correction unit 202 can provide 1 error bit of error recovery and the ability that detects 2 error bits to data.It is worth mentioning that, flash memory 102 is to be encapsulated as the triangular web chip with error correcting controller 104 in the present embodiment, yet flash memory 102 can be respectively independently chip with error correcting controller 104 in another embodiment of the present invention.
Flash memory 102 is the Storage Medias in order to storage data.Flash memory 102 can be divided into a plurality of physical blocks 102-1～102-N, and this a little physical blocks unit can be defined as data field (data area) and spare area (spare area).Classify as in the physical blocks of data field and can store the valid data that write by writing instruction, and the physical blocks in the spare area is in order to the physical blocks in replacement data district when execution writes instruction.Specifically, console controller 200 wishs are write fashionable to the physical blocks of data field, console controller 200 can be from the spare area extracts physical block and will the physical blocks that wish is upgraded in the data field in effective legacy data write to the new data of wanting to write the physical blocks of extracting from the spare area and the physical blocks that will write new data is associated as the data field, and the physical blocks of data field is erased and is associated as the spare area originally.In order to allow successfully access of host computer system under console controller 200 with the physical blocks of the mode storage data of rotating, console controller 200 can carry out access for host computer system by the configuration logic block, and wherein logical blocks is to configure according to the physical areas block size.That is to say that console controller 200 can set up logical-physical address mapping table (logical-physical addressmapping table), and the mapping relations in this table between the physical blocks of record and renewal logical blocks and data field reflect rotating of physical blocks, so host computer system only need to be assigned access instruction to console controller 200 for providing logical blocks, and console controller 200 can read or data writing the physical blocks of shining upon practically according to the logical-physical address mapping table.In addition, in flash memory 102, the physical blocks of meeting reserve part is distinguished as an alternative, and it is to continue running in order to replace the physical blocks of having damaged when the physical blocks in data field or spare area is damaged.
Microprocessor unit 104a is the running in order to all elements in Control and coordination error correcting controller 104.Specifically, microprocessor unit 104a can process the access instruction (for example, writing instruction or reading command) of assigning with 200 pairs of flash memory chip systems 100 of response console controller according to the error correcting method (as shown in Figure 3) that the embodiment of the present invention proposes.
The first error correction unit 104b is electrically connected to microprocessor unit 104a.The first error correction unit 104b can produce the new error recovery coding that meets flash memory 102 specifications when console controller 200 is wanted data writing to flash memory chip system 100.
In embodiments of the present invention, the maximum error recovery figure place of the first error correction unit 104b is be designed to 4 positions and can detect 8 error bits, meets the required error correction capability of flash memory 102 to provide.Yet, it must be appreciated that it is the Error-Correcting Circuit that is designed to 4 positions that the first error correction unit 104b of the present invention is not limited to maximum error recovery figure place.In other words, can support the Error-Correcting Circuit of the error correction capability that flash memory 102 is required all to can be applicable to the present invention.For example, when if flash memory 102 must carry out access with error recovery coding that can 4 error bits of error recovery and error-correcting routine, the first error correction unit 104b can be can 4 error bits of error recovery, the Error-Correcting Circuit of 8 error bits, 12 error bits, 24 error bits or 48 error bits.
The first flash interface 104d connects console controller 200, and the second flash interface 104e connects flash memory 102.
Make wrong unit 104f and be and be electrically connected to microprocessor unit 104a and produce error bit in order to the instruction of foundation microprocessor unit 104a in data.It is worth mentioning that, be to come implementation to make wrong unit 104f with hardware structure in the present embodiment, yet the invention is not restricted to this, make wrong unit 104f and can also form of firmware come implementation, in another embodiment, this is made wrong unit 104f and also can be embodied in microprocessor unit 104a.
Fig. 2 illustrates the data flow diagram of console controller 200 access flash memory chip systems 100 according to first embodiment of the invention.
Please refer to Fig. 2, when console controller 200 receives by its host computer system (not illustrating) the data DATA1 that wants to write, the old error correction unit 202 of console controller 200 can produce old error recovery coding ECC1 according to data DATA1, and console controller 200 can be assigned flash memory chip system 100 and writes instruction and data DATA1 and the old error recovery ECC1 that encodes is sent to flash memory chip system 100.
When the microprocessor unit 104a of error correcting controller 104 via the first flash interface 104d receive that console controller 200 transmits write instruction WC, data DATA1 and old error recovery coding ECC1 the time, microprocessor unit 104a can learn this access instruction for writing instruction, and data DATA1 and old error recovery coding ECC1 are temporary in impact damper 104c.Then, the first error correction unit 104b can produce new error recovery coding ECC2 with the data DATA2 that comprises data DATA1 and old error recovery coding ECC1.At last, data DATA2 and new error recovery coding ECC2 are sent in the physical blocks of flash memory 102.
In addition, when the microprocessor unit 104a of error correcting controller 104 received the reading command RC of reading out data DATA1 and old error recovery coding ECC1 via the first flash interface 104d from console controller 200, microprocessor unit 104a can read the data DATA2 that comprises data DATA1 and old error recovery coding ECC1 and new error recovery coding ECC2 and data DATA2 and the new error recovery ECC2 that encodes is temporary in impact damper 104c from flash memory 102.Afterwards, the first error correction unit 104b can be according to the data DATA2 execution error correction program of new error recovery coding ECC2 to reading.Afterwards, microprocessor unit 104a can transmit corresponding data to console controller 200 according to the result of error recovery.
Specifically, if the first error correction unit 104b can execution error correction program judge when whether having error bit and data DATA2 in data DATA2 has error bit and attempt error recovery is carried out in error bit.it is worth mentioning that, due to the old error correction unit 202 of console controller 200 as mentioned above also can the execution error correction program and console controller 200 can be according to the execution result of old error correction unit 202 to the relevant management operation of the onblock executing of flash memory (for example, carry out average block wearing and tearing (wear-leveling) program), therefore can after executing error-correcting routine to data DATA2, the first error correction unit 104b provide data DATA1 and old error recovery coding ECC1 to console controller 200 by the error correction capability according to old error correction unit 202 according to embodiment of the present invention microprocessor unit 104a.
For example, the data DATA2 that reads when the first error correction unit 104b judgement is when having error bit, and microprocessor unit 104a can transmit the data DATA1 that reads and encode ECC1 to console controller 200 with old error recovery.
In addition, the data that read when the first error correction unit 104b judgement are deposited DATA2 and are had error bit and this error bit can be by error recovery the time, make wrong unit 104f and can produce error bit at random among the data DATA1 that receives error recovery from the first error correction unit 104b, and microprocessor unit 104a can send data DATA1 and the old error recovery coding ECC1 with error bit to console controller 200.Particularly, make wrong unit 104f and produce the data DATA1 with error bit and can come error recovery according to old error recoverys coding ECC1 by old error correction unit 202, therefore make wrong unit 104f and can produce the data DATA1 with error bit according to the error correction capability of old error correction unit 202.In the present embodiment, 1 error bit of old error correction unit 202 energy error recoverys, therefore making wrong unit 104f can produce 1 error bit at random in data DATA1, and microprocessor unit 104a can send data DATA1 and the old error recovery coding ECC1 with 1 error bit to console controller 200.The base this, according to the embodiment of the present invention, though the error correcting controller 104 of flash memory chip system 100 carries out error recovery with error bit, but also can provide the information of the position of having made a mistake to console controller, console controller 200 can know that the unsettled situation of storing state has appearred in the physical blocks of institute's access thus.
It is worth mentioning that, in another embodiment of the present invention, if old error correction unit 202 can 4 error bits of error recoverys, and the first error correction unit 104b makes wrong unit 104f and also can produce according to mapping ruler the data DATA1 of above-mentioned tool error bit can 8 error bits of error recovery the time.For example, when having 1 or 2 error bit in data DATA2, make wrong unit 104f and can make 1 error bit in by the data DATA1 of the first error correction unit 104b error recovery; When having 3 or 4 error bits in data DATA2, make wrong unit 104f and can make 2 error bits in by the data DATA1 of the first error correction unit 104b error recovery; When having 5 or 6 error bits in data DATA2, make wrong unit 104f and can make 3 error bits in by the data DATA1 of the first error correction unit 104b error recovery; And when having 7 or 8 error bits in data DATA2, make wrong unit 104f and can make 4 error bits in by the data DATA1 of the first error correction unit 104b error recovery.
Moreover, the data DATA2 that reads when the first error correction unit 104b judgement has error bit and error bit can't be by error recovery the time, and microprocessor unit 104a default misdata and the default error recovery that can transmit prior storage encoded to console controller 200.For example, this default misdata can be judged to be according to this default error recovery coding the error bit that generation can't error recovery by old error correction unit 202.
Specifically, because the first error correction unit 104b judgement data DATA2 can't be by error recovery (namely, data DATA2 has 5～8 error bits), that is to say that data DATA1 loses in flash memory 102, therefore microprocessor unit 104a must inform that old error correction unit 202 data DATA1 lose, and console controller 200 just can judge that the physical blocks of storage data DATA1 damages according to the error recovery result of old error correction unit 202 thus.In the present embodiment, because old error correction unit 202 can detect to data error recovery coding and the error-correcting routine of 2 error bits and 1 error bit of error recovery, so 104 default misdata that store in advance of microprocessor unit are to have 2 error bits.It is worth mentioning that, the above mapping ruler of carrying is only illustration, the invention is not restricted to this mapping ruler.
In another embodiment, except mapping ruler, console controller 200 can be assigned manufacturer's instruction (vendor command) during reading out data, the wrong figure place of the data DATA1 reality that console controller 200 can be read from flash memory chip system 100 by this manufacturer's instruction, and allow console controller 200 carry out corresponding administrative mechanism for the actual damage situation of flash memory 102.That is to say, the error correcting controller 104 data DATA1 of error recovery sends console controller 200 to, sends the wrong figure place of reality to console controller 200 by the instruction of response manufacturer in addition.
In addition, it is worth mentioning that the correlation parameter information that the physical blocks of flash memory 102 in the present embodiment can store error correcting controller 104 and use (for example, about the information of the required error correction capability of the physical blocks of access flash memory 102, about the information of the error correction capability of console controller 200, firmware program of error correcting controller 104 etc.).Yet, for avoid console controller 200 may be under the physical blocks that can't identification stores these a little important informations the mistake deletion be stored in information in this physical blocks, therefore in the present embodiment, microprocessor unit 104a can be labeled as the physical blocks that stores these a little information and damage physical blocks.Therefore, console controller 110 can change with the physical blocks in above-mentioned alternate area and carries out access for damaging physical blocks according to these a little physical blocks of this mark identification when this a little physical blocks of console controller 110 accesses.
Based on above-mentioned, the flash memory chip system 100 that the embodiment of the present invention proposes can offer the console controller institute access of old master's machine system, and the console controller that solves thus old master's machine system can't be supported the problem of new flash memory.Below will coordinate Fig. 3 explanation according to the error correcting method of the embodiment of the present invention.
Fig. 3 illustrates the process flow diagram of error recovery step according to first embodiment of the invention.
Please refer to Fig. 3, receive access instruction and judge that this access instruction is for writing instruction or reading command from console controller 200 in step S301.
If this access instruction is when writing instruction, can error recovery old with it according to the data that write (for example encode in step S303, data DATA1 and old error recovery coding ECC1) (for example produce new error recovery coding, new error recovery coding ECC2), and in step S305 data, its old error recovery coding of wanting to write is stored in the physical blocks of flash memory 102 with the new error recovery coding that produces.
When if this access instruction is the reading out data instruction, can be according to instruction reading out data from the physical blocks of flash memory 102 error recovery coding old with it (for example, data DATA1 and old error recovery coding ECC1) and corresponding new error recovery coding in step S307.
Then, can be according to the data error recovery old with it that the judgement of new error recovery coding the is read position of whether making a mistake of encoding in step S309, if when judging the data that read error recovery coding old with it without the generation error bit in step S309, send the data that read error recovery coding old with it to console controller 200 in step S311.
If judge in step S309 when the data that read error recovery old with it coding makes a mistake, the program that can proofread and correct error bit in step S313, and judge that in step S315 whether this error bit is by error recovery.If when the result of error-correcting routine shows this error bit by error recovery in step S315, producing in the data of error recovery in step S317 can be by the error bit of console controller 200 error recoverys, and sends data and the old error recovery coding thereof of tool error bit to console controller 200 in step S319.
If when this error bit of judgement can't be by error recovery in step S315, can will preset misdata and encode with default error recovery and send console controller 200 in step S321.
In addition, miss as mentioned above the set information of deletion error correcting controllers 104 for fear of console controller 200, in another embodiment of the present invention, above-mentioned error recovery step also comprises the parameter information about the first error correction unit is stored in a physical blocks of flash memory and this physical blocks is labeled as damages block.
It is worth mentioning that, in order to avoid the position of making a mistake when the programming flash memory, error correcting controller 104 also comprises data converter (not illustrating) in another embodiment of the present invention.Data converter can receive when wanting to write to the data DATA1 of flash memory 102 from console controller 200 when error correcting controller 104, each in data DATA1 is carried out suitable conversion, with with in data DATA1 continuously and the position of recording identical value (for example, be a plurality of positions or continuous a plurality of positions for " 1 " of " 0 " continuously) disperse, so that more stable when programming flash memory 102.Particularly, data converter can judge the position that whether has in data DATA1 continuously and record identical value, if data DATA1 has continuously and during the position of recording identical value data converter ability data DATA1 is carried out above-mentioned conversion.
[the second embodiment]
Fig. 4 illustrates the summary calcspar of flash memory chip system according to second embodiment of the invention.
Please refer to Fig. 4, flash memory chip system 400 comprises flash memory 402 and error correcting controller 404.Flash memory chip system 400 can be connected with console controller 200 by console controller 200, it to be carried out various access runnings.As mentioned above, console controller 200 has old error correction unit 202, and wherein old error correction unit 202 can provide 1 error bit of error recovery and the ability that detects 2 error bits to data.
The second error correction unit 404f is electrically connected to microprocessor unit 404a and has Error-Correcting Circuit with old error correction unit 202 same error correction capabilities.For example, the second error correction unit 404f can carry out 1 error bit of error recovery/2 of detections error bit to data.In addition, the function of microprocessor unit 404a, the first error correction unit 404b, impact damper 404c, the first flash interface 404d and the second flash interface 404e and structure are to be function and the structure of the microprocessor unit 104a, the first error correction unit 104b, impact damper 104c, the first flash interface 104d and the second flash interface 104e that are same as the first embodiment in essence, below will only describe for difference.
Fig. 5 illustrates the data flow diagram of console controller 200 access flash memory chip systems 400 according to second embodiment of the invention.
Please refer to Fig. 5, when console controller 200 receives by its host computer system the data DATA1 that wants to write, the old error correction unit 202 of console controller 200 can produce old error recovery coding ECC1 according to data DATA1, and console controller 200 can be assigned flash memory chip system 400 and writes instruction and data DATA1 and the old error recovery ECC1 that encodes is sent to flash memory chip system 400.
When the microprocessor unit 404a of error correcting controller 404 receives from console controller 200 when writing instruction, data DATA1 and old error recovery coding ECC1 via the first flash interface 404d, microprocessor unit 404a can learn this access instruction for writing instruction, and data DATA1 and old error recovery coding ECC1 are temporary in impact damper 404c.
In embodiments of the present invention, the second error correction unit 404f can carry out error-correcting routine to data DATA1 according to old error recovery coding ECC1, programme (programming) afterwards console controller 200 can assign manufacturer's instruction, complete if data DATA1 this moment can't be proofreaied and correct by the second error correction unit write fashionable, microprocessor unit 404a can respond console controller 200 data DATA1 and can't be written into, and then console controller 200 just can be programmed once again again.Thus, can also accomplish the operation that correctly writes and proofread and correct to data writing.Then, the first error correction unit 404b can produce new error recovery coding ECC2 ' according to data DATA1.At last, data DATA1 and new error recovery coding ECC2 ' are sent in the physical blocks of flash memory 402.
In addition, from flash memory chip system 400 during reading out data DATA1 and old error recovery coding ECC1, microprocessor unit 404a can be temporary in impact damper 404c with new error recovery coding ECC2 ' and with data DATA1 and new error recovery coding ECC2 ' according to the reading command that comes from console controller 200 reading out data DATA1 from flash memory 402 when console controller 200 wishs.Then, the first error correction unit 404b can be according to the data DATA1 execution error correction program of new error recovery coding ECC2 ' to reading.Afterwards, microprocessor unit 404a can transmit corresponding data to console controller 200 according to the result of error recovery.
Specifically, if the first error correction unit 404b can execution error correction program judge when whether having error bit and data DATA1 in data DATA1 has error bit and attempt error recovery is carried out in error bit.
The data DATA1 that reads when the first error correction unit 404b judgement is when having error bit, the second error correction unit 404f can regenerate old error recovery coding ECC1 according to data DATA1, and microprocessor unit 404a can transmit the data DATA1 that reads with the old error recovery coding ECC1 that regenerates to console controller 200.At this, because the error correcting controller 400 according to the present embodiment does not store old error recovery coding ECC1, so error correcting controller 400 can regenerate by the second error correction unit 404f.
In addition, the data that read when the first error correction unit 404b judgement are deposited DATA1 and are had error bit and this error bit can be by error recovery the time, microprocessor unit 404a is can be after the data DATA1 that receives error recovery from the first error correction unit 404b random among data DATA1 produces error bit, and the data DATA1 that will have an error bit and the old error recovery ECC1 that encodes sends console controller 200 to.Be same as the first embodiment, microprocessor unit 404a produces the data DATA1 with error bit must come error recovery according to old error recovery coding ECC1 by old error correction unit 202, so microprocessor unit 404a can produce the data DATA1 with error bit according to the error correction capability of old error correction unit 202.Similarly, in this example, error correcting controller 400 can regenerate old error recovery coding ECC1 by the second error correction unit 404f foundation data DATA1 of error recovery.
Moreover, the data DATA1 that reads when the first error correction unit 404b judgement has error bit and error bit can't be by error recovery the time, and microprocessor unit 404a default misdata and the default error recovery that can transmit prior storage encoded to console controller 200.Be same as the first embodiment, this default misdata can be judged to be according to this default error coded the error bit that generation can't error recovery by old error correction unit 202.
In the first embodiment, as shown in Figure 2, error correcting controller is carry out error recovery coding and former data and old error recovery coding and new error recovery coding are stored in flash memory containing former data and old error recovery coded data, therefore needs more storage area store simultaneously old error recovery coding and encodes with new error recovery.Yet the flash memory chip system 400 that the second embodiment proposes can be saved simultaneously flash memory stores data required spaces except the function that can reach the first embodiment.Below will coordinate Fig. 6 explanation according to the error correcting method of the embodiment of the present invention.
Fig. 6 illustrates the process flow diagram of error recovery step according to second embodiment of the invention.
Please refer to Fig. 6, receive access instruction and judge that this access instruction is for writing instruction or reading command from console controller 200 in step S601.
If this access instruction is when writing instruction, can be according to old error recovery coding (for example in step S603, old error recovery coding ECC1) to the data that write (for example, data DATA1) carry out error-correcting routine, and produce new error recovery coding (for example, new error recovery coding ECC2 ') according to the data of error recovery in step S605.Afterwards, in step S607, the data of wanting to write and the new error recovery coding that produces are stored in the physical blocks of flash memory 402.
If this access instruction can be according to instruction reading out data (for example, data DATA1) and corresponding new error recovery coding (for example, new error recovery coding ECC2 ') from the physical blocks of flash memory 102 in step S609 for reading money during instruction.
Then, the data that read according to the judgement of new error recovery coding in the step S611 position of whether making a mistake, if judge that in step S611 the data that read are when error bit occurs, regenerate corresponding old error recovery coding according to the data that read in step S613, and send the data that read and the old error recovery coding that regenerates to console controller 200 in step S615.
If judge in step S611 when the data that read make a mistake, in step S617, error bit proofreaied and correct and judge that in step S619 whether this error bit is by error recovery.If when this error bit of judgement is by error recovery in step S619, regenerate corresponding old error recovery coding according to the data of error recovery in step S621, and produce can be by the error bit of console controller 200 error recoverys in the data of error recovery in step S623.Then, send the data of tool error bit and the old error recovery coding that regenerates to console controller 200 in step S625.
If when this error bit of judgement can't be by error recovery in step S619, can will preset misdata and encode with default error recovery and send console controller 200 in step S627.
In sum, the error correcting controller of new flash memory is directly enough supported in the present invention's configuration between the console controller of old system and new flash memory, but makes thus the flash memory of console controller access a new generation of old system.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; have in technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (24)
1. error correcting controller comprises:
The first flash interface is in order to connect console controller;
The second flash interface, in order to connecting flash memory,
Microprocessor unit is electrically connected to described the first flash interface and described the second flash interface;
Make wrong unit, be electrically connected to this microprocessor unit; And
The first error correction unit, be electrically connected to described microprocessor unit, wherein said the first error correction unit can produce the first error recovery coding and described data and described the first error recovery are encoded and be stored in described flash memory when described console controller is wanted data writing to described flash memory
Wherein when described console controller wish reads described data from described flash memory, described microprocessor unit can read described data and described the first error recovery coding from described flash memory, and described the first error correction unit can encode to judge whether the described data that read have at least one error bit and whether described at least one error bit can be by error recovery according to described the first error recovery
The described data that wherein read when described the first error correction unit judgement have described at least one error bit and described at least one error bit can be by error recovery the time, described make wrong unit can produce can by the misdata of error recovery and described microprocessor unit can transmit described can be by the misdata of error recovery to described console controller
Wherein said can be produce and can be come error recovery by described console controller according to the described data that described the first error recovery coding is completed after error recovery by the misdata of error recovery.
2. error correcting controller according to claim 1, the described data that wherein read when described the first error correction unit judgement have described at least one error bit and described at least one error bit can't be by error recovery the time, described microprocessor unit can transmit default misdata to described console controller, and
Wherein said console controller can judge that described default misdata has a plurality of default error bits and described default error bit can't be by error recovery.
3. error correcting controller according to claim 1, wherein said console controller also includes the 3rd error correction unit.
4. error correcting controller according to claim 3, the maximum error recovery figure place of wherein said the 3rd error correction unit is less than the maximum error recovery figure place of described the first error correction unit.
5. error correcting controller according to claim 3, wherein said data also comprise the second error recovery coding.
6. error correcting controller according to claim 5, also comprise the second error correction unit that is electrically connected to this microprocessing unit, the maximum error recovery figure place of wherein said the second error correction unit is the maximum error recovery figure place that is same as described the 3rd error correction unit.
7. error correcting controller according to claim 6, wherein described the second error correction unit can be produced described the second error recovery coding by the data of error recovery according to described when described console controller wish reads described data from described flash memory.
8. error correcting controller according to claim 6, wherein when described console controller wanted to write described data to described flash memory, described the second error correction unit can encode the described data of error recovery according to described the second error recovery.
9. error correcting controller according to claim 1, wherein said microprocessor unit will be stored in about the parameter information of described the first error correction unit in a physical blocks of described flash memory, and described physical blocks is labeled as will damage block.
10. error correcting controller according to claim 1, also comprise data converter, and wherein when described console controller wanted to write described data to described flash memory, described data converter can be changed described data.
11. a flash memory chip system comprises:
Flash memory; And
Error correcting controller is electrically connected to described flash memory, and this error correcting controller comprises:
The first flash interface is in order to connect console controller;
The second flash interface, in order to connecting flash memory,
Microprocessor unit is electrically connected to described the first flash interface and described the second flash interface;
Make wrong unit, be electrically connected to this microprocessor unit; And
The first error correction unit is electrically connected to described microprocessor unit,
Wherein said the first error correction unit can produce the first error recovery coding and described data and described the first error recovery are encoded and be stored in described flash memory when described console controller is wanted data writing to described flash memory,
Wherein when described console controller wish reads described data from described flash memory, described microprocessor unit can read described data and described the first error recovery coding from described flash memory, and described the first error correction unit encodes to judge according to described the first error recovery whether the described data that read have at least one error bit and whether described at least one error bit can be by error recovery
The described data that wherein read when the judgement of described error correcting controller have described at least one error bit and described at least one error bit can be by error recovery the time, described make that wrong unit can transmit can be by the misdata of error recovery to described console controller,
Wherein said can be produce and can be come error recovery by described console controller according to the described data that described the first error recovery coding is completed after error recovery by the misdata of error recovery.
12. flash memory chip system according to claim 11, the described data that wherein read when described the first error correction unit judgement have described at least one error bit and described at least one error bit can't be by error recovery the time, described microprocessor unit can transmit default misdata to described console controller, and
Wherein said console controller can judge that described default misdata has a plurality of default error bits and described default error bit can't be by error recovery.
13. flash memory chip system according to claim 11, wherein this error correcting controller comprises that also the second error correction unit and the described data that are electrically connected to this microprocessing unit also comprise the second error recovery coding.
14. flash memory chip system according to claim 13, wherein described the second error correction unit can regenerate described the second error recovery coding according to described data when described console controller wish reads described data from described flash memory.
15. flash memory chip system according to claim 13, wherein when described console controller wanted to write described data to described flash memory, described the second error correction unit can encode the described data of error recovery according to described the second error recovery.
16. flash memory chip system according to claim 11, wherein said microprocessor unit will be about the correlation parameter information storage in physical blocks of described flash memory, and described physical blocks is labeled as damages block.
17. flash memory chip system according to claim 11, wherein this error correcting controller also comprises data converter, changes described data when the described flash memory in order to want to write described data when described console controller.
18. an error correcting method is applicable to the error recovery console controller to the data of flash memory institute access, described error correcting method comprises:
Produce the first error recovery coding and described data and described the first error recovery coding are stored in described flash memory when described console controller is wanted data writing to described flash memory; And
When described console controller wish reads described data from described flash memory, read described data and described the first error recovery coding and encode to judge according to described the first error recovery whether the described data that read have at least one error bit and whether described at least one error bit can be by error recovery from described flash memory
Wherein have described at least one error bit and described at least one error bit can be by error recovery the time when the described data that read of judgement, transmitting can be by the misdata of error recovery to described console controller,
Wherein said can be produce and can be come error recovery by described console controller according to the described data that described the first error recovery coding is completed after error recovery by the misdata of error recovery.
19. error correcting method according to claim 18 wherein has described at least one error bit and described at least one error bit can't be by error recovery the time when the described data that read of judgement, transmits default misdata to described console controller, and
Wherein said console controller can judge that described default misdata has a plurality of default error bits and described default error bit can't be by error recovery.
20. error correcting method according to claim 18, wherein said data also comprise the second error recovery coding.
21. error correcting method according to claim 20 also comprises when described console controller wish reads described data from described flash memory, console controller encodes the described data of error recovery according to described the second error recovery.
22. error correcting method according to claim 20 wherein wants to write described data to the described flash memory the time when described console controller, encodes the described data of error recovery according to described the second error recovery, and
Wherein in the time can't using described the second error recovery code error to proofread and correct described data, respond to described console controller one error message according to manufacturer's instruction.
23. error correcting method according to claim 18 also comprises parameter information is stored in a physical blocks of described flash memory, and described physical blocks is labeled as damages block.
24. error correcting method according to claim 18 also comprises when described console controller wants to write described data to described flash memory, described data is changed.
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| CN201210349327.0A CN102855943B (en) | 2008-11-28 | 2008-11-28 | Error correction controller, flash memory chip system thereof and error correction method |
| CN 200810182398 CN101752012B (en) | 2008-11-28 | 2008-11-28 | Error correcting controller, flash memory chip system thereof and error correcting method |
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| CN1447242A (en) * | 2002-03-25 | 2003-10-08 | 太和科技股份有限公司 | Control device suitable to quick flash memory card and its construction methods |
| CN101124639A (en) * | 2005-09-30 | 2008-02-13 | 西格马特尔公司 | System and method of accessing non-volatile computer memory |
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| CN1447242A (en) * | 2002-03-25 | 2003-10-08 | 太和科技股份有限公司 | Control device suitable to quick flash memory card and its construction methods |
| CN101124639A (en) * | 2005-09-30 | 2008-02-13 | 西格马特尔公司 | System and method of accessing non-volatile computer memory |
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