CN101751328B - Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM) - Google Patents
Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM) Download PDFInfo
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- CN101751328B CN101751328B CN2008102394996A CN200810239499A CN101751328B CN 101751328 B CN101751328 B CN 101751328B CN 2008102394996 A CN2008102394996 A CN 2008102394996A CN 200810239499 A CN200810239499 A CN 200810239499A CN 101751328 B CN101751328 B CN 101751328B
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Abstract
The invention provides a simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM), which is based on a logical add non-volatile random access memory (NVRAM) combination and belongs to the technical field of intelligent card simulation. A structure and a time sequence based on the FLASH/EEPROM are realized by adopting a logic mode, a mode of a counter is adopted in the logic to realize the time sequence of the FLASH/EEPROM, and various logic signals are realized on the basis of realizing the time sequence of the FLASH/EEPROM.
Description
Technical field
The present invention relates to the intelligent card chip simulation technical field.
Background technology
In the intelligent card chip emulator, can relate to the emulation of FLASH/EEPROM module,
1. before chip is realized, need emulator to realize usually, and also do not have the way of realization of FLASH/EEPROM this moment, particularly as Embedded FLASH/EEPROM module.
2. consider from the compatibility of emulator that the packing forms of FLASH/EEPROM, pin are arranged various, be difficult for assembling realization on same PCB.
A kind of NVRAM of employing that the present invention proposes adds the mode of logical circuit and comes the method for emulation FLASH/EEPROM can solve this type of problem.
Summary of the invention
The function that the present invention adopts NVRAM power down data not lose, the non-volatile characteristic of the data of emulation FLASH/EEPROM; The mode of employing fpga logic and NVRAM combination realizes the emulation of FLASH/EEPROM, pass through logical course, the various states of emulation FLASH/EEPROM, as wipe, programme, write caching of page district, sense data etc., and counter mode regularly, the sequential of the control signal of structure FLASH/EEPROM; When erase operation, force " 1 " is write NVRAM, when programming operation, pass through logical algorithm, promptly utilize data " with " function, when writing data to NVRAM, earlier the data in the NVRAM are read out, do AND-operation with the data that will write, its result is as the data that really write NVRAM, when the data of NVRAM inside were " 0 ", the data perseverance behind the AND-operation was " 0 ", guaranteed that the data that write are " 0 ", when only the data in NVRAM are " 1 ", data behind the AND-operation could with the data consistent that will write, thereby write among the NVRAM, realized that " 0 " function is write in the wiping " 1 " of FLASH/EEPROM.Simultaneously, adopt the function in the caching of page district of FPGA internal RAM emulation FLASH/EEPROM.
Description of drawings
Fig. 1 adds the block diagram that logical circuit is realized FLASH/EEPROM emulation based on NVRAM
Fig. 2 is used for the logical circuit of emulation FLEASH/EEPROM temporal characteristics
Fig. 3 state enable signal sequential chart
Fig. 4 page or leaf programming number time sequential routine figure
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
A kind of FLASH/EEPROM emulation mode based on NVRAM disclosed in this invention can be preserved data characteristic, the data hold function of emulation FLASH/EEPROM after utilizing the NVRAM power down; By logical circuit, come the wiping of emulation FLASH/EEPROM, program timing sequence; Adopt the caching of page district of FPGA internal RAM emulation FLASH/EEPROM; " 0 " function is write in wiping " 1 " with FPGA internal logic realization FLASH/EEPROM.
Logical circuit is described below:
Design a counting logic, as shown in Figure 2, no matter be erase operation or programming operation, the address signal of NVRAM is produced simultaneously by the output signal and the outside Input Address signal of counter, read-write according to the counter meter time certain, produce in conjunction with the Mbus signal, it is fixed that the concrete time can require according to the sequential of FLASH/EEPROM.Also design the caching of page district of an inside simultaneously, be used to deposit page or leaf or half page of data programmed, when carrying out programming operation, read the data in caching of page district earlier, write NVRAM again.
Under the effect of system clock and mode select signal, produce the Status Flag signal (as: page or leaf or half page wipe or programming state, write the caching of page zone state) of various operations by state machine generative circuit module.Designing a counter circuit, when the program enable signal is effective Mbus is counted, is basically under some Status Flags, when counter arrives certain value, produces corresponding state enable signal.Sequential chart as shown in Figure 3.
Enable the valid period at state, the address generator module is with counter output valve and outside Input Address signal combination, produce the address signal of NVRAM and the page address signal in caching of page district, the rule of combination of NVRAM address signal is least-significant byte address (the page operations mode of the output valve calculated address of counter, be 256 bytes) or low 7 bit address (half page mode, be 128 bytes), other high position of outside Input Address calculated address.The rule of combination of caching of page regional address signal is 8 bit address of counter output.
Read-write maker module produces the read-write of NVRAM and the read signal in caching of page district according to the output signal and the state enable signal of counter.
Enable the valid period at state, if Status Flag is erase operation (page or leaf or half page), the data of then exporting to NVRAM are " 1 ".Realize wiping " 1 " function of FLASH/EEPROM.
Enable the valid period at state, if Status Flag is programming operation (page or leaf or half page), when the address generator module is exported the address of a NVR, also export a caching of page regional address, meanwhile, read-write maker module is simultaneously output page read signal and NVR read signal also, reads value in the caching of page district and the data of NVRAM, two data are done AND operation in data conversion module, as the data that will write NVRAM.Realize to write " 0 " among the FLASH/EEPROM function that can not one writing.The write signal of last read-write maker module output NVRAM.The output data of data conversion module is write NVRAM.Sequential as shown in Figure 4.
The value in caching of page district writes external data by write signal in advance under corresponding mode of operation.
Claims (4)
1. FLASH/EEPROM emulation mode based on NVRAM, it is characterized in that adopting the mode of fpga logic and NVRAM combination to realize the emulation of FLASH/EEPROM, can preserve data characteristic after utilizing the NVRAM power down, the data hold function of emulation FLASH/EEPROM; By logical circuit, the wiping of emulation FLASH/EEPROM, program timing sequence; Adopt the page buffer of FPGA internal RAM emulation FLASH/EEPROM; " 0 " function is write in wiping " 1 " with FPGA internal logic realization FLASH/EEPROM; Step is as follows:
(1) under the effect of system clock and mode select signal, produce the Status Flag signal of various operations by state machine generative circuit module, counter circuit is counted Mbus when the program enable signal is effective, when counter arrives certain value, produces corresponding state enable signal;
(2) enable the valid period at state, the address generator module produces the address signal of NVRAM and the page address signal in caching of page district with counter output valve and outside Input Address signal combination;
(3) enable the valid period at state, read-write maker module time certain, produces the read-write of NVRAM and the read signal in caching of page district in conjunction with the Mbus signal according to the counter meter;
(4) the caching of page district of an inside of design is used to deposit page or leaf or half page of data programmed, when carrying out programming operation, reads the data in caching of page district earlier, writes NVRAM again;
(5) wipe the function that " 1 " writes " 0 " for realizing, before data write NVRAM, the data that the data of NVRAM are read earlier and will be write are done AND-operation, again the data behind the AND-operation are write NVRAM.
2. a kind of FLASH/EEPROM emulation mode as claimed in claim 1 based on NVRAM, it is characterized in that enabling the valid period at state, if Status Flag is an erase operation, the data of then exporting to NVRAM are " 1 ", realize wiping " 1 " function of FLASH/EEPROM.
3. a kind of FLASH/EEPROM emulation mode as claimed in claim 1 based on NVRAM, it is characterized in that enabling the valid period at state, if Status Flag is a programming operation, when the address generator module is exported the address of a NVR, also export a caching of page regional address, read-write maker module is while output page read signal and NVR read signal also, read value in the caching of page district and the data of NVRAM, two data are done AND operation in data conversion module, as the data that will write NVRAM, the write signal of last read-write maker module output NVRAM, the output data of data conversion module is write NVRAM, realized that FLASH/EEPROM can only write the function that " 0 " can not one writing.
4. a kind of FLASH/EEPROM emulation mode as claimed in claim 1 based on NVRAM, it is characterized in that in the counting region of counter, set the read-write that just produces NVRAM when the counter meter to the regular hour, the sequential of control read-write reaches consistent with real FLASH/EEPROM sequential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2008102394996A CN101751328B (en) | 2008-12-12 | 2008-12-12 | Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM) |
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| CN2008102394996A CN101751328B (en) | 2008-12-12 | 2008-12-12 | Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM) |
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| CN101751328A CN101751328A (en) | 2010-06-23 |
| CN101751328B true CN101751328B (en) | 2011-07-27 |
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| CN104102521A (en) * | 2014-07-25 | 2014-10-15 | 浪潮(北京)电子信息产业有限公司 | Method and device for updating nonvolatile storage |
| CN107944128B (en) * | 2017-11-21 | 2021-03-19 | 上海航天测控通信研究所 | FLASH bad block simulation verification system based on storage control FPGA |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632759A (en) * | 2003-12-24 | 2005-06-29 | 上海华虹集成电路有限责任公司 | Method capable of smartly implementing EEPROM simulation function in chip |
| CN2831248Y (en) * | 2005-06-08 | 2006-10-25 | 上海华虹集成电路有限责任公司 | Internal nonvolatile memory copying system of chip |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1632759A (en) * | 2003-12-24 | 2005-06-29 | 上海华虹集成电路有限责任公司 | Method capable of smartly implementing EEPROM simulation function in chip |
| CN2831248Y (en) * | 2005-06-08 | 2006-10-25 | 上海华虹集成电路有限责任公司 | Internal nonvolatile memory copying system of chip |
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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building, Patentee after: Beijing CEC Huada Electronic Design Co., Ltd. Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer Patentee before: Beijing CEC Huada Electronic Design Co., Ltd. |
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