CN101751226A - Non-volatile memory medium controller and non-volatile memory device - Google Patents
Non-volatile memory medium controller and non-volatile memory device Download PDFInfo
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- CN101751226A CN101751226A CN200810241302A CN200810241302A CN101751226A CN 101751226 A CN101751226 A CN 101751226A CN 200810241302 A CN200810241302 A CN 200810241302A CN 200810241302 A CN200810241302 A CN 200810241302A CN 101751226 A CN101751226 A CN 101751226A
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Abstract
The invention discloses a non-volatile memory medium controller and a non-volatile memory device. In the invention, a secondary processing host instruction method is adopted, namely, a co-processor is arranged in a control module of a controller to analyze a medium control instruction into a medium operation instruction, and configuration information (characteristic information, etc.) of a non-volatile memory medium is configured and stored in a read-only memory of the memory device beforehand, thereby greatly improving the configurability of the controller and the memory device and instruction processing efficiency. In addition, the parallel processing among the multiple control modules and the parallel processing of a medium chip instruction are realized by arranging a plurality of control modules in the controller and an instruction cache mechanism in the multiple control modules, thereby realizing high speed of medium operation and data transmission.
Description
Technical field
The present invention relates to the compatible control technology of non-volatile memory medium.
Background technology
Popularization gradually along with all kinds of non-volatile memory mediums application, increasing all kinds of dielectric chip manufacturer emerges, because different its technology of manufacturer and design and mode of operation are all slightly variant, even the steering order of using in the design that all can cause product owing to causes such as product up-gradation of the products of different batches of identical manufacturer and the product all is different.Therefore, this type of situation brings very big challenge and problem for the device fabrication of rear end and the manufacturer of product application.One is exactly the problem of Products Compatibility, and the device fabrication merchant of rear end expects that this class memory medium controller that its product uses has good compatibility, can compatible many tame storage mediums.Like this, will make equipment have more selection, can take all factors into consideration multiple factors such as the performance of each tame product and price, perhaps use different products to obtain the equipment of different size or the equipment of different prices.Its two, therefore the equipment of different series need use the storage medium of different size, faces different methods of operating.For example: use the SLC series of products (Single-Level Cell, single layer cell flash memory) of NANDFlash and the MLC series of products (Multi-Level Cell, multi-layered unit flash memory) of NAND Flash.What SLC and MLC adopted is two kinds of dissimilar NAND Flash storage mediums, and in general, SLC is better than MLC performance, and high-end product is generally done with SLC by manufacturer, and MLC is used for doing low-end product.But need use different controller chips to control for these two kinds of storage mediums, and the instruction of using and operation all have very big difference.Its three, the equipment of different series may face the storage medium of different sizes and configuration, for example, the memory device of different capabilities, the array scale of its storage medium or the capacity of single medium are different.
For the device fabrication merchant, the expense of a memory medium controller chip of exploitation is quite expensive, generally need hundreds of thousands even U.S. dollar up to a million easily, therefore, if control chip does not possess very strong compatibility, its scope of application is narrower, when the manufacturer considers to change to the storage medium chip of other manufacturer's storage medium chips or other types, just be faced with and need develop a control chip again, this expense is quite expensive.Certainly, perhaps there are some manufacturers to consider this type of compatibility issue, therefore adopt method commonly used in the traditional IC design, promptly in the IC design process, add some configurable circuit design, some expanded functions or interlock circuit design are added in the control chip, dispose the circuit selection of IC chip, thereby reach the purpose of control chip compatibility according to product needed.Certainly, do like this and also can satisfy manufacturer about requirement to storage medium chip compatibility, but, use this type of solution, need to design a large amount of configurable hardware circuits in the control chip, could satisfy different manufacturers or all types of dielectric chips, this just means that each control chip has in use all only used a part wherein, and an other part is not configured to use, just be wasted.The price of chip and the design scale of chip chip size in other words are directly proportional, and each chips all means the price of having wasted a lot of parts.Therefore, though this method can reach compatible purpose, also can satisfy simultaneously the demand that control chip of business men man use satisfies multiple different rear end storage medium chip, but, this method is that the price with controller chip is a cost, improve the price of control chip significantly, caused very big waste.
Summary of the invention
The present invention is directed in the prior art non-volatile memory medium controller problem of compatible multiple non-volatile memory medium cheaply, proposed a kind of mode that does not need additionally to increase configuration circuit and just can realize the different non-volatile storage medium is carried out compatible non-volatile memory medium controller and non-volatile memory apparatus.
The non-volatile memory medium controller that the present invention adopts comprises at least one control module, and each control module is controlled one group of non-volatile memory medium; At least comprise in the control module: coprocessor, data-carrier store; The medium steering order that described coprocessor is used for the receiving equipment main control processor after resolving, and the medium steering order is resolved to the media operation instruction be issued in the corresponding non-volatile memory medium; Described data-carrier store is connected with corresponding one group of non-volatile memory medium with the equipment buffer memory respectively, and described coprocessor control data-carrier store is finished the transmission of data between equipment buffer memory and non-volatile memory medium.
Preferably, also comprise first random access memory in the described control module, be used for the medium steering order after buffer memory equipment main control processor is resolved, described coprocessor extracts steering order and carries out dissection process from first random access memory.
Preferably, also comprise second random access memory in the described control module, be used for the operational order that when corresponding non-volatile memory medium work of treatment state buffer memory coprocessor parses this medium.
The invention allows for a kind of non-volatile memory apparatus, except comprising above-mentioned non-volatile memory medium controller, also comprise: interface controller, ROM (read-only memory), main control processor, ROM (read-only memory), buffer unit, non-volatile memory medium.Described ROM (read-only memory) also is used to store the configuration information of described non-volatile memory medium, and described main control processor resolves to the medium steering order according to this characteristic information of storing in the ROM (read-only memory) with host command.
The non-volatile memory medium that uses among the present invention can be flash chip, for example NAND type flash chip etc.
The present invention is owing to be provided with coprocessor in control module, and be responsible for that by coprocessor the medium steering order is resolved to media operation and instruct, the configuration information of non-volatile memory medium such as characteristic information etc. are configured in advance and are stored in the ROM (read-only memory) of memory device, and the mode of this two stage treatment host command has improved the configurability and the work efficiency of controller and memory device greatly.
Can resolve and send the medium steering order successively in the course of the work owing to coprocessor in addition, when the corresponding medium of instruction is in running order, coprocessor can be deposited in the instruction after resolving in second random access memory earlier, and instruction that continue to carry out other media resolves and sends and buffer memory, the raising of this very big degree the work efficiency of controller and the speed of media operation.
All right integrated a plurality of control modules have simultaneously then comprised a plurality of coprocessors in the controller of the present invention in the controller, and each module all is the independent parallel operation each other, have significantly improved the transfer rate of instruction of medium controller and dielectric chip and data.
Description of drawings
Fig. 1 is a non-volatile memory medium control module preferred embodiment schematic diagram of the present invention;
Fig. 2 is a non-volatile memory medium controller preferred embodiment schematic diagram of the present invention;
Fig. 3 is a non-volatile memory apparatus preferred embodiment structured flowchart of the present invention.
Embodiment
Below in conjunction with accompanying drawing and by specific embodiment realization of the present invention is elaborated.
Non-volatile memory medium control module structure principle chart as shown in Figure 1, in the present embodiment in the non-volatile memory medium control module 150 except comprising: coprocessor 1503 and the data-carrier store 1502, also comprise: first random access memory 1501 and second random access memory 1504.The instruction that host computer system is sent is sent to main control processor 13 by interface controller, main control processor is according to the medium configuration information of storage in the ROM (read-only memory) 12, for example: the instruction manipulation information of the array features of flash media, flash media etc., host command is resolved to corresponding medium steering order send in first random access memory 1501 in the control module 150 and carry out buffer memory, wherein first random access memory 1501 can select to adopt dynamic RAM.In 1503 pairs first random access memory 1501 of coprocessor the medium steering order further instructed parsing, resolve to the media operation instruction and send in the corresponding storage medium 1601,1602,1603,1604.When the storage medium of correspondence was in running order, the media operation Instructions Cache after coprocessor 1503 will be resolved was in second random access memory 1504, and second random access memory 1504 can adopt dynamic RAM.And when the storage medium of correspondence is in idle condition, successively operational order is issued the purpose storage medium.Comprise a plurality of storage mediums in 160, one non-volatile memory medium groups 160 of non-volatile memory medium control module 150 non-volatile memory medium groups of control in the present embodiment.Also can save first random access memory 1501 in the present embodiment under situation about simplifying or/and second random access memory 1504, this way has promptly been saved the buffering of instruction.Coprocessor 1503 is by the transmission of control data storer 1502 control datas.
Non-volatile memory medium controller preferred embodiment as shown in Figure 2, comprise a plurality of non-volatile memory medium control modules 150,151,152 in the non-volatile memory controller 15, the non-volatile memory medium group 160,161,162 in each non-volatile memory medium control module 150,151,152 corresponding control non-volatile memory medium unit 16.The main control processor 13 of memory device carries out instruction interaction by a plurality of coprocessors in control bus and the controller 15, buffer unit carries out data transmission by the data-carrier store of each coprocessor in data bus and the controller 15, each unit module is as shown in Figure 1 all arranged in each non-volatile memory medium control module 150,151,152, and the operator scheme of its each unit is consistent with corresponding unit principle of work among Fig. 1.But the storage medium array of each non-volatile memory medium control module 150,151,152 rear ends control storage medium chip in other words might be different.Be that main control processor 13 is by reading corresponding configuration information in the ROM (read-only memory) 12, in course of normal operation, main control processor 13 is accepted after the host command, characteristics correspondence according to the storage medium configuration information resolves to the medium steering order with host command, and promptly coprocessor resolves to the steering order that coprocessor can further be resolved.This steering order is sent in first random access memory in the corresponding medium control module 150,151,152 and deposits.Coprocessor is further resolved the steering order in first random access memory, when the corresponding stored medium is in idle condition, operational order after coprocessor will be resolved sends to the corresponding stored medium, when the corresponding stored medium is in running order, coprocessor with Instructions Cache in second random access memory, continue to resolve the steering order of corresponding other storage mediums simultaneously, and the instruction of other corresponding stored media is sent or buffer memory according to its state.Be complete parallel work-flow between all coprocessors, do not have the feedback of multiplexing or state simultaneously between the coprocessor nuclear, can not influence the independence of work each other; In addition, the storage medium under each coprocessor control also is an independent operation after accepting instruction, also is the operation that walks abreast each other.
Memory device structured flowchart as shown in Figure 3, non-volatile memory apparatus 1 comprises: interface controller 11, ROM (read-only memory) 12, main control processor 13, buffer unit 14, non-volatile memory medium controller 15, non-volatile memory medium unit 16.Wherein non-volatile memory medium controller 15 can be single coprocessor architectures shown in Figure 1, also can be the structure of a plurality of coprocessors shown in Figure 2.The configuration information of non-volatile memory medium is stored in the ROM (read-only memory) 12, and ROM (read-only memory) 12 is gone back memory device operation firmware information.Buffer unit 14 is used for buffer memory command information and data message.Interface controller 11 links to each other with host computer system 2, is used to transmit the host computer control instruction.
Non-volatile memory medium among the above embodiment can be a flash memory, for example nand flash memory etc.
Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. a non-volatile memory medium controller is characterized in that, comprises at least one control module, and each control module is controlled one group of non-volatile memory medium; Described control module comprises at least: coprocessor, data-carrier store; The medium steering order that described coprocessor is used for the receiving equipment main control processor after resolving, and the medium steering order is resolved to the media operation instruction be issued in the corresponding non-volatile memory medium; Described data-carrier store is connected with corresponding one group of non-volatile memory medium with the equipment buffer memory respectively, and described coprocessor control data-carrier store is finished the transmission of data between equipment buffer memory and non-volatile memory medium.
2. non-volatile memory medium controller according to claim 1, it is characterized in that, also comprise first random access memory in the described control module, be used for the medium steering order after buffer memory equipment main control processor is resolved, described coprocessor extracts steering order and carries out dissection process from first random access memory.
3. non-volatile memory medium controller according to claim 1 and 2, it is characterized in that, also comprise second random access memory in the described control module, be used for the operational order that when corresponding non-volatile memory medium work of treatment state buffer memory coprocessor parses this medium.
4. non-volatile memory medium controller according to claim 1 and 2 is characterized in that, described non-volatile memory medium is a flash chip.
5. non-volatile memory medium controller according to claim 3 is characterized in that, described non-volatile memory medium is a flash chip.
6. non-volatile memory apparatus, comprise: interface controller, ROM (read-only memory), main control processor, non-volatile memory medium controller, ROM (read-only memory), buffer unit, non-volatile memory medium unit, it is characterized in that, described ROM (read-only memory) also is used to store the configuration information of described non-volatile memory medium, and described main control processor resolves to the medium steering order according to this characteristic information of storing in the ROM (read-only memory) with host command; Described non-volatile memory medium controller comprises at least one control module, and each control module is controlled one group of non-volatile memory medium; Described control module comprises at least: coprocessor, data-carrier store; The medium steering order that described coprocessor is used for the receiving equipment main control processor after resolving, and the medium steering order is resolved to the media operation instruction be issued in the corresponding non-volatile memory medium; Described data-carrier store is connected with corresponding one group of non-volatile memory medium with the equipment buffer memory respectively, and described coprocessor control data-carrier store is finished the transmission of data between equipment buffer memory and non-volatile memory medium.
7. non-volatile memory apparatus according to claim 6, it is characterized in that, also comprise first random access memory in the described control module, be used for the medium steering order after buffer memory equipment main control processor is resolved, described coprocessor extracts steering order and carries out dissection process from first random access memory.
8. according to claim 6 or 7 described non-volatile memory apparatus, it is characterized in that, also comprise second random access memory in the described control module, be used for the operational order that when corresponding non-volatile memory medium work of treatment state buffer memory coprocessor parses this medium.
9. according to claim 6 or 7 described non-volatile memory apparatus, it is characterized in that described non-volatile memory medium is a flash chip.
10. non-volatile memory apparatus according to claim 8 is characterized in that, described non-volatile memory medium is a flash chip.
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| CN200810241302A CN101751226A (en) | 2008-12-08 | 2008-12-08 | Non-volatile memory medium controller and non-volatile memory device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222055A (en) * | 2011-06-02 | 2011-10-19 | 钟浩 | Device and method for improving running speed of high-capacity solid data memory system |
| CN104778069A (en) * | 2015-04-30 | 2015-07-15 | 杭州华三通信技术有限公司 | Electronic equipment and method for starting and uploading of electronic equipment |
| CN105094752A (en) * | 2015-09-21 | 2015-11-25 | 中国科学院自动化研究所 | Instruction buffering and aligning buffering device and operation method thereof |
| CN107291379A (en) * | 2016-03-03 | 2017-10-24 | 三星电子株式会社 | Accumulator system and its control method |
| CN110990301A (en) * | 2019-11-15 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Sequential reading method of multi-plane storage medium and related device |
| US11294571B2 (en) | 2016-03-03 | 2022-04-05 | Samsung Electronics Co., Ltd. | Coordinated in-module RAS features for synchronous DDR compatible memory |
-
2008
- 2008-12-08 CN CN200810241302A patent/CN101751226A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222055A (en) * | 2011-06-02 | 2011-10-19 | 钟浩 | Device and method for improving running speed of high-capacity solid data memory system |
| CN104778069A (en) * | 2015-04-30 | 2015-07-15 | 杭州华三通信技术有限公司 | Electronic equipment and method for starting and uploading of electronic equipment |
| CN104778069B (en) * | 2015-04-30 | 2018-02-09 | 新华三技术有限公司 | Electronic equipment and the method for electronic equipment start-up loading |
| CN105094752A (en) * | 2015-09-21 | 2015-11-25 | 中国科学院自动化研究所 | Instruction buffering and aligning buffering device and operation method thereof |
| CN105094752B (en) * | 2015-09-21 | 2018-09-11 | 中国科学院自动化研究所 | Instruction buffer be aligned buffer unit and its operating method |
| CN107291379A (en) * | 2016-03-03 | 2017-10-24 | 三星电子株式会社 | Accumulator system and its control method |
| US11294571B2 (en) | 2016-03-03 | 2022-04-05 | Samsung Electronics Co., Ltd. | Coordinated in-module RAS features for synchronous DDR compatible memory |
| CN110990301A (en) * | 2019-11-15 | 2020-04-10 | 苏州浪潮智能科技有限公司 | Sequential reading method of multi-plane storage medium and related device |
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Application publication date: 20100623 |