CN101404492A - Method, apparatus and system for loading field programmable gate array - Google Patents
Method, apparatus and system for loading field programmable gate array Download PDFInfo
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- CN101404492A CN101404492A CNA2008101809041A CN200810180904A CN101404492A CN 101404492 A CN101404492 A CN 101404492A CN A2008101809041 A CNA2008101809041 A CN A2008101809041A CN 200810180904 A CN200810180904 A CN 200810180904A CN 101404492 A CN101404492 A CN 101404492A
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Abstract
The invention discloses a method for loading a field programmable gate array, a device and a system thereof, and belongs to the field of electronic circuit. The method includes: starting a loading flow; judging whether all the field programmable gate arrays in a preset delay time are responded or not; if the judging result is that all the field programmable gate arrays are responded, then loading a plurality of field programmable gate arrays in parallel. The device comprises a starting module, a judging module and a loading module. The system comprises a loading controller and a plurality of field programmable gate arrays. The invention leads the needed total loading time to be shortened by loading the field programmable gate arrays in parallel when a plurality of field programmable gate arrays are loaded; moreover, the data output capacity of the existing system can be fully used.
Description
Technical field
The present invention relates to electronic circuit field, particularly a kind of methods, devices and systems of loading field programmable gate array.
Background technology
FPGA (Field Programmable Gate Array, field programmable gate array) is a kind of important programmable logic device, it generally adopts SRAM (Static Random Access Memory, static random access memory) technology, integrated level is very high, can finish extremely complicated sequential and combinational logic circuit function.FPGA is widely used in communication equipment, complex digital circuitry fields such as automotive electronics at present.For the digital circuitry with FPGA design, because the configuration information of FPGA is stored among its inner SRAM, and SRAM belongs to the storage medium of power down volatibility.Therefore in digital circuitry electrifying startup process, it is indispensable one procedure that the configuration information of FPGA is loaded.Existing high-end FPGA scale is increasing, and its configuration information amount is also increasing thereupon, and new change is not taken place the method that the configuration information of FPGA loads, therefore to single FPGA time of loading of configuration information will be more and more longer thereupon.And in the existing digital circuitry design, it is very common adopting a plurality of large-scale F PGA to carry out system design.So, when system design, must consider how effectively to shorten load time of a plurality of FPGA.
Referring to Fig. 1, the schematic diagram that the configuration information of a plurality of FPGA is loaded for prior art, as can be seen from the figure: loading data (configuration information of FPGA) only takies GPIO (the General PurposeInput/Output Port of loading control 8bit (bit), general purpose I/O interface), loading control generally is system CPU (Central Processing Unit, central processing unit) or CPU module; All FPGA that are loaded use the serial load mode, and the 8bit loading data interface of all FPGA is multiplexing, and other Loading Control lines are independently.This hardware topology has determined must carry out successively the loading of a plurality of FPGA, be that loading data is exported successively/read back by the public GPIO of 8bit, and in the design of existing complex digital circuitry system, the application of 32bit processor has become main flow, and this class processor generally has the GPIO of 32bit bit wide or can expand the GPIO interface of 32bit even wideer bit wide by other buses and bridge joint device.
In realizing process of the present invention, the inventor finds that there is following problem at least in prior art:
When 1) loading a plurality of FPGA, the total load time that needs is long.
2) the existing system data fan-out capability is not fully utilized.
Summary of the invention
Load total load time that a plurality of FPGA need in order to reduce, the embodiment of the invention provides a kind of methods, devices and systems of loading field programmable gate array.Described technical scheme is as follows:
On the one hand, the embodiment of the invention provides a kind of method of loading field programmable gate array, and described method comprises:
The start-up loading flow process;
Judge whether a plurality of field programmable gate arrays all have response in the default delay time;
If judged result is described a plurality of field programmable gate array response is arranged all, then the described a plurality of field programmable gate arrays of loaded in parallel.
On the other hand, the embodiment of the invention provides a kind of device of loading field programmable gate array, and described device comprises:
Start module, be used for the start-up loading flow process;
Judge module, be used for described startup module start-up loading flow process after, judge whether a plurality of field programmable gate arrays all have response in the default delay time;
Load-on module, the judged result that is used for when described judge module is after described a plurality of field programmable gate array all has response, the described a plurality of field programmable gate arrays of loaded in parallel.
On the other hand, the embodiment of the invention provides a kind of system of loading field programmable gate array, and described system comprises:
Loading control and a plurality of field programmable gate array;
Described loading control is used for the start-up loading flow process; Judge whether described a plurality of field programmable gate arrays all have response in the default delay time; If judged result is described a plurality of field programmable gate array response is arranged all, then the described a plurality of field programmable gate arrays of loaded in parallel.
The beneficial effect of the technical scheme that the embodiment of the invention provides is:
By a plurality of field programmable gate arrays of loaded in parallel, when make loading a plurality of field programmable gate array, the total load time that needs shortens; And, also make the existing system data fan-out capability be fully used.
Description of drawings
Fig. 1 is the schematic diagram that prior art loads a plurality of FPGA;
Fig. 2 is the method flow diagram of a kind of loading field programmable gate array of providing of the embodiment of the invention 1;
Fig. 3 is the method flow diagram of the another kind of loading field programmable gate array that provides of the embodiment of the invention 1;
Fig. 4 is the method flow diagram of another loading field programmable gate array of providing of the embodiment of the invention 1;
Fig. 5 is the device schematic diagram of a kind of loading field programmable gate array of providing of the embodiment of the invention 2;
Fig. 6 is the system schematic of a kind of loading field programmable gate array of providing of the embodiment of the invention 3;
Fig. 7 is a kind of loading control that provides of the embodiment of the invention 3 and the annexation schematic diagram of a plurality of field programmable gate arrays;
Fig. 8 is a kind of loading control that provides of the embodiment of the invention 3 and the annexation schematic diagram of a plurality of field programmable gate arrays.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
One group of GPIO that the embodiment of the invention is chosen in the loading control exports loading datas to a plurality of FPGA simultaneously, choose other in the loading control one group or several groups of GPIO and realize Loading Control signal and clock output etc., the number of the FPGA that can load as required in the practical application decides which the group GPIO that specifically chooses in the loading control, for example:, can choose the one group of GPIO in the loading control so more than or equal to the 4*8 bit wide if 4 FPGA are arranged; If n FPGA arranged, can choose the one group of GPIO in the loading control so more than or equal to the n*8 bit wide.
Need to prove, may not reach the GPIO group of n*8 bit wide in the practical application in the loading control, but also can export loading data to n FPGA, specifically how realize, will be described in detail in the following embodiments with the method for the embodiment of the invention.
For convenience of description, the described loading control bit wide of the embodiment of the invention is meant the one group of GPIO that is used for exporting to n FPGA loading data in the loading control of choosing.
Embodiment 1
The embodiment of the invention provides a kind of method of loading field programmable gate array, as shown in Figure 2, comprising:
201: the start-up loading flow process;
202: judge whether a plurality of field programmable gate arrays all have response in the default delay time;
203: if judged result is a plurality of field programmable gate arrays response is arranged all, then a plurality of field programmable gate arrays of loaded in parallel.
When loading control bit wide during more than or equal to the total bit wide of a plurality of field programmable gate arrays, a plurality of field programmable gate arrays of above-mentioned loaded in parallel specifically comprise:
The sheet choosing of a plurality of field programmable gate arrays is enabled;
Read loading data, output loading data, and the bat of output clock, rising edge or the trailing edge clapped at clock load data into described a plurality of field programmable gate array;
Whether judge has field programmable gate array to load unusually in a plurality of field programmable gate arrays;
If there do not have field programmable gate array to load in a plurality of field programmable gate arrays to be unusual, judge that whether having field programmable gate array to load in a plurality of field programmable gate arrays finishes;
Finish if there is field programmable gate array to load in a plurality of field programmable gate arrays, to judge whether that a plurality of field programmable gate arrays all load to finish;
If a plurality of field programmable gate arrays all load and finish, finish to load.
Further comprise:
All load if not a plurality of field programmable gate arrays and to finish, the sheet that then will load completed field programmable gate array selects forbidden energy, carries out loaded in parallel to loading uncompleted field programmable gate array.
When loading control bit wide during less than the total bit wide of a plurality of field programmable gate arrays, a plurality of field programmable gate arrays of above-mentioned loaded in parallel specifically comprise:
The sheet choosing of field programmable gate array to be loaded in a plurality of field programmable gate arrays is enabled;
Read loading data, output loading data, and the bat of output clock, rising edge or the trailing edge clapped at clock load data into field programmable gate array to be loaded;
Whether judge has field programmable gate array to load unusually in the field programmable gate array to be loaded;
If there do not have field programmable gate array to load in the field programmable gate array to be loaded to be unusual, judge that whether having field programmable gate array to load in the field programmable gate array to be loaded finishes;
Finish if there is field programmable gate array to load in the field programmable gate array to be loaded, judge whether field programmable gate array is to be loaded in addition under the passage that loads the field programmable gate array of finishing;
Do not have field programmable gate array to be loaded if load under the passage of the field programmable gate array finish, judge whether that a plurality of field programmable gate arrays all load to finish;
If a plurality of field programmable gate arrays all load and finish, finish to load.
Further comprise:
All load if not a plurality of field programmable gate arrays and to finish, the sheet that then will load completed field programmable gate array selects forbidden energy, carries out loaded in parallel to loading uncompleted field programmable gate array.
Further comprise:
Have field programmable gate array to be loaded if load under the passage of the field programmable gate array finish, the sheet of the field programmable gate array that loading is finished selects forbidden energy;
Field programmable gate array to be loaded under the passage of the field programmable gate array that loading is finished carries out loaded in parallel.
Below in conjunction with different scenes the embodiment of the invention is described in detail:
First kind of scene: the loading control bit wide is more than or equal to n*8bit, and n is for needing the FPGA of loading, and n is the natural number greater than 1, and just the loading control bit wide is more than or equal to total bit wide of a plurality of FPGA.In this scene, be 32bit with the loading control bit wide, needing the FPGA of 4 8bit of loading is that example is described in detail, and as shown in Figure 3, the method for loading field programmable gate array comprises:
301: the start-up loading flow process.
302: judge whether 4 FPGA all have response in default delay time, if judged result is that 4 FPGA have response in delay time, then carry out 305; Otherwise, carry out 303.
In the present embodiment, it is the FPGA zero clearing that FPGA has the sign of response, if the sign of 4 FPGA all is zero clearing, then judged result is that 4 FPGA have response, if wherein the sign of at least 1 FPGA is not zero clearing, then judged result is not response.
303: judge whether to surpass delay time,, then carry out 304 if judged result is to surpass delay time; Otherwise, carry out 302.
304: ignore the FPGA that does not have response, carry out 305 then, perhaps directly carry out 313.
305: the FPGA that choosing enables or sheet choosing is enabled to the FPGA sheet keeps its sheet to select enabled state.
Need to prove that it specifically is that FPGA sheet choosing to be loaded enables that FPGA sheet choosing is enabled, and specifically is that 4 FPGA sheets choosings are enabled, and to the FPGA that sheet choosing enables, when carrying out this step once more, is the maintenance of the FPGA sheet being selected enabled state herein.
306: read loading data, export with the 4*8bit bit wide.
The data that are used to load 4 FPGA are two files that generate according to 4 original loading data files of FPGA:
File one is a large data files that utilizes the original loading data file generation of 4 FPGA, and each word length is 32bit in the file one, and the form of file one is as shown in table 1:
Table 1
| First " word " | Second " word " | The 3rd " word " | …… | I " word " | …… | M " word " | |
| 1 | 8bit | 8bit | 8bit | …… | 8bit | …… | 8bit |
| 2 | 8bit | 8bit | 8bit | …… | The 8bit padding data [1] | …… | The 8bit padding data [1] |
| 3 | 8bit | 8bit | 8bit | …… | 8bit | …… | The 8bit padding data [1] |
| 4 | 8bit | 8bit | 8bit | …… | 8bit | …… | The 8bit padding data [1] |
In the table 1, m is a length value of getting the maximum length of 4 original loading datas among the FPGA, can guarantee like this that loading data among each FPGA can both be loaded to finish; 1,2,3,4 respectively corresponding a FPGA, the 2nd FPGA, the 3rd FPGA, the 4th FPGA; 8bit is the loading data of respectively corresponding a FPGA, the 2nd FPGA, the 3rd FPGA, the 4th FPGA; The 8bit padding data
[1]Be shorter when corresponding FPGA loading data, the extraneous data that continues to send after the data load of corresponding FPGA is finished can arbitrarily be filled, but in order to guarantee the readability of file, recommends to use 00, fixed data shapes fillings such as FF, 55, AA.For example: 4 FPGA are arranged, it is 5*8bit that the one FPGA needs loading data, and it is 3*8bit that the 2nd FPGA needs loading data, and it is 4*8bit that the 3rd FPGA needs loading data, it is 2*8bit that the 4th FPGA needs loading data, and this moment, corresponding file one was as shown in table 2 so:
Table 2
| First " word " | Second " word " | The 3rd " word " | The 4th " word " | The 5th " word " | |
| 1 | 8bit | 8bit | 8bit | 8bit | 8bit |
| 2 | 8bit | 8bit | 8bit | FF | FF |
| 3 | 8bit | 8bit | 8bit | 8bit | FF |
| 4 | 8bit | 8bit | FF | FF | FF |
File two is data files describing the loading data length of 4 FPGA.For example: 4 FPGA are arranged, it is 5*8bit that the one FPGA needs loading data, it is 3*8bit that the 2nd FPGA needs loading data, it is 4*8bit that the 3rd FPGA needs loading data, it is 2*8bit that the 4th FPGA needs loading data, and put down in writing in the file two this moment: the loading data length of a FPGA correspondence is that the loading data length of 5, the two FPGA correspondences is 3, the loading data length of the 3rd FPGA correspondence is that the loading data length of 4, the four FPGA correspondences is 2.
Need to prove, for can encapsulating or variation such as compression of file one and file two.
307: the output clock is clapped, and rising edge or trailing edge in that each clock is clapped load the above-mentioned FPGA that loads data into.
Loading the above-mentioned FPGA of loading data into specifically is, the rising edge or the trailing edge FPGA that clap at each clock can read the loading data of loading control output.
308: it is unusual to have judged whether that FPGA loads, if judged result is to have FPGA to load unusually, then carries out 309; Otherwise, carry out 310.
309: carry out abnormality processing, carry out 313 then.
310: having judged whether that FPGA loads finishes, if judged result is to have FPGA to load to finish, then carries out 311; Otherwise, carry out 305.
Concrete, when the loading data of FPGA has reached the loading data length of describing in the file two, return a signal to loading control, after loading control is read this signal, corresponding FPGA is put loading data complement mark.
311: judging whether that 4 FPGA all load finishes, if judged result is 4 FPGA all to load and finish, then carries out 313; Otherwise, carry out 312.
312: select forbidden energy to loading completed FPGA sheet, carry out 305 to loading uncompleted FPGA.
313: finish.
Second kind of application scenarios: the loading control bit wide is less than n*8bit, and n is for needing the FPGA of loading, and n is the natural number greater than 1, and just the loading control bit wide is less than total bit wide of a plurality of FPGA.In this scene, be 32bit with the loading control bit wide, needing the FPGA of 5 8bit of loading is that example is described in detail, and as shown in Figure 4, the method for loading field programmable gate array comprises:
401: the start-up loading flow process.
402: in default delay time, judge whether 5 FPGA all have response, response is all arranged, then carry out 405 if judged result is 5 FPGA; Otherwise, carry out 403.
This step is similar with step 302, repeats no more herein.
403: judge whether to surpass delay time,, then carry out 404 if judged result is to surpass delay time; Otherwise, carry out 402.
404: ignore the FPGA that does not have response, carry out 405 then; Perhaps directly carry out 416.
405: the FPGA that choosing enables or sheet choosing is enabled to the FPGA counterpiece keeps its sheet to select enabled state.
Need to prove, it specifically is that FPGA sheet choosing to be loaded enables that FPGA sheet choosing is enabled, though 5 FPGA are arranged in the embodiment of the invention, but once can only 4 FPGA of loaded in parallel, that is to say that FPGA to be loaded is 4, thus specifically be that choosing enables to 4 FPGA sheets herein, and the FPGA that sheet choosing is enabled, when carrying out this step once more, be the maintenance of the FPGA sheet being selected enabled state.
406: read loading data, export with the 4*8bit bit wide.
The data that are used to load 5 FPGA are two files that generate according to 5 original loading data files of FPGA:
File one is a large data files that utilizes the loading data file generation of 5 FPGA, and each word length is 32bit in the file one, and the form of file one is as shown in table 3:
Table 3
In the table 3, m is a length value of getting the maximum length of 5 loading datas among the FPGA; 1,2,3,4 respectively corresponding a FPGA, the 2nd FPGA, the 3rd FPGA, the 4th FPGA; 8bit is the loading data of respectively corresponding a FPGA, the 2nd FPGA, the 3rd FPGA, the 4th FPGA; The 8bit padding data
[1]Be shorter when corresponding FPGA loading data, the extraneous data that continues to send after the data load of corresponding FPGA is finished can arbitrarily be filled, but in order to guarantee the readability of file, recommends to use 00, fixed data shapes fillings such as FF, 55, AA; 8bit
[2]It is the loading data of corresponding the 5th FPGA.In actual applications, can take all factors into consideration the length of the loading data of the several FPGA that need loading, rationally arrange the loading sequence between the FPGA, thereby shorten the overall load time.
For example: 5 FPGA are arranged, it is 5*8bit that the one FPGA needs loading data, it is 3*8bit that the 2nd FPGA needs loading data, it is 4*8bit that the 3rd FPGA needs loading data, it is 2*8bit that the 4th FPGA needs loading data, it is 2*8bit that the 5th FPGA needs loading data, and this moment, corresponding file one was as shown in table 4 so:
Table 4
| First " word " | Second " word " | The 3rd " word " | The 4th " word " | The 5th " word " | |
| 1 | 8bit | 8bit | 8bit | 8bit | 8bit |
| 2 | 8bit | 8bit | 8bit | FF | FF |
| 3 | 8bit | 8bit | 8bit | 8bit | FF |
| 4 | 8bit | 8bit | 8bit [2] | 8bit [2] | FF |
File two except the loading data length of describing 5 FPGA, has also been described the loading sequence between 5 FPGA.
For example: 5 FPGA are arranged, it is 5*8bit that the one FPGA needs loading data, it is 3*8bit that the 2nd FPGA needs loading data, it is 4*8bit that the 3rd FPGA needs loading data, it is 2*8bit that the 4th FPGA needs loading data, it is 2*8bit that the 5th FPGA needs loading data, record in the file two this moment: the loading data length of a FPGA correspondence is 5, the loading data length of the 2nd FPGA correspondence is 3, the loading data length of the 3rd FPGA correspondence is 4, the loading data length of the 4th FPGA correspondence is that the loading data length of 2, the five FPGA correspondences is 2; Also record in the file two in addition: a FPGA, the 2nd FPGA, the 3rd FPGA, the 4th FPGA are parallel the connections, and the 5th FPGA serial is in a FPGA back.
Need to prove, can encapsulate or variation such as compression for the form of file one and file two.
407: the output clock is clapped, and rising edge or trailing edge in that each clock is clapped load the above-mentioned FPGA that loads data into.
Loading the above-mentioned FPGA of loading data into specifically is, the rising edge or the trailing edge FPGA that clap at each clock can read the loading data of loading control output.
408: it is unusual to have judged whether that FPGA loads, if judged result is to have FPGA to load unusually, then carries out 409; Otherwise, carry out 410.
409: carry out abnormality processing, carry out 416 then.
410: having judged whether that FPGA loads finishes, if judged result is to have FPGA to load to finish, then carries out 411; Otherwise, carry out 405.
This step is similar with step 310, repeats no more herein.
411: judge whether FPGA is to be loaded in addition under the passage that loads the FPGA that finishes, also have FPGA to be loaded down, then carry out 412 if judged result is the passage that loads the FPGA that finishes; Otherwise, carry out 414.
412: the sheet of the FPGA that loading is finished selects forbidden energy.
413: start the loading of the FPGA to be loaded under the passage of the FPGA that loading is finished, carry out 405 then.
414: judging whether that all FPGA load finishes, if judged result is all FPGA to load and finish, then carries out 416; Otherwise, carry out 415.
415: select forbidden energy to loading completed FPGA sheet, carry out 405 to loading uncompleted FPGA.
416: finish.
Need to prove, the described method of the embodiment of the invention is applicable to that also using programmable logic device that the input/output interface of loading control is extended out is a plurality of input/output interfaces, a plurality of FPGA are carried out the situation of loaded in parallel, being used for loaded data file one and file two remains and is handled by loading control, the Loading Control flow process is still moved by loading control, the instruction that difference is just sent, data, clock, the data of sheet choosing and other control signals and retaking of a year or grade, control signals etc. all need to carry out privately owned communication between loading control and the programmable logic device through programmable logic device.
The described technical scheme of the embodiment of the invention has shortened the load time of a plurality of field programmable gate arrays by a plurality of field programmable gate arrays of loaded in parallel; And, also make the existing system data fan-out capability be fully used; In addition, by the loading that a plurality of field programmable gate arrays is walked abreast and serial combines, making is having under the situation of identical GPIO, has realized the loading to more a plurality of field programmable gate arrays.
Embodiment 2
Referring to Fig. 5, the embodiment of the invention provides a kind of device of loading field programmable gate array, and this device specifically comprises:
Load-on module 503, the judged result that is used for when judge module 502 is after a plurality of field programmable gate arrays all have response, a plurality of field programmable gate arrays of loaded in parallel.
Further,
Wherein, load-on module 503 specifically comprises:
First enables the unit, is used for the sheet choosing of a plurality of field programmable gate arrays is enabled;
First output unit, being used for first enables to read loading data, the output loading data after the unit enables the choosing of the sheet of a plurality of field programmable gate arrays, and the bat of output clock, rising edge or the trailing edge clapped at clock load above-mentioned a plurality of field programmable gate arrays that load data into;
First judging unit, be used for first output unit rising edge that clock is clapped or trailing edge load above-mentioned load data into a plurality of field programmable gate arrays after, judge that whether to have field programmable gate array to load in a plurality of field programmable gate arrays unusual; Do not finish when having field programmable gate array to load when unusual, judge whether have field programmable gate array to load in a plurality of field programmable gate arrays in a plurality of field programmable gate arrays; When having field programmable gate array to load in a plurality of field programmable gate arrays to finish, judge whether that a plurality of field programmable gate arrays all load to finish;
First end unit is used for all loading when finishing when a plurality of field programmable gate arrays of first judgment unit judges, finishes to load.
Further, load-on module 503 also comprises:
First processing unit, be used for when first judgment unit judges be not that a plurality of field programmable gate arrays all load when finishing, the sheet that loads completed field programmable gate array is selected forbidden energy, carry out loaded in parallel to loading uncompleted field programmable gate array.
In addition, load-on module 503 specifically comprises:
Second enables the unit, and the sheet choosing that is used for the field programmable gate array that a plurality of field programmable gate arrays are to be loaded enables;
Second output unit, after being used for the second sheet choosing that enables the unit field programmable gate array that a plurality of field programmable gate arrays are to be loaded and enabling, read loading data, the output loading data, and the bat of output clock, rising edge or the trailing edge clapped at clock load the above-mentioned field programmable gate array to be loaded that loads data into;
Second judging unit, be used for second output unit rising edge that clock is clapped or trailing edge load above-mentioned load data into field programmable gate array to be loaded after, whether judge has field programmable gate array to load unusually in the field programmable gate array to be loaded; When not having the field programmable gate array loading data unusual in the field programmable gate array to be loaded, judge that whether having field programmable gate array to load in the field programmable gate array to be loaded finishes; When having the field programmable gate array loading to finish in the field programmable gate array to be loaded, judge whether field programmable gate array is to be loaded in addition under the passage that loads the field programmable gate array of finishing; When not having field programmable gate array to be loaded under the passage of the field programmable gate array that loading is finished, judge whether that a plurality of field programmable gate arrays all load to finish;
Second end unit is used for all loading when finishing when a plurality of field programmable gate arrays of second judgment unit judges, finishes to load.
Further, load-on module 503 also comprises:
Second processing unit, be used for when having field programmable gate array to be loaded under the passage of the field programmable gate array that the loading of second judgment unit judges is finished, the sheet of the field programmable gate array that loading is finished selects forbidden energy, and the field programmable gate array to be loaded under the field programmable gate array respective channel that loading is finished carries out loaded in parallel.
Further, load-on module 503 also comprises:
The 3rd processing unit, be used for when second judgment unit judges be not that a plurality of field programmable gate arrays all load when finishing, the sheet that loads completed field programmable gate array is selected forbidden energy, carry out loaded in parallel to loading uncompleted field programmable gate array.
Device shown in the embodiment of the invention, by a plurality of field programmable gate arrays of loaded in parallel, when make loading a plurality of field programmable gate array, the total load time that needs shortens; And, also make the existing system data fan-out capability be fully used; In addition, by the loading that a plurality of field programmable gate arrays is walked abreast and serial combines, making is having under the situation of identical GPIO, has realized the loading to more a plurality of field programmable gate arrays.
Embodiment 3
Referring to Fig. 6, the embodiment of the invention provides a kind of system of loading field programmable gate array, and this system specifically comprises:
Further, referring to Fig. 7, be the annexation schematic diagram of a kind of loading control 601 and a plurality of field programmable gate array 602.
Wherein, loading control 601 links to each other with each field programmable gate array in a plurality of field programmable gate arrays 602;
Further, referring to Fig. 8, be the annexation schematic diagram of another kind of loading control 601 and a plurality of field programmable gate array 602.
Wherein, a plurality of field programmable gate arrays 602 are divided into many groups;
Field programmable gate array in other group except that first group in many groups links to each other with loading control 601 by the field programmable gate array in first group;
Need to prove, a plurality of field programmable gate arrays are divided into many groups, when loading control bit wide during less than the total bit wide of a plurality of field programmable gate arrays, can not realize once a plurality of field programmable gate arrays being carried out loaded in parallel simultaneously, a plurality of field programmable gate arrays can be divided into many groups, loaded in parallel is carried out in gradation, for example: the loading control bit wide is 32bit, need to load 7 8bit field programmable gate arrays, 7 8bit field programmable gate arrays can be divided into 2 groups and carry out loaded in parallel, wherein first group comprises 4 8bit field programmable gate arrays, second group comprises 3 8bit field programmable gate arrays, and the field programmable gate array of 3 8bit that comprise in second group can be connected any one back of first group of 4 8bit field programmable gate array that comprise; In addition, also 7 8bit field programmable gate arrays can be divided into 3 groups and carry out loaded in parallel, wherein first group comprises 4 8bit field programmable gate arrays, second group comprises 2 8bit field programmable gate arrays, the 3rd group comprises 1 8bit field programmable gate array, second group of 2 8bit field programmable gate array that comprise can be connected any one back of first group of 4 8bit field programmable gate array that comprise, and the 3rd group of 1 8bit field programmable gate array that comprises can be connected any one back of second group of 2 8bit field programmable gate array that comprise.Specifically how to divide into groups, can select flexibly according to actual needs, but the product of the bit wide of the number of the field programmable gate array that comprises and field programmable gate array in each group bit wide of loading data (be used for) is less than and equals the loading control bit wide.
Need to prove in addition, system shown in the embodiment of the invention is applicable to that also using programmable logic device that the input/output interface of loading control is extended out is a plurality of input/output interfaces, a plurality of FPGA are carried out the situation of loaded in parallel, the Loading Control flow process is still moved by loading control, the data of the instruction that difference is just sent, data, clock, sheet choosing and other control signals and retaking of a year or grade, control signal etc. all need to carry out privately owned communication between loading control and the programmable logic device through programmable logic device.
System shown in the embodiment of the invention, by a plurality of field programmable gate arrays of loaded in parallel, when make loading a plurality of field programmable gate array, the total load time that needs shortens; And, also make the existing system data fan-out capability be fully used; In addition, by the loading that a plurality of field programmable gate arrays is walked abreast and serial combines, making is having under the situation of identical GPIO, has realized the loading to more a plurality of field programmable gate arrays.
All or part of content in the technical scheme that above embodiment provides can realize that its software program is stored in the storage medium that can read by software programming, storage medium for example: the hard disk in the computer, CD or floppy disk.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (16)
1, a kind of method of loading field programmable gate array is characterized in that, comprising:
The start-up loading flow process;
Judge whether a plurality of field programmable gate arrays all have response in the default delay time;
If judged result is described a plurality of field programmable gate array response is arranged all, then the described a plurality of field programmable gate arrays of loaded in parallel.
2, the method for loading field programmable gate array according to claim 1, it is characterized in that, when judged result is that described a plurality of field programmable gate array is not when all response being arranged, judge whether to surpass default delay time, if judged result is to surpass default delay time, then loaded in parallel has the field programmable gate array of response.
3, the method for loading field programmable gate array according to claim 1, it is characterized in that, when loading control bit wide during more than or equal to the total bit wide of a plurality of field programmable gate arrays, the described a plurality of field programmable gate arrays of described loaded in parallel comprise:
The sheet choosing of described a plurality of field programmable gate arrays is enabled;
Read loading data, export described loading data, and the bat of output clock, rising edge or the trailing edge clapped at described clock load the described described a plurality of field programmable gate array that loads data into;
Whether judge has field programmable gate array to load unusually in described a plurality of field programmable gate array;
If there do not have field programmable gate array to load in described a plurality of field programmable gate array to be unusual, judge that whether having field programmable gate array to load in described a plurality of field programmable gate array finishes;
Finish if there is field programmable gate array to load in described a plurality of field programmable gate array, to judge whether that described a plurality of field programmable gate array all loads to finish;
If described a plurality of field programmable gate array all loads finish, finish to load.
4, the method for loading field programmable gate array according to claim 1 is characterized in that, when loading control bit wide during less than the total bit wide of a plurality of field programmable gate arrays, the described a plurality of field programmable gate arrays of described loaded in parallel comprise:
The sheet choosing of field programmable gate array to be loaded in described a plurality of field programmable gate arrays is enabled;
Read loading data, export described loading data, and the bat of output clock, rising edge or the trailing edge clapped at described clock load the described described field programmable gate array to be loaded that loads data into;
Whether judge has field programmable gate array to load unusually in the described field programmable gate array to be loaded;
If there do not have field programmable gate array to load in the described field programmable gate array to be loaded to be unusual, judge that whether having field programmable gate array to load in the described field programmable gate array to be loaded finishes;
Finish if there is field programmable gate array to load in the described field programmable gate array to be loaded, judge whether field programmable gate array is to be loaded in addition under the passage that loads the field programmable gate array of finishing;
Do not have field programmable gate array to be loaded if load under the passage of the field programmable gate array finish, judge whether that described a plurality of field programmable gate array all loads to finish;
If described a plurality of field programmable gate array all loads finish, finish to load.
5, according to the method for claim 3 or 4 described loading field programmable gate arrays, it is characterized in that, described judge whether described a plurality of field programmable gate array all load finish after, also comprise:
All load if not described a plurality of field programmable gate arrays and to finish, the sheet that then will load completed field programmable gate array selects forbidden energy, carries out loaded in parallel to loading uncompleted field programmable gate array.
6, the method for loading field programmable gate array according to claim 4 is characterized in that, described judgement load whether also have under the passage of the field programmable gate array of finishing field programmable gate array to be loaded after, also comprise:
Have field programmable gate array to be loaded if load under the passage of the field programmable gate array finish, the sheet of the field programmable gate array that loading is finished selects forbidden energy;
Field programmable gate array to be loaded under the passage of the field programmable gate array that loading is finished carries out loaded in parallel.
7, a kind of device of loading field programmable gate array is characterized in that, described device comprises:
Start module, be used for the start-up loading flow process;
Judge module, be used for described startup module start-up loading flow process after, judge whether a plurality of field programmable gate arrays all have response in the default delay time;
Load-on module, the judged result that is used for when described judge module is after described a plurality of field programmable gate array all has response, the described a plurality of field programmable gate arrays of loaded in parallel.
8, the device of loading field programmable gate array according to claim 7 is characterized in that,
Described judge module, be used for also that a plurality of field programmable gate arrays are not when all response being arranged in judged result is the delay time of presetting, judge whether to surpass default delay time, if judged result is to surpass default delay time, then notify described load-on module loaded in parallel that the field programmable gate array of response is arranged.
9, the device of loading field programmable gate array according to claim 7 is characterized in that, described load-on module comprises:
First enables the unit, is used for the sheet choosing of described a plurality of field programmable gate arrays is enabled;
First output unit, being used for described first enables after the unit enables the choosing of the sheet of described a plurality of field programmable gate arrays, read loading data, export described loading data, and the bat of output clock, rising edge or the trailing edge clapped at described clock load the described described a plurality of field programmable gate array that loads data into;
First judging unit, be used for described first output unit rising edge that described clock is clapped or trailing edge load described load data into described a plurality of field programmable gate array after, judge that whether to have field programmable gate array to load in described a plurality of field programmable gate array unusual; Do not finish when having field programmable gate array to load when unusual, judge whether have field programmable gate array to load in described a plurality of field programmable gate array in described a plurality of field programmable gate arrays; When having field programmable gate array to load in described a plurality of field programmable gate arrays to finish, judge whether that described a plurality of field programmable gate array all loads to finish;
First end unit is used for all loading when finishing when the described a plurality of field programmable gate arrays of described first judgment unit judges, finishes to load.
10, the device of loading field programmable gate array according to claim 9 is characterized in that, described load-on module also comprises:
First processing unit, be used for when described first judgment unit judges be not that described a plurality of field programmable gate array all loads when finishing, the sheet that loads completed field programmable gate array is selected forbidden energy, carry out loaded in parallel loading uncompleted field programmable gate array.
11, the device of loading field programmable gate array according to claim 7 is characterized in that, described load-on module comprises:
Second enables the unit, and the sheet choosing that is used for the field programmable gate array that described a plurality of field programmable gate arrays are to be loaded enables;
Second output unit, after being used for the described second sheet choosing that enables the unit field programmable gate array that described a plurality of field programmable gate arrays are to be loaded and enabling, read loading data, export described loading data, and the bat of output clock, rising edge or the trailing edge clapped at described clock load the described described field programmable gate array to be loaded that loads data into;
Second judging unit, be used for described second output unit rising edge that described clock is clapped or trailing edge load described load data into described field programmable gate array to be loaded after, judge that whether to have field programmable gate array to load in the described field programmable gate array to be loaded unusual; Do not finish when having field programmable gate array to load when unusual, judge whether have field programmable gate array to load in the described field programmable gate array to be loaded in the described field programmable gate array to be loaded; When having the field programmable gate array loading to finish in the described field programmable gate array to be loaded, judge whether field programmable gate array is to be loaded in addition under the passage that loads the field programmable gate array of finishing; When not having field programmable gate array to be loaded under the passage of the field programmable gate array that loading is finished, judge whether that described a plurality of field programmable gate array all loads to finish;
Second end unit is used for all loading when finishing when the described a plurality of field programmable gate arrays of described second judgment unit judges, finishes to load.
12, the device of loading field programmable gate array according to claim 11 is characterized in that, described load-on module also comprises:
Second processing unit, be used for when having field programmable gate array to be loaded under the passage of the field programmable gate array that described second judgment unit judges loading is finished, the sheet of the field programmable gate array that loading is finished selects forbidden energy, and the field programmable gate array to be loaded under the passage of the field programmable gate array that loading is finished carries out loaded in parallel.
According to the device of claim 11 or 12 described loading field programmable gate arrays, it is characterized in that 13, described load-on module also comprises:
The 3rd processing unit, be used for when described second judgment unit judges be not that described a plurality of field programmable gate array all loads when finishing, the sheet that loads completed field programmable gate array is selected forbidden energy, carry out loaded in parallel loading uncompleted field programmable gate array.
14, a kind of system of loading field programmable gate array is characterized in that, described system comprises:
Loading control and a plurality of field programmable gate array;
Described loading control is used for the start-up loading flow process; Judge whether described a plurality of field programmable gate arrays all have response in the default delay time; If judged result is described a plurality of field programmable gate array response is arranged all, then the described a plurality of field programmable gate arrays of loaded in parallel.
15, the system of loading field programmable gate array according to claim 14 is characterized in that,
Described loading control links to each other with each field programmable gate array in described a plurality of field programmable gate arrays;
Described loading control specifically is used for the sheet choosing of described a plurality of field programmable gate arrays is enabled; Read loading data, export described loading data, and the bat of output clock, rising edge or the trailing edge clapped at described clock load the described described a plurality of field programmable gate array that loads data into; Whether judge has field programmable gate array to load unusually in described a plurality of field programmable gate array; If there do not have field programmable gate array to load in described a plurality of field programmable gate array to be unusual, judge that whether having field programmable gate array to load in described a plurality of field programmable gate array finishes; Finish if there is field programmable gate array to load in described a plurality of field programmable gate array, to judge whether that described a plurality of field programmable gate array all loads to finish; If described a plurality of field programmable gate array all loads finish, finish to load.
16, the system of loading field programmable gate array according to claim 14 is characterized in that,
Described a plurality of field programmable gate array is divided into many groups;
Each field programmable gate array in first group in described loading control and the described many groups links to each other;
Field programmable gate array in other group except that first group in described many groups links to each other with described loading control by the field programmable gate array in described first group;
Described loading control, the sheet choosing that specifically is used for the field programmable gate array that described a plurality of field programmable gate arrays are to be loaded enables; Read loading data, export described loading data, and the bat of output clock, rising edge or the trailing edge clapped at described clock load the described described field programmable gate array to be loaded that loads data into; Whether judge has field programmable gate array to load unusually in the described field programmable gate array to be loaded; If there do not have field programmable gate array to load in the described field programmable gate array to be loaded to be unusual, judge that whether having field programmable gate array to load in the described field programmable gate array to be loaded finishes; Finish if there is field programmable gate array to load in the described field programmable gate array to be loaded, judge whether field programmable gate array is to be loaded in addition under the passage that loads the field programmable gate array of finishing; Do not have field programmable gate array to be loaded if load under the passage of the field programmable gate array finish, judge whether that described a plurality of field programmable gate array all loads to finish; If described a plurality of field programmable gate array all loads finish, finish to load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA2008101809041A CN101404492A (en) | 2008-11-14 | 2008-11-14 | Method, apparatus and system for loading field programmable gate array |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008101809041A CN101404492A (en) | 2008-11-14 | 2008-11-14 | Method, apparatus and system for loading field programmable gate array |
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| CN101404492A true CN101404492A (en) | 2009-04-08 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200955A (en) * | 2011-04-26 | 2011-09-28 | 中兴通讯股份有限公司 | Method and device for supporting field programmable gate arrays (FPGA) to download data |
| CN102662780A (en) * | 2012-03-22 | 2012-09-12 | 中兴通讯股份有限公司 | Protection method and protection device for power supply in multiple-programmable-device system |
| CN105511897A (en) * | 2014-09-26 | 2016-04-20 | 杭州华三通信技术有限公司 | Method and device used for initialization of programmable device |
| CN108027798A (en) * | 2015-12-08 | 2018-05-11 | 上海兆芯集成电路有限公司 | The processor with expansible instruction set architecture of resource is performed for dynamic configuration |
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2008
- 2008-11-14 CN CNA2008101809041A patent/CN101404492A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102200955A (en) * | 2011-04-26 | 2011-09-28 | 中兴通讯股份有限公司 | Method and device for supporting field programmable gate arrays (FPGA) to download data |
| CN102200955B (en) * | 2011-04-26 | 2015-10-21 | 中兴通讯股份有限公司 | Support method and the device of multiple field programmable gate array downloading data |
| CN102662780A (en) * | 2012-03-22 | 2012-09-12 | 中兴通讯股份有限公司 | Protection method and protection device for power supply in multiple-programmable-device system |
| CN102662780B (en) * | 2012-03-22 | 2015-06-10 | 中兴通讯股份有限公司 | Protection method and protection device for power supply in multiple-programmable-device system |
| CN105511897A (en) * | 2014-09-26 | 2016-04-20 | 杭州华三通信技术有限公司 | Method and device used for initialization of programmable device |
| CN105511897B (en) * | 2014-09-26 | 2018-11-09 | 新华三技术有限公司 | Method and apparatus for initializing programming device |
| US10268631B2 (en) | 2014-09-26 | 2019-04-23 | Hewlett Packard Enterprise Development Lp | Initialize programmable components |
| CN108027798A (en) * | 2015-12-08 | 2018-05-11 | 上海兆芯集成电路有限公司 | The processor with expansible instruction set architecture of resource is performed for dynamic configuration |
| CN108027798B (en) * | 2015-12-08 | 2021-08-20 | 上海兆芯集成电路有限公司 | Processor with extensible instruction set architecture for dynamically configuring execution resources |
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