CN101751067B - Synchronous circuit applied to multiple microprocessors - Google Patents
Synchronous circuit applied to multiple microprocessors Download PDFInfo
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- CN101751067B CN101751067B CN2008101764337A CN200810176433A CN101751067B CN 101751067 B CN101751067 B CN 101751067B CN 2008101764337 A CN2008101764337 A CN 2008101764337A CN 200810176433 A CN200810176433 A CN 200810176433A CN 101751067 B CN101751067 B CN 101751067B
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Abstract
The invention provides a synchronous circuit applied to multiple microprocessors, which comprises a plurality of microprocessors, wherein each microprocessor comprises a frequency signal end for receiving frequency signal, a reset signal end for receiving a reset signal, a control end for sending a control signal or receiving a response signal, an indicating port end for providing voltage to indicate whether the microprocessor is initialized or not, and an initialized state indicating circuit coupled on the indicating port end, wherein after each reset signal is cleared, each microprocessor reduces the voltage on the indicating port end to initialize; when all the microprocessors complete the initialization, the voltage on the indicating port end rises, all the microprocessors work together according to respective frequency signal, and send control signal or receive respond signal on each control end.
Description
Technical field
The present invention relates to a kind of synchronizing circuit, refer in particular to a kind of synchronizing circuit that is applied to a plurality of microprocessors.
Background technology
In a system that is made up of many microprocessors, the communication between each microprocessor, collaborative and synchronous problem are most important, and its synchronous performance has each other determined effect and the quality that system appears at last.
For the stationary problem between a plurality of microprocessors; Knowing technology generally all utilizes a microprocessor as active process device (Master MCU); Remaining microprocessor then is a slave processor (SlaveMCU), and the action that cooperates the active process device is to reach synchronous effect.For example U.S. Pat 2006/0182214A1 number, the method that is wherein proposed promptly be a microprocessor in the middle of utilizing as the active process device, and see synchronizing signal off and give in the system other microprocessor; In addition, slave microprocessor also needs a universe reference frequency to respond the synchronous time.Yet this design is not only too complicated, and also need expend sizable cost when expanding, even needs design again comprehensively.
In addition, even system uses simple universe reset signal and universe frequency, can't confirm also whether total system is consistent synchronously.This is that these time differences of requirement elimination are that present semiconductor technology is beyond one's reach because each microprocessor required time when resetting with initialization is all different.
Summary of the invention
Because of post, the applicant is in view of the disappearance of knowing in the technology to be produced, and through concentrated test and research, and in line with the spirit of working with perseverance, visualizes the present invention-be applied to the synchronizing circuit of a plurality of microprocessors eventually, below is brief description of the present invention.
Here, be necessary to conceive a kind of synchronizing circuit that is applied to a plurality of microprocessors, utilize this synchronizing circuit to be able to the different difference of initialization time of each microprocessor in the elimination system.This synchronizing circuit is to utilize the electrical specification open the drain electrode port, makes that the init state of each microprocessor all is reflected on unique lead in the system, and the lead here is meant that resistance R 1 is connected to the lead of MCU1～MCU3 simultaneously; After all microprocessor is accomplished initialization, utilize the triangular web frequency signal again, make that each microprocessor executes instruction synchronously in the system.
According to above-mentioned conception, the present invention proposes a kind of synchronizing circuit that is applied to a plurality of microprocessors, comprising: a plurality of microprocessors and an init state indicating circuit; Respectively this microprocessor all has: a frequency signal end receives a frequency signal; One reset signal end receives a reset signal; One control end sends a control signal or receives a reaction signal; Reach an indication port end, a voltage is provided, whether accomplish initialization to indicate this microprocessor; This init state indicating circuit is coupled in respectively this indication port end; Wherein, After respectively this reset signal is removed; Respectively this microprocessor will indicate this voltage on the port end to reduce, carrying out initialization, and when all microprocessors are all accomplished initialization; This indication this voltage on port end raises, and respectively this microprocessor is according to the collaborative work and respectively sending this control signal or receiving this reaction signal on this control end each other of this frequency signal respectively.
Preferably, wherein this indication port end be decided to be according to a functional menu (option table) one open drain electrode end (open drain port) or and export/go into end.
Preferably, wherein this init state indicating circuit is to be made up of lead and resistance.
Preferably, wherein respectively this microprocessor be to constitute by AND logic gate, OR logic gate and transistor.
Preferably, also have an error detection circuit, be coupled in respectively this microprocessor, in order to respectively whether normal operation of this microprocessor of detecting.
Preferably, wherein this error detection circuit is to be made up of AND logic gate, reverser and counter.
Preferably, also has a test circuit, in order to test which this microprocessor abnormal operation.
Preferably, wherein this test circuit is to be made up of resistance, reverser and pilot lamp.
By drawings as hereinafter and detailed description, can obtain more deep understanding to the present invention:
Description of drawings
Fig. 1 is the circuit block diagram of the synchronizing circuit that is applied to a plurality of microprocessors proposed by the invention;
Fig. 2 is the circuit block diagram of microprocessor one preferred embodiment proposed by the invention;
Fig. 3 is the action flow chart of the microprocessor of Fig. 2;
Fig. 4 is the process flow diagram of the error detection method of microprocessor proposed by the invention;
Fig. 5 is the circuit block diagram in order to error detection circuit one preferred embodiment of the error detection method of execution graph 4;
Fig. 6 is the circuit block diagram in order to test circuit one preferred embodiment of the error detection method of collocation Fig. 4.
Embodiment
See also Fig. 1, it is the circuit block diagram of the synchronizing circuit that is applied to a plurality of microprocessors proposed by the invention.In Fig. 1, synchronizing circuit 10 mainly is that wherein init state indicating circuit 11 is to be made up of resistance R 1 and lead by a plurality of microprocessors (being three microprocessors in this example) MCU1～3 and 11 formations of an init state indicating circuit.
Each microprocessor all has a frequency signal end, a reset signal end, a control end and an indication port end.With microprocessor MCU1 is example; The frequency signal termination is received a frequency signal Clk_g; The reset signal termination is received reset signal reset; Control end sends a control signal or receives a reaction signal matrix area 1, and indication port end Port S then provides a voltage whether to accomplish initialization with indication microprocessor MCU1.
The function mode of synchronizing circuit 10 is following:
When system power supply was opened, after all microprocessors waited for that reset signal reset removes, beginning was reset and initialization separately.Reset and initialization among, each microprocessor is that indication port end Port S is pulled to low-voltage, lets other microprocessor in the system know that this microprocessor do not accomplish initialization as yet and fail operate as normal by this.And after this microprocessor was accomplished replacement and initialization, it just can decontrol indication port end Port S, waited for that the voltage of indication port end Port S becomes high voltage, and all then microprocessors just begin to execute instruction according to the frequency signal Clk_g of universe.At this moment, all collaborative works synchronously with one another of all microprocessors in the system.According to the data of each microprocessor that system designer is distributed to, export control signal or receive its reaction signal for the matrix area of being responsible for.
What deserves to be mentioned is that indication port end Port S is to open drain electrode port (open-drain port), to reach above-mentioned function.Yet when same microprocessor not needing to be applied in the synchronous system, indication port end Port S can be decided to be another general input/output terminal according to a functional menu (option table); That is to say that microprocessor need not design the IO port of a synchronization dedicated.
See also Fig. 2, it is the circuit block diagram of microprocessor one preferred embodiment proposed by the invention.In Fig. 2, microprocessor 20 mainly is to be made up of AND logic gate 21 and 22, OR logic gate 23 and 24 in transistor.
Below when cooperating Fig. 2, its internal actions mode is described.
See also Fig. 3, it is the action flow chart of the microprocessor of Fig. 2.As shown in Figure 3, after system power supply starts, open the drain electrode port and be preset to startup and reduce to electronegative potential, then the download function menu.Functional menu read finish after, whether microprocessor can use and hold the drain electrode port and drive according to setting decision.
(i) be general IO port if decision is set, then continue and reset and initialization action, and after initialization was accomplished, microprocessor also can be according to each item function of normal procedure executive routine.
If (ii) decision is set to opening the drain electrode port, microprocessor will not change setting, the initialization action that continues, and after initialization was accomplished, microprocessor then can be waited for when the voltage of holding the drain electrode port is promoted to high voltage, each item function of the executive routine that just continues.
Owing to open the characteristic of drain electrode port, as long as arbitrary microprocessor of parallel connection is not decontroled out the voltage of drain electrode port, then the init state indicating circuit just can not be promoted to high voltage, and total system just can not get into mode of operation yet.Therefore, if there is arbitrary microprocessor to take place will indicate unusually and not port to decontrol in the system, total system just will be stopped.
To problems such as fault eliminating or production test, the mode that a kind of system of essential design detects.Because the indication port on all microprocessors is to be connected in parallel; Which microprocessor generation problem can't use simple electron measuring mode to learn is; Therefore propose a kind of error detection method, Fig. 4 is the process flow diagram of the error detection method of microprocessor proposed by the invention.
As shown in Figure 4, whether after system power supply starts, it is overtime then to detect error detection by counter; If, then represent mistake to produce, promptly the stop frequency signal and begin the test; If not, then whether all be in the preparation, whether carried out the synergistic function of all microprocessors with decision according to all microprocessors.
See also Fig. 5, it is the circuit block diagram in order to error detection circuit one preferred embodiment of the error detection method of execution graph 4.Can find out that by Fig. 5 error detection circuit 50 mainly is to be made up of counter 51, reverser 52 and 53 of AND logic gates.
See also Fig. 6, it is the circuit block diagram in order to test circuit one preferred embodiment of the error detection method of collocation Fig. 4.When error detection circuit 50 was reported mistake, system will utilize the lifting circuit of other one group of test, came to judge one by one whether each microprocessor takes place unusual and whether the indication port still drives.Shown in the test circuit 60 of Fig. 6, it mainly is to be made up of resistance R 2, pilot lamp 61 and 62 of reversers.After each microprocessor was all tested, as be judged to be unusually, then as long as the engineering staff is this microprocessor of replacement.Under this mode that detects one by one, the state of each microprocessor can both be to be detected, it is hereby ensured that all problematic microprocessors can be screened.
In sum; The present invention mainly proposes a kind of synchronizing circuit that is applied to a plurality of microprocessors; The electrical specification of drain electrode port is opened in utilization; Make that the init state of each microprocessor all is reflected on unique lead in the system, the lead here is meant that resistance R 1 is connected to the lead of MCU1～MCU3 simultaneously; After all microprocessor is accomplished initialization, utilize the triangular web frequency signal again, make that each microprocessor executes instruction synchronously in the system.By such design, system developer can be utilized simple command calculations, makes all microprocessors put its corresponding data of input and output at the same time, can save design cost and increase Extended Spaces.
Description of reference numerals:
10 synchronizing circuits, 11 init state indicating circuits
20 microprocessors 21,22,53AND logic gate
23OR logic gate 24 transistors
50 error detection circuit, 51 counters
52,62 reversers, 60 test circuits
61 pilot lamp R1, R2 resistance
Any modification and change that those skilled in the art is done according to the present invention all do not break away from the protection domain of the incidental claim of the present invention.
Claims (8)
1. synchronizing circuit that is applied to a plurality of microprocessors comprises:
A plurality of microprocessors, each said microprocessor all has:
One frequency signal end receives a frequency signal;
One reset signal end receives a reset signal;
One control end sends a control signal or receives a reaction signal; And
One indication port end provides a voltage, whether accomplishes initialization to indicate said microprocessor; And
One init state indicating circuit is coupled in each said indication port end;
Wherein, After each said reset signal is removed; Each said microprocessor reduces the said voltage on the said indication port end, carrying out initialization, and when all microprocessors are all accomplished initialization; Said voltage on the said indication port end raises, and each said microprocessor is according to the collaborative work and on each said control end, send said control signal or receive said reaction signal each other of each said frequency signal.
2. synchronizing circuit as claimed in claim 1, wherein said indication port end be decided to be according to a functional menu one open drain electrode end or and export/go into end.
3. synchronizing circuit as claimed in claim 1, wherein said init state indicating circuit is to be made up of lead and resistance.
4. synchronizing circuit as claimed in claim 1, wherein each said microprocessor is to be made up of AND logic gate, OR logic gate and transistor.
5. synchronizing circuit as claimed in claim 1 also has an error detection circuit, is coupled in each said microprocessor, in order to detect the whether normal operation of each said microprocessor.
6. synchronizing circuit as claimed in claim 5, wherein said error detection circuit is to be made up of AND logic gate, reverser and counter.
7. synchronizing circuit as claimed in claim 5 also has a test circuit, in order to test which said microprocessor abnormal operation.
8. synchronizing circuit as claimed in claim 7, wherein said test circuit are to be made up of resistance, reverser and pilot lamp.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101764337A CN101751067B (en) | 2008-11-11 | 2008-11-11 | Synchronous circuit applied to multiple microprocessors |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101764337A CN101751067B (en) | 2008-11-11 | 2008-11-11 | Synchronous circuit applied to multiple microprocessors |
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| CN101751067A CN101751067A (en) | 2010-06-23 |
| CN101751067B true CN101751067B (en) | 2012-05-23 |
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| CN106201961B (en) * | 2016-07-01 | 2019-05-07 | 英业达科技有限公司 | The calculator system and method for control processor working frequency |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949129A (en) * | 2006-11-27 | 2007-04-18 | 杭州华为三康技术有限公司 | Time synchronizing method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1949129A (en) * | 2006-11-27 | 2007-04-18 | 杭州华为三康技术有限公司 | Time synchronizing method and device |
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