CN101740323A - Method for manufacturing alignment mark of semiconductor silicon wafer and semiconductor silicon wafer thereby - Google Patents
Method for manufacturing alignment mark of semiconductor silicon wafer and semiconductor silicon wafer thereby Download PDFInfo
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- CN101740323A CN101740323A CN200810043997A CN200810043997A CN101740323A CN 101740323 A CN101740323 A CN 101740323A CN 200810043997 A CN200810043997 A CN 200810043997A CN 200810043997 A CN200810043997 A CN 200810043997A CN 101740323 A CN101740323 A CN 101740323A
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- alignment mark
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Abstract
The invention discloses a method for manufacturing an alignment mark of a semiconductor silicon wafer. The method comprises the following steps of: depositing a layer of luminescent material on the back face of the semiconductor wafer, photoetching the back of the semiconductor wafer, manufacturing the alignment mark through corrosion and removing photoresist. The invention also discloses a semiconductor wafer, the back of the semiconductor wafer is provided with the alignment mark which is made of the luminescent material. In the invention, the alignment mark is arranged on the back of the semiconductor wafer, thereby the use area of the front of the wafer is greatly saved. The position of the alignment mark is fixed so that an alignment signal can not be influenced by different products and different processes.
Description
Technical field
The present invention relates to a kind of manufacture method of semi-conductor silicon chip alignment mark.The invention still further relates to a kind of semi-conductor silicon chip.
Background technology
At present, in semiconductor is made, alignment mark is put in the Cutting Road in silicon chip front, so just reduced the usable floor area of front silicon chip.Particularly when new process development, need add in batches estimating of many alignment marks through regular meeting, at this time, Cutting Road tends to not enough use.Simultaneously, since the difference of the chip size of the silicon chip of the new product of each exploitation, each position that all needs to rearrange alignment mark; And when the thickness (film stack) of product changed, pattern of registration signal (profile) and signal strength signal intensity all can be affected.
In addition, in semi-conductive various technical processs, may make the pattern of alignment mark change owing to a variety of causes.As shown in Figure 1, when the alignment mark pattern changes, may introduce secondary peak, cause the registration signal metamorphopsic distortion, thereby influence the coordinate of alignment mark.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacture method of semi-conductor silicon chip alignment mark, and the semi-conductor silicon chip that adopts this method to make, can save the usable floor area in silicon chip front, the riding position of fixed alignment mark, and make registration signal not be subjected to the influence of different product and different process.
For solving the problems of the technologies described above, the technical scheme of the manufacture method of semi-conductor silicon chip alignment mark of the present invention is, at semi-conductor silicon chip back side deposit one deck luminescent material, carries out photoetching at the silicon chip back side afterwards, and etching is produced alignment mark then, removes photoresist.
The present invention also provides a kind of semi-conductor silicon chip, and its technical scheme is, the described semi-conductor silicon chip back side is provided with alignment mark, and described alignment mark is by luminescent materials.
The present invention has saved the usable floor area in silicon chip front greatly by alignment mark being arranged on the back side of semi-conductor silicon chip, the riding position of fixed alignment mark, and make registration signal not be subjected to the influence of different product and different process.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is influenced by morphology change for conventional semiconductor silicon chip alignment mark schematic diagram;
Fig. 2 and Fig. 3 are the side cutaway view of another embodiment of the manufacture method of semi-conductor silicon chip of the present invention and alignment mark thereof;
Fig. 4 is influenced by morphology change for semi-conductor silicon chip alignment mark of the present invention schematic diagram;
Fig. 5 is the side cutaway view of another embodiment of the manufacture method of semi-conductor silicon chip of the present invention and alignment mark thereof;
Fig. 6 is the structural representation of the aligning sniffer of semi-conductor silicon chip of the present invention.
Reference numeral is among the figure, 1. semi-conductor silicon chip; 2. alignment mark; 3. luminescent material; 4. oxide-film; 5. light source; 6. half-reflecting half mirror; 7. lens; 8. lens; 9. optical detector.
Embodiment
The invention discloses a kind of manufacture method of semi-conductor silicon chip alignment mark, as shown in Figure 2, carry out before the photoetching, at semi-conductor silicon chip 1 back side deposit one deck luminescent material 3, carry out photoetching at the silicon chip back side then, and after etch step in described luminous material layer is carried out etching, form alignment mark 2, as shown in Figure 3.
Among the present invention, described alignment mark is by luminescent materials.In alignment mark, added luminescent substance, strengthened the signal strength signal intensity of peak value greatly, so,, perhaps had under the residual situation, also can improve signal strength signal intensity, reduced measure error even the bottom pattern is bad after the alignment mark etching.As shown in Figure 4, after mixing luminescent substance in the alignment mark, the signal strength signal intensity of alignment mark mainly is subjected to the influence on the upper strata of mark, and the bottom information of alignment mark can reduce the influence of signal strength signal intensity.Described luminescent substance is meeting visible emitting or its all band under infrared radiation, can adopt fluorescent material, adopts sol-gal process to implement.At first deployed fluorescent material and epoxy resin, the concentration of allotment will choose, and is coated onto the silicon chip back side then.
As shown in Figure 5, when making the alignment mark of semi-conductor silicon chip according to the manufacture method of semi-conductor silicon chip alignment mark provided by the present invention, after removing photoresist, can be at semi-conductor silicon chip 1 back side deposit layer oxide film 4 again, avoid alignment mark in manufacture process, to be subjected to the influence of other technologies.
Alignment mark of the present invention can adopt the aligning sniffer of semi-conductor silicon chip as shown in Figure 6 to survey, this sniffer comprises that one shines in the light source 5 of semi-conductor silicon chip 1 back side alignment mark, at described light source 6 irradiations oblique half-reflecting half mirror 7 that is provided with on the transmitted light path at the silicon chip back side, described light source transmitted light path shines described half-reflecting half mirror 7 back transmissions and crosses described half-reflecting half mirror 7, and shine described silicon chip 1 back side, also be provided with lens 7 on the described transmitted light path, described transmitted light path is focused on alignment mark, the reflected light path on silicon chip 1 surface reflects again after shining described half-reflecting half mirror 6 afterwards, shine on the optical detector 9 of described aligning sniffer, also be provided with lens 8 on the described reflected light path, with the reflected light path focal imaging on optical detector 9.
In sum, the present invention has saved the usable floor area in silicon chip front greatly by alignment mark being arranged on the back side of semi-conductor silicon chip, the riding position of fixed alignment mark, and make registration signal not be subjected to the influence of different product and different process.
Claims (4)
1. the manufacture method of a semi-conductor silicon chip alignment mark is characterized in that, at semi-conductor silicon chip back side deposit one deck luminescent material, carries out photoetching at the silicon chip back side afterwards, and etching is produced alignment mark then, removes photoresist.
2. the manufacture method of semi-conductor silicon chip alignment mark according to claim 1 is characterized in that, after removing photoresist, at semi-conductor silicon chip back side deposit layer oxide film.
3. a semi-conductor silicon chip of making of claim 1 or 2 described semi-conductor silicon chip alignment mark manufacture methods is characterized in that the described semi-conductor silicon chip back side is provided with alignment mark, and described alignment mark is by luminescent materials.
4. semi-conductor silicon chip according to claim 3 is characterized in that, the described semi-conductor silicon chip back side is coated with layer oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810043997A CN101740323A (en) | 2008-11-25 | 2008-11-25 | Method for manufacturing alignment mark of semiconductor silicon wafer and semiconductor silicon wafer thereby |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810043997A CN101740323A (en) | 2008-11-25 | 2008-11-25 | Method for manufacturing alignment mark of semiconductor silicon wafer and semiconductor silicon wafer thereby |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101740323A true CN101740323A (en) | 2010-06-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810043997A Pending CN101740323A (en) | 2008-11-25 | 2008-11-25 | Method for manufacturing alignment mark of semiconductor silicon wafer and semiconductor silicon wafer thereby |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101740323A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992166A (en) * | 2016-11-11 | 2017-07-28 | 福州京东方光电科技有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN109166474A (en) * | 2018-10-10 | 2019-01-08 | 京东方科技集团股份有限公司 | A kind of display module and Anawgy accuracy detection method |
-
2008
- 2008-11-25 CN CN200810043997A patent/CN101740323A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106992166A (en) * | 2016-11-11 | 2017-07-28 | 福州京东方光电科技有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN109166474A (en) * | 2018-10-10 | 2019-01-08 | 京东方科技集团股份有限公司 | A kind of display module and Anawgy accuracy detection method |
| CN109166474B (en) * | 2018-10-10 | 2021-08-31 | 京东方科技集团股份有限公司 | Display module and laminating precision detection method |
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Application publication date: 20100616 |