CN101739926B - Row reading circuit - Google Patents
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- CN101739926B CN101739926B CN2008101762350A CN200810176235A CN101739926B CN 101739926 B CN101739926 B CN 101739926B CN 2008101762350 A CN2008101762350 A CN 2008101762350A CN 200810176235 A CN200810176235 A CN 200810176235A CN 101739926 B CN101739926 B CN 101739926B
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Abstract
The invention relates to a row reading circuit for sampling a first and a second picture element signals respectively transmitted through a first and a second data lines in a picture element array. The row reading circuit comprises a first and a second sampling circuits, an amplifier circuit and a control circuit, wherein the control circuit is used for controlling the first sampling circuit to sample the reset level and the data level of the first picture element signal during first sampling and controlling the second sampling circuit to sample the reset level and the data level of the second picture element signal during second sampling. The control circuit controls the amplifier circuit to output the reset level and the data level of the first picture element signal during first sampling and output the resetting level and the data level of the second picture element signal during second sampling.
Description
Technical field
The invention relates to that a kind of row reads (Correlated Double Sampling) circuit, and particularly relevant for a kind of row reading circuit that the picture element signal that transmits on many data lines is taken a sample that is used to.
Background technology
In the prior art, row reads (Correlated Double sampling) circuit and can receive the signal that a pixel is exported, and to its back output of taking a sample.For instance, the signal that pixel is exported comprises replacement level and data level, and row reading circuit has corresponding sample circuit and respectively the replacement level and the data level of picture element signal takes a sample.Row reading circuit also comprises amplifier circuit, in order to the level output that the sample circuit sampling is obtained.
Traditionally, the number of row reading circuit needs corresponding with the size of pel array.For instance, concerning being of a size of 1600 * 1200 pel array, it needs 600 row reading circuits of application 1 to come respectively the picture element signal that transmits on 1600 data lines wherein to be taken a sample.The problem that the circuit area that so will cause row reading circuit to take is bigger.
Summary of the invention
The present invention reads (Correlated Double Sampling) circuit relevant for a kind of row, and the circuit structure of its adjustment row reading circuit makes a row reading circuit to be used to the picture element signal that transmits on many data lines is taken a sample.So, compared to traditional row reading circuit, the row reading circuit that the present invention is correlated with has the less advantage of circuit area.
A kind of row reading circuit is proposed, in order to first and second picture element signal that transmits through first and second data line respectively in the pel array is taken a sample according to the present invention.Row reading circuit comprises first and second sample circuit, amplifier circuit and control circuit.Control circuit is taken a sample to the first replacement level and first data level of first picture element signal in order to control first sample circuit between first sampling date, and in order to control second sample circuit between second sampling date second replacement level and second data level of second picture element signal is taken a sample.The first sampling replacement level and the first sampled data level that obtains that control circuit is also taken a sample in order to output first sample circuit during the control amplifier circuit is between first period of output, and the second sampling replacement level and the second sampled data level that the sampling of output second sample circuit obtains between second period of output.
A kind of row reading circuit is proposed, in order to first and second picture element signal that transmits through first and second data line respectively in the pel array is taken a sample according to the present invention.Row reading circuit comprises amplifier circuit, control circuit, first and second sample circuit.First sample circuit comprises first and second sampling capacitor, and second sample circuit comprises the 3rd and the 4th group of electric capacity, and first termination of first to fourth sampling capacitor is received first reference voltage.Control circuit comprises first to fourth group of switch.First group of switch provides second end to first and second sampling capacitor respectively in order to first picture element signal that between first sampling date, will have replacement level and data level.Second group of switch provides respectively to second end of the 3rd and the 4th sampling capacitor in order to second picture element signal that between second sampling date, will have replacement level and data level.The 3rd group of switch in order to second end that between first period of output, couples first and second sampling capacitor to amplifier circuit, to export the replacement level and the data level of first picture element signal.The 4th group of switch in order to second end that between second period of output, couples the 3rd and the 4th sampling capacitor to amplifier circuit, to export the replacement level and the data level of second picture element signal.
Kind of a row reading circuit is proposed, in order to first and second picture element signal that transmits through first and second data line respectively in the pel array is taken a sample according to the present invention.Row reading circuit comprises amplifier circuit, control circuit, first and second sample circuit.First sample circuit comprises first and second sampling capacitor, and second sample circuit comprises the 3rd and the 4th sampling capacitor.Control circuit comprises first to fourth group of switch.First group of switch provides first end to first and second sampling capacitor respectively in order to first picture element signal that between first sampling date, will have the replacement level and have a data level.Second group of switch provides respectively to first end of the 3rd and the 4th sampling capacitor in order to second picture element signal that between second sampling date, will have the replacement level and have a data level.The 3rd group of switch in order to second end that between first period of output, couples first and second sampling capacitor to amplifier circuit, to export the replacement level and the data level of first picture element signal.The 4th group of switch in order to second end that between second period of output, couples the 3rd and the 4th sampling capacitor to amplifier circuit, to export the replacement level and the data level of second picture element signal.
Description of drawings
For letting the foregoing of the present invention can be more obviously understandable, below conjunction with figs. is elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 illustrates the calcspar of the Image sensor apparatus of the row reading circuit of using the embodiment of the invention.
Fig. 2 illustrates the circuit diagram according to the row reading circuit of first embodiment of the invention.
Fig. 3 has illustrated the coherent signal oscillogram of the row reading circuit of Fig. 2.
Fig. 4 illustrates the circuit diagram according to the line output circuit of second embodiment of the invention.
Fig. 5 illustrates the coherent signal oscillogram of the line output circuit that is Fig. 4.
Embodiment
The row of present embodiment reads the mode of (Correlated Double Sampling) circuit through sequential control can take a sample a row reading circuit to the picture element signal on many data lines.
The row reading circuit of present embodiment is in order to take a sample to first picture element signal and second picture element signal that transmit through first and second data line respectively in the pel array.Row reading circuit comprises first sample circuit, second sample circuit, amplifier circuit and control circuit.Control circuit is taken a sample to the first replacement level and first data level of first picture element signal in order to control first sample circuit between first sampling date, and in order to control second sample circuit between second sampling date second replacement level and second data level of second picture element signal is taken a sample.The first sampling replacement level and the first sampled data level that control circuit also obtains in order to output first sample circuit sampling during the control amplifier circuit is between first period of output, and the second sampling replacement level and the second sampled data level that the sampling of output second sample circuit obtains between second period of output.
First embodiment
Please with reference to Fig. 1, it illustrates the calcspar of the Image sensor apparatus of the row reading circuit of using the embodiment of the invention.Image sensor apparatus 1 comprises pel array 12, column decoder (Row Decoder) 14, row decoder (ColumnDecoder) 16, time schedule controller (Timing Controller) 18, goes and read module 20, bias circuit 22 and output processor 24.
In the present embodiment, row is read module 20 and is comprised K capable sensing circuit 20_1~20_K, and it is in order to carry out read operation to the capable pixel of M in the pel array 12, and K is the natural number less than M.In a preferred embodiment, K=M/2, that is each row sensing circuit 20_1~20_K is in order to detect the picture element signal of each pixel on the two row pixels.
Because the operation of each row sensing circuit 20_1~20_K is similar in fact; Next only go up the picture element signal P1 of transmission and the example that is operating as of the picture element signal P2 that data line SLy goes up transmission is explained with a sensing circuit 20_i reading of data line SLx; Wherein i is the natural number that is less than or equal to K, and x and y are the natural number that is less than or equal to M; In this example, data line SLx and SLy are data line adjacent one another are.
Please with reference to Fig. 2 and Fig. 3, Fig. 2 illustrates the circuit diagram according to the row reading circuit of first embodiment of the invention, and Fig. 3 illustrates the coherent signal oscillogram of the row reading circuit of Fig. 2.Row reading circuit 20_i comprises sample circuit 202,204, control circuit 206 and amplifier circuit 208.Sample circuit 202 comprises sampling capacitor C1 and C2, and sample circuit 204 comprises sampling capacitor C3 and C4.The termination of sampling capacitor C1~C4 is received reference voltage Vr1, and the other end is coupled to control circuit 206.
In addition; Because during resetting among the TR; The signal of input amplifier 208a and 208b is all reference voltage Vr2, and output signal OUT1 and OUT2 level difference among the TR during resetting are essentially the output deviation of signal value (Offset Value) of amplifier 208a and 208b.So, through the operation of TR during the aforementioned replacement, the operator also can learn the output deviation of signal value between amplifier 208a and 208b, carries out the compensation of deviate with pair amplifier 208a and 208b.
Though only explain in the present embodiment, yet row is read in the module 20 other operation of going sensing circuit and can analogized and obtain according to going the operation of sensing circuit 20_i to go picture element signal P1 and the example that is operating as of P2 that sensing circuit 20_i reads on transmission data line SLx and the SLy.Though be that the situation of data line adjacent one another are is that example is explained only in the present embodiment, yet data line SLx and SLy are not limited to data line adjacent one another are (and possibly be same data line) with data line SLx and SLy.In other example, data line SLx and SLy also can be and correspond to the data line that has the inferior pixel of same color in some pixels.
Though be that example is explained only in the present embodiment, yet K and M are not limited to satisfy aforementioned relation to go the situation that the number K of the capable sensing circuit in the read module 20 equals M/2 in fact.
Though be that example is explained in order to the situation that detects two picture element signals on the data line only in the present embodiment with row reading circuit 20_i; Yet the row reading circuit 20_i of present embodiment is not limited thereto, and also can be in order to detect the picture element signal on the data line more than three or three.
The row reading circuit of present embodiment has a plurality of sample circuits, corresponding picture element signal is taken a sample between the sampling date of correspondence in order to be controlled by control circuit.The row reading circuit of present embodiment is also exported the level of corresponding sample through controlling these a little sample circuits during control circuit is between a plurality of period of output respectively through amplifier circuit.So, compared to traditional row reading circuit, the row reading circuit that the present invention is correlated with has the less advantage of circuit area.
Second embodiment
Please with reference to Fig. 4 and Fig. 5, Fig. 4 illustrates the circuit diagram according to the line output circuit of second embodiment of the invention, and Fig. 5 has illustrated the coherent signal oscillogram of the line output circuit of Fig. 4.Different ground with first embodiment; The sample circuit 202 of present embodiment ' and 204 ' in the level at sampling capacitor C1 '~C4 ' two ends by control circuit 206 ' control circuit 206 ' also between the sampling date of correspondence, provide reference voltage Vr4 to sampling capacitor C1 '~C4 ' is provided.
More specifically say, switch SW 5 ', SW7 ' and SW9 ' respectively in response to control signal S5 ', S7 ' and S9 ' in the middle conducting of sub-scan period TS1 ', to form short circuit paths reference voltage Vr4 is provided the end to sampling capacitor C1 ' and C3 '.So, the take a sample respectively replacement level P_RST that obtains picture element signal P1 ' of sampling capacitor C1 ' and C3 ' reaches the sampling voltage V2 ' of the replacement level P_RST ' of picture element signal P2 ' with respect to reference voltage Vr4 with respect to the sampling voltage V1 ' of reference voltage Vr4.
Similarly, switch SW 6 ', SW8 ' and SW10 ' be respectively in response to control signal S6 ', S8 ' and S10 ' in the middle conducting of sub-scan period TS2 ', to form short circuit paths reference voltage Vr4 is provided the end to sampling capacitor C2 ' and C2 '.So, sampling capacitor C2 ' and C4 ' take a sample the data level P_SIGLD1 ' that obtains picture element signal P1 ' respectively with respect to the data level P_SIG ' LD2 ' of the sampling voltage V3 ' of reference voltage Vr4 and the picture element signal P2 ' sampling voltage V4 ' with respect to reference voltage Vr4.
The control circuit 206 of present embodiment ' also comprise switch SW 11, it makes the end of sampling capacitor C1 ' and C2 ' have identical voltage level in order in response to conducting during control signal S11 is during the level shift of correspondence.In an example, if through after the sampling process, A point voltage VA is replacement level P_RST, and B point voltage VB is signal level P_SIG, and C point voltage VC is Vr4, and D point voltage VD is Vr4.This moment is if open switch SW 11, capacitor C 1 ' redistribute with the electric charge on the C2 ', and A point and B point voltage VA and VB are satisfied:
C point voltage VC and D point voltage VD satisfy respectively:
So, after switch SW 11 activations, the absolute value ABS (VC-VD) of the voltage difference between C point voltage VC and DD point voltage VD satisfies:
That is the absolute value of the absolute value of the voltage difference between C point voltage VC and D point VD and A point and the B primary voltage difference of ordering is identical.In other words; The control circuit 206 of present embodiment ' provide to amplifier circuit 208 ' the absolute value ABS (VC-VD) of voltage difference equal the absolute value of resetting the difference voltage between level P_RST and signal level P_SIG in fact, and C point voltage VC and D point voltage VD adjust through over level.This moment, level adjusted C point voltage VC and D point voltage VD were provided to amplifier circuit 208 ' also output accordingly.
Similarly, the control circuit 206 of present embodiment ' comprise that also switch SW 12, its operation are the operations similar in appearance to switch SW 11, level P_RST ' and between's signal level PP_SIG ' voltage difference so that the voltage difference of C point voltage VC and D point voltage VD equals to reset.In this, and no longer its operation is given unnecessary details.
So, through the operation of switch SW 9-SW12, the line output circuit 20_i ' of present embodiment can adjust effectively provide to amplifier circuit 208 ' the level of signal.
Though only connect the end that sampling capacitor C1 ' reaches C2 ' in the present embodiment with switch SW 11 short circuits during the level shift of correspondence through conducting; And the switch SW 12 through conducting opens circuit and connects the end of sampling capacitor C3 ' and C4 '; Make capacitor C 1 ' and end capacitor C 3 of C2 ' ' and the example that the end of C4 ' has identical voltage be that example is explained, yet the line output circuit of present embodiment is not limited thereto.
In other example, also can the end that sampling capacitor C1 ' reaches C2 ' be coupled to a datum simultaneously through switch, so, also can make the end of sampling capacitor C1 ' and C2 ' have same voltage level.Similarly, also can the end that sampling capacitor C3 ' reaches C4 ' be connected to this datum simultaneously, make the end of sampling capacitor C3 ' and C4 ' have same voltage level through corresponding switch.
The row reading circuit of present embodiment also has a plurality of sample circuits between the sampling date of correspondence, corresponding picture element signal is taken a sample.And the row reading circuit of present embodiment is also exported the level of corresponding sample through controlling these a little sample circuits during control circuit is between a plurality of period of output respectively through amplifier circuit.So, compared to traditional row reading circuit, the row reading circuit that the present invention is correlated with also has the less advantage of circuit area.
Though the situation that in the above embodiment of the present invention, only has like Fig. 3 and signal output waveform OUT1 as shown in Figure 5 and OUT2 and signal output waveform OUT1 ' and OUT2 ' with the output signal of row reading circuit is that example is explained; Yet the above embodiment of the present invention only proposes several operational instances of the row reading circuit that the present invention gives prominence to; The actual waveform of the output signal of the row reading circuit that present embodiment proposes is not limited to this, and should be as the criterion with actual conditions.
In sum, though the present invention with the preferred embodiment exposure as above, yet it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes that are equal to or replacement.Therefore, protection scope of the present invention is when looking accompanying being as the criterion that the sharp scope of the application's claim defined.
Claims (16)
1. a row reading circuit is taken a sample in order to one first picture element signal that transmits through one first data line in the pel array is reached through one second picture element signal of one second data line transmission, and this row reading circuit comprises:
One first sample circuit and one second sample circuit;
One amplifier circuit; And
One control circuit; In order to this first sample circuit of control between one first sampling date the one first replacement level and one first data level of this first picture element signal are taken a sample, and the one second replacement level and one second data level of this second picture element signal are taken a sample in order to control this second sample circuit between one second sampling date;
Wherein, This control circuit also in order to control this amplifier circuit between one first period of output in this first sample circuit of output resulting one first sampling replacement level and one first sampled data level of taking a sample, and this second sample circuit of output resulting one second take a sample replacement level and one second sampled data level of taking a sample between one second period of output in.
2. row reading circuit according to claim 1 is characterized in that:
This first sample circuit comprises one first sampling capacitor and one second sampling capacitor; This first sampling capacitor is in order to take a sample to this first replacement level during one first son between this first sampling date, and this second sampling capacitor is in order to take a sample to this first data level during one second son between this first sampling date; And
This second sample circuit comprises one the 3rd sampling capacitor and one the 4th sampling capacitor; The 3rd sampling capacitor is in order to take a sample to this second replacement level during one the 3rd son between this second sampling date, and the 4th sampling capacitor is in order to take a sample to this second data level during one the 4th son between this second sampling date.
3. row reading circuit according to claim 2 is characterized in that this control circuit comprises:
One first switch and a second switch; Second input end of this first switch and this second switch all is coupled to this first data line; The first input end of this first switch is coupled to an end of this first sampling capacitor; The first input end of this second switch is coupled to first end of this second sampling capacitor, the conducting during this first son of this first switch, the conducting during this second son of this second switch; And
One the 3rd switch and one the 4th switch; Second input end of the 3rd switch and the 4th switch all is coupled to this second data line; The first input end of the 3rd switch is coupled to an end of the 3rd sampling capacitor; The first input end of the 4th switch is coupled to first end of the 4th sampling capacitor, the conducting during the 3rd son of the 3rd switch, the conducting during the 4th son of the 4th switch.
4. row reading circuit according to claim 3 is characterized in that:
This amplifier circuit comprises one first amplifier and one second amplifier; This control circuit also comprises:
One the 5th switch and one the 6th switch; The first input end of the 5th switch is coupled to this first amplifier input terminal; The first input end of the 6th switch is coupled to this second amplifier input terminal; Second input end of the 5th switch and the 6th switch all receives a reference voltage; The 5th switch provides this reference voltage to this first amplifier input terminal in during one resets, and the 6th switch provides this reference voltage to this second amplifier input terminal in during this replacement;
Trigger during this replacement in this first and this second period of output between before, and during this replacement, this first and this second period of output between stagger each other.
5. row reading circuit according to claim 4 is characterized in that this control circuit also comprises:
One minion is closed and an octavo is closed; The first input end that this minion is closed is coupled to first end of this first sampling capacitor; The first input end that this octavo is closed is coupled to first end of this second sampling capacitor; Second input end that this minion is closed is coupled to this first amplifier input terminal, and second input end that this octavo is closed is coupled to this second amplifier input terminal, the 7th and this octavo close all conductings between this first period of output; And
One the 9th switch and 1 the tenth switch; The first input end of the 9th switch is coupled to first end of the 3rd sampling capacitor; The first input end of the tenth switch is coupled to first end of the 4th sampling capacitor; Second input end of the 9th switch is coupled to this first amplifier input terminal, and second input end of the tenth switch is coupled to this second amplifier input terminal, and the 9th and the tenth switch is conducting between this second period of output all.
6. row reading circuit according to claim 4 is characterized in that this control circuit also comprises:
One minion is closed and an octavo is closed; The first input end that this minion is closed is coupled to second end of this first sampling capacitor; The first input end that this octavo is closed is coupled to second end of this second sampling capacitor; Second input end that this minion is closed is coupled to this first amplifier input terminal, and second input end that this octavo is closed is coupled to this second amplifier input terminal, the 7th and this octavo close all conductings between this first period of output; And
One the 9th switch and 1 the tenth switch; The first input end of the 9th switch is coupled to second end of the 3rd sampling capacitor; The first input end of the tenth switch is coupled to second end of the 4th sampling capacitor; Second input end of the 9th switch is coupled to this first amplifier input terminal, and second input end of the tenth switch is coupled to this second amplifier input terminal, the conducting between this second period of output of the 9th and the tenth switch.
7. row reading circuit according to claim 6 is characterized in that:
The 5th and this minion close also during this first son in conducting, so that second end of this reference voltage to this first sampling capacitor to be provided;
The 6th and this octavo close more during this second son in conducting, so that second end of this reference voltage to this second sampling capacitor to be provided;
The the 5th and the 9th switch more during the 3rd son in conducting, so that second end of this reference voltage to the 3rd sampling capacitor to be provided; And
The the 6th and the tenth switch also during the 4th son in conducting, so that second end of this reference voltage to the 4th sampling capacitor to be provided.
8. row reading circuit according to claim 6 is characterized in that this control circuit also comprises:
The 11 switch, in order to make in during one first level shift this first and first end of this second sampling capacitor have identical voltage level; And
One twelvemo is closed, and in during one second level shift, makes first end of the 3rd and the 4th sampling capacitor have identical voltage level.
9. row reading circuit according to claim 2 is characterized in that during this first and the 3rd son for during the identical operations, during this second and the 4th son be identical operations during.
10. row reading circuit according to claim 1, it is characterized in that this first and this second data line be different data line.
11. a row reading circuit is taken a sample in order to one first picture element signal that transmits through one first data line in the pel array is reached through one second picture element signal of one second data line transmission, this row reading circuit comprises:
One amplifier circuit;
One first sample circuit comprises:
One first sampling capacitor and one second sampling capacitor, first termination of this first and second sampling capacitor is received one first reference voltage;
One second sample circuit comprises:
One the 3rd sampling capacitor and one the 4th group of electric capacity, first termination of the 3rd and the 4th sampling capacitor is received this first reference voltage; And
One control circuit comprises:
One first group of switch, in order to this first picture element signal that between one first sampling date, will have one first replacement level and one first data level provide respectively to this first and second end of this second sampling capacitor;
One second group of switch provides respectively to second end of the 3rd and the 4th sampling capacitor in order to this second picture element signal that between one second sampling date, will have one second replacement level and have one second data level;
One the 3rd group of switch; In order between one first period of output, couple this first and second end of this second sampling capacitor to this amplifier circuit, with this first replacement level of exporting this first sampling capacitor sampling and this first data level of exporting this second sampling capacitor sampling; And
One the 4th group of switch; In order to second end that between one second period of output, couples the 3rd and the 4th sampling capacitor to this amplifier circuit, with this second replacement level of exporting the sampling of the 3rd sampling capacitor and export this second data level of the 4th sampling capacitor sampling.
12. row reading circuit according to claim 11 is characterized in that:
This amplifier circuit comprises one first amplifier and one second amplifier;
This control circuit also comprises:
One the 5th group of switch, in order to provide in during one resets one second reference voltage to this first and this second amplifier input terminal; And
Trigger during this replacement in this first and this second period of output between before, and during this replacement, this first and this second period of output between stagger each other.
13. a row reading circuit is taken a sample in order to one first picture element signal that transmits through one first data line in the pel array is reached through one second picture element signal of one second data line transmission, this row reading circuit comprises:
One amplifier circuit;
One first sample circuit comprises:
One first sampling capacitor and one second sampling capacitor;
One second sample circuit comprises:
One the 3rd sampling capacitor and one the 4th sampling capacitor; And
One control circuit comprises:
One first group of switch, in order to this first picture element signal that between one first sampling date, will have the one first replacement level and first data level provide respectively to this first and first end of this second sampling capacitor;
One second group of switch provides respectively to first end of the 3rd and the 4th sampling capacitor in order to this second picture element signal that between one second sampling date, will have one second replacement level and one second data level;
One the 3rd group of switch; In order between one first period of output, couple this first and second end of this second sampling capacitor to this amplifier circuit, with this first replacement level of exporting this first sampling capacitor sampling and this first data level of exporting this second sampling capacitor sampling; And
One the 4th group of switch; In order to second end that between one second period of output, couples the 3rd and the 4th sampling capacitor to this amplifier circuit, with this second replacement level of exporting the sampling of the 3rd sampling capacitor and export this second data level of the 4th sampling capacitor sampling.
14. row reading circuit according to claim 13 is characterized in that also comprising:
One the 5th group of switch, in order to one provide during resetting a reference voltage to this first and this second amplifier input terminal; And
Trigger during this replacement in this first and this second period of output between before, and during this replacement, this first and this second period of output between stagger each other.
15. row reading circuit according to claim 14 is characterized in that:
The 3rd group and the 5th group of switch also between this first sampling date in conducting, with provide this reference voltage to this first and second end of this second sampling capacitor;
The 4th group and the 5th group of switch also between this second sampling date in conducting, so that second end of this reference voltage to the 3rd and the 4th sampling capacitor to be provided.
16. row reading circuit according to claim 13 is characterized in that this control circuit also comprises;
One the 6th group of switch; In order to make in during one first level shift this first and first end of this second sampling capacitor have identical voltage level, and in during one second level shift, make first end of the 3rd and the 4th sampling capacitor have identical voltage level.
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CN1662948A (en) * | 2002-06-27 | 2005-08-31 | 卡西欧计算机株式会社 | Current drive apparatus and drive method thereof, and display apparatus using same apparatus |
CN101014991A (en) * | 2004-06-29 | 2007-08-08 | 彩光公司 | System and method for a high-performance display device having individual pixel luminance sensing and control |
JP2007249135A (en) * | 2006-03-20 | 2007-09-27 | Seiko Epson Corp | Electrooptic device, driving circuit therefor and electronic apparatus |
CN101086572A (en) * | 2006-06-05 | 2007-12-12 | Lg.菲利浦Lcd株式会社 | Liquid crystal display and driving method thereof |
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CN1662948A (en) * | 2002-06-27 | 2005-08-31 | 卡西欧计算机株式会社 | Current drive apparatus and drive method thereof, and display apparatus using same apparatus |
CN101014991A (en) * | 2004-06-29 | 2007-08-08 | 彩光公司 | System and method for a high-performance display device having individual pixel luminance sensing and control |
JP2007249135A (en) * | 2006-03-20 | 2007-09-27 | Seiko Epson Corp | Electrooptic device, driving circuit therefor and electronic apparatus |
CN101086572A (en) * | 2006-06-05 | 2007-12-12 | Lg.菲利浦Lcd株式会社 | Liquid crystal display and driving method thereof |
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