CN101739926A - Row reading circuit - Google Patents

Row reading circuit Download PDF

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Publication number
CN101739926A
CN101739926A CN200810176235A CN200810176235A CN101739926A CN 101739926 A CN101739926 A CN 101739926A CN 200810176235 A CN200810176235 A CN 200810176235A CN 200810176235 A CN200810176235 A CN 200810176235A CN 101739926 A CN101739926 A CN 101739926A
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sampling
sampling capacitor
switch
level
circuit
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CN101739926B (en
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周国煜
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Novatek Microelectronics Corp
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Novatek Microelectronics Corp
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Abstract

The invention relates to a row reading circuit for sampling a first and a second picture element signals respectively transmitted through a first and a second data lines in a picture element array. The row reading circuit comprises a first and a second sampling circuits, an amplifier circuit and a control circuit, wherein the control circuit is used for controlling the first sampling circuit to sample the reset level and the data level of the first picture element signal during first sampling and controlling the second sampling circuit to sample the reset level and the data level of the second picture element signal during second sampling. The control circuit controls the amplifier circuit to output the reset level and the data level of the first picture element signal during first sampling and output the resetting level and the data level of the second picture element signal during second sampling.

Description

Row reading circuit
Technical field
The invention relates to that a kind of row reads (Correlated Double Sampling) circuit, and particularly relevant for a kind of row reading circuit that the picture element signal that transmits on many data lines is taken a sample that is used to.
Background technology
In the prior art, row reads (Correlated Double sampling) circuit and can receive the signal that a pixel is exported, and to its back output of taking a sample.For instance, the signal that pixel is exported comprises replacement level and data level, and row reading circuit has corresponding sample circuit and respectively the replacement level and the data level of picture element signal takes a sample.Row reading circuit also comprises amplifier circuit, in order to the level output that the sample circuit sampling is obtained.
Traditionally, the number of row reading circuit needs corresponding with the size of pel array.For instance, concerning being of a size of 1600 * 1200 pel array, it need be used 1600 row reading circuits and come respectively the picture element signal that transmits on 1600 data lines wherein to be taken a sample.Bigger problem of the circuit area that will cause row reading circuit to take like this.
Summary of the invention
The present invention reads (Correlated Double Sampling) circuit relevant for a kind of row, and its circuit structure of adjusting row reading circuit makes a row reading circuit to be used to the picture element signal that transmits on many data lines is taken a sample.So, compared to traditional row reading circuit, the row reading circuit that the present invention is correlated with has the less advantage of circuit area.
A kind of row reading circuit is proposed, in order to first and second picture element signal that transmits by first and second data line respectively in the pel array is taken a sample according to the present invention.Row reading circuit comprises first and second sample circuit, amplifier circuit and control circuit.Control circuit is taken a sample to the first replacement level and first data level of first picture element signal in order to control first sample circuit between first sampling date, and in order to control second sample circuit between second sampling date second replacement level and second data level of second picture element signal is taken a sample.The first sampling replacement level and the first sampled data level that obtains that control circuit is also taken a sample in order to output first sample circuit during the control amplifier circuit is between first period of output, and the second sampling replacement level and the second sampled data level that the sampling of output second sample circuit obtains between second period of output.
A kind of row reading circuit is proposed, in order to first and second picture element signal that transmits by first and second data line respectively in the pel array is taken a sample according to the present invention.Row reading circuit comprises amplifier circuit, control circuit, first and second sample circuit.First sample circuit comprises first and second sampling capacitor, and second sample circuit comprises the 3rd and the 4th group of electric capacity, and first termination of first to fourth sampling capacitor is received first reference voltage.Control circuit comprises first to fourth group of switch.First group of switch provides second end to first and second sampling capacitor respectively in order to first picture element signal that will have replacement level and data level between first sampling date.Second group of switch provides respectively to second end of the 3rd and the 4th sampling capacitor in order to second picture element signal that will have replacement level and data level between second sampling date.The 3rd group of switch in order to second end that between first period of output, couples first and second sampling capacitor to amplifier circuit, to export the replacement level and the data level of first picture element signal.The 4th group of switch in order to second end that between second period of output, couples the 3rd and the 4th sampling capacitor to amplifier circuit, to export the replacement level and the data level of second picture element signal.
Kind of a row reading circuit is proposed, in order to first and second picture element signal that transmits by first and second data line respectively in the pel array is taken a sample according to the present invention.Row reading circuit comprises amplifier circuit, control circuit, first and second sample circuit.First sample circuit comprises first and second sampling capacitor, and second sample circuit comprises the 3rd and the 4th sampling capacitor.Control circuit comprises first to fourth group of switch.First group of switch provides first end to first and second sampling capacitor respectively in order to first picture element signal that will have the replacement level and have a data level between first sampling date.Second group of switch provides respectively to first end of the 3rd and the 4th sampling capacitor in order to second picture element signal that will have the replacement level and have a data level between second sampling date.The 3rd group of switch in order to second end that between first period of output, couples first and second sampling capacitor to amplifier circuit, to export the replacement level and the data level of first picture element signal.The 4th group of switch in order to second end that between second period of output, couples the 3rd and the 4th sampling capacitor to amplifier circuit, to export the replacement level and the data level of second picture element signal.
Description of drawings
For foregoing of the present invention can be become apparent, below conjunction with figs. is elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 illustrates the calcspar of the Image sensor apparatus of the row reading circuit of using the embodiment of the invention.
Fig. 2 illustrates the circuit diagram according to the row reading circuit of first embodiment of the invention.
Fig. 3 has illustrated the coherent signal oscillogram of the row reading circuit of Fig. 2.
Fig. 4 illustrates the circuit diagram according to the line output circuit of second embodiment of the invention.
Fig. 5 illustrates the coherent signal oscillogram of the line output circuit that is Fig. 4.
Embodiment
The row of present embodiment reads the mode of (Correlated Double Sampling) circuit by sequential control can take a sample a row reading circuit to the picture element signal on many data lines.
The row reading circuit of present embodiment is in order to take a sample to first picture element signal and second picture element signal that transmit by first and second data line respectively in the pel array.Row reading circuit comprises first sample circuit, second sample circuit, amplifier circuit and control circuit.Control circuit is taken a sample to the first replacement level and first data level of first picture element signal in order to control first sample circuit between first sampling date, and in order to control second sample circuit between second sampling date second replacement level and second data level of second picture element signal is taken a sample.The first sampling replacement level and the first sampled data level that control circuit also obtains in order to output first sample circuit sampling during the control amplifier circuit is between first period of output, and the second sampling replacement level and the second sampled data level that the sampling of output second sample circuit obtains between second period of output.
First embodiment
Please refer to Fig. 1, it illustrates the calcspar of the Image sensor apparatus of the row reading circuit of using the embodiment of the invention.Image sensor apparatus 1 comprises pel array 12, column decoder (Row Decoder) 14, row decoder (ColumnDecoder) 16, time schedule controller (Timing Controller) 18, goes and read module 20, bias circuit 22 and output processor 24.
Pel array 12 is for example for having CMOS (Complementary Metal Oxide Semiconductor) (the ComplementaryMetal Oxide Semiconductor of size M * N, CMOS) pel array, it produces the sensing image that is of a size of M * N pixel in order to induction, and wherein M and N are the natural number greater than 1.Pel array 12 is controlled by column decoder 14, row decoder 16, time schedule controller 18 and bias circuit 22, and the sensing image of its generation can be read module 20 and output processor 24 outputs by data line SL1～SLM, row.
In the present embodiment, row is read module 20 and is comprised K capable sensing circuit 20_1～20_K, and it is in order to carry out read operation to the capable pixel of M in the pel array 12, and K is the natural number less than M.In a preferred embodiment, K=M/2, that is each row sensing circuit 20_1～20_K is in order to detect the picture element signal of each pixel on the two row pixels.
Because the operation of each row sensing circuit 20_1～20_K is similar in fact, next only explain with the picture element signal P1 of the last transmission of a sensing circuit 20_i reading of data line SLx and the example that is operating as of the last picture element signal P2 that transmits of data line SLy, wherein i is the natural number that is less than or equal to K, and x and y are the natural number that is less than or equal to M; In this example, data line SLx and SLy are data line adjacent one another are.
Please refer to Fig. 2 and Fig. 3, Fig. 2 illustrates the circuit diagram according to the row reading circuit of first embodiment of the invention, and Fig. 3 illustrates the coherent signal oscillogram of the row reading circuit of Fig. 2.Row reading circuit 20_i comprises sample circuit 202,204, control circuit 206 and amplifier circuit 208.Sample circuit 202 comprises sampling capacitor C1 and C2, and sample circuit 204 comprises sampling capacitor C3 and C4.The termination of sampling capacitor C1～C4 is received reference voltage Vr1, and the other end is coupled to control circuit 206.
Control circuit 206 comprises switch SW 1 and SW2, and the first input end of switch SW 1 and SW2 is coupled to sampling capacitor C1 and C2 respectively, and second input end is in order to receive picture element signal P1.Switch SW 1 is controlled by control signal S1 conducting among the TS1 during subsample, to provide picture element signal P1 to sampling capacitor C1.This moment, picture element signal P1 had replacement level LS1, and so sampling capacitor C1 takes a sample and obtains resetting the sampling voltage V1 of level LS1 with respect to reference voltage Vr1.Switch SW 2 is controlled by control signal S2 conducting among the TS2 during subsample, to provide picture element signal P1 to sampling capacitor C2.This moment, picture element signal P1 had data level LD1, and so sampling capacitor C2 sampling obtains the sampling voltage V2 of data level LD1 with respect to reference voltage Vr1.
Control circuit 206 also comprises switch SW 3 and SW4, its circuit structure and operation are similar in appearance to switch SW 1 and SW2, in response to conducting during control signal S3 and S4 are during the subsample of correspondence, sampling capacitor C3 and C4 are taken a sample obtain level LS2 and data level LD2 sampling voltage V3 and the V4 that reset with respectively respectively with respect to reference voltage Vr1.In the present embodiment, the waveform of control signal S3 and S4 equals the waveform of control signal S1 and S2 in fact, and for example respectively gauge tap SW3 and SW4 conducting among TS1 and the TS2 during subsample of control signal S3 and S4.
Amplifier circuit 208 comprises amplifier 208a and 208b, and in one embodiment, amplifier 208a and 208b have source follower (Source Follower) configuration.In this embodiment, the signal that received in order to pair amplifier 208a and 208b of amplifier circuit 208 carries out difference and amplifies.
Control circuit 206 comprises switch SW 5 and SW6, and the first input end of switch SW 5 and SW6 is coupled to sampling capacitor C1 and C2 respectively, and second input end couples the input end of amplifier 208a and 208b respectively.Switch SW 5 and SW6 are controlled by control signal S5 and S6 conducting among the TO1 between period of output respectively, with sampling voltage V1 and V2 difference input amplifier 208a and the 208b with sampling capacitor C1 and C2 sampling, accordingly output signal OUT1 and OUT2 are exported.
Control circuit 206 also comprises switch SW 7 and SW8, its circuit structure and operation are similar in appearance to switch SW 5 and SW6, the conducting among the TO2 between period of output in response to control signal S7 and S8 respectively, with sampling voltage V3 and V4 difference input amplifier 208a and 208b, make amplifier 208a and 208b accordingly with output signal OUT1 and OUT2 output with sampling capacitor C3 and C4 sampling.
Control circuit 206 also comprises switch SW 9 and SW10, and the first input end of switch SW 9 and SW10 is coupled to the input end of amplifier 208a and 208b respectively, and second input end receives reference voltage Vr2.Switch SW 9 and SW10 are controlled by control signal S9 and S10 conducting among the TR during resetting respectively, so that reference voltage Vr2 to be provided the input end to amplifier 208a and 208b.So, can reset to reference voltage Vr2 at the incoming level that enters between period of output before the TO1 and TO2 earlier amplifier 208a and 208b.So, can avoid the output signal OUT1 of amplifier 208a and 208b generation and the level of OUT2 to be subjected to the image of last input signal and to produce skew.
In addition, because during resetting among the TR, the signal of input amplifier 208a and 208b is all reference voltage Vr2, and output signal OUT1 and the OUT2 level difference among the TR during resetting is essentially the output signal deviate (Offset Value) of amplifier 208a and 208b.So, by the operation of TR during the aforementioned replacement, the operator also can learn the output signal deviate between amplifier 208a and 208b, carries out the compensation of deviate with pair amplifier 208a and 208b.
Though only sensing circuit 20_i reads picture element signal P1 on transmission data line SLx and the SLy and the example that is operating as of P2 explains to go in the present embodiment, yet row is read operation of other row sensing circuit in the module 20 and can be analogized according to the operation of row sensing circuit 20_i and obtain.Though be that the situation of data line adjacent one another are is that example explains only in the present embodiment, yet data line SLx and SLy are not limited to data line adjacent one another are (and may be same data line) with data line SLx and SLy.In other example, data line SLx and SLy also can be and correspond to the data line that has the inferior pixel of same color in some pixels.
Though be that example explains only in the present embodiment, yet K and M are not limited to satisfy aforementioned relation to go the situation that the number K of the capable sensing circuit in the read module 20 equals M/2 in fact.
Though be that example explains in order to the situation that detects two picture element signals on the data line only in the present embodiment with row reading circuit 20_i, yet the row reading circuit 20_i of present embodiment is not limited thereto, and also can be in order to detect the picture element signal on the data line more than three or three.
The row reading circuit of present embodiment has a plurality of sample circuits, corresponding picture element signal is taken a sample between the sampling date of correspondence in order to be controlled by control circuit.The row reading circuit of present embodiment is also exported the level of corresponding sample by controlling these a little sample circuits during control circuit is between a plurality of period of output respectively by amplifier circuit.So, compared to traditional row reading circuit, the row reading circuit that the present invention is correlated with has the less advantage of circuit area.
Second embodiment
Please refer to Fig. 4 and Fig. 5, Fig. 4 illustrates the circuit diagram according to the line output circuit of second embodiment of the invention, and Fig. 5 has illustrated the coherent signal oscillogram of the line output circuit of Fig. 4.With first embodiment differently, the sample circuit 202 of present embodiment ' and 204 ' in the level at sampling capacitor C1 '～C4 ' two ends by control circuit 206 ' control circuit 206 ' also provide reference voltage Vr4 to sampling capacitor C1 '～C4 ' between the sampling date of correspondence is provided.
More specifically say, switch SW 5 ', SW7 ' and SW9 ' respectively in response to control signal S5 ', S7 ' and S9 ' in the middle conducting of sub-scan period TS1 ', provide reference voltage Vr4 end to form short circuit paths to sampling capacitor C1 ' and C3 '.So, the take a sample respectively replacement level P_RST that obtains picture element signal P1 ' of sampling capacitor C1 ' and C3 ' reaches the sampling voltage V2 ' of the replacement level P_RST ' of picture element signal P2 ' with respect to reference voltage Vr4 with respect to the sampling voltage V1 ' of reference voltage Vr4.
Similarly, switch SW 6 ', SW8 ' and SW10 ' be respectively in response to control signal S6 ', S8 ' and S10 ' in the middle conducting of sub-scan period TS2 ', provide reference voltage Vr4 end to form short circuit paths to sampling capacitor C2 ' and C2 '.So, sampling capacitor C2 ' and C4 ' take a sample the data level P_SIGLD1 ' that obtains picture element signal P1 ' respectively with respect to the data level P_SIG ' LD2 ' of the sampling voltage V3 ' of reference voltage Vr4 and the picture element signal P2 ' sampling voltage V4 ' with respect to reference voltage Vr4.
The control circuit 206 of present embodiment ' also comprise switch SW 11, it makes the end of sampling capacitor C1 ' and C2 ' have identical voltage level in order in response to conducting during control signal S11 is during the level shift of correspondence.In an example, if through after the sampling process, A point voltage VA is replacement level P_RST, and B point voltage VB is signal level P_SIG, and C point voltage VC is Vr4, and D point voltage VD is Vr4.This moment is if open switch SW 11, capacitor C 1 ' redistribute with the electric charge on the C2 ', and A point and B point voltage VA and VB are satisfied:
VA = VB = 1 2 ( P _ RST + P _ SIG )
C point voltage VC and D point voltage VD satisfy respectively:
VC = Vr 4 - 1 2 ( P _ RST - P _ SIG )
VD = Vr 4 - 1 2 ( P _ SIG - P _ RST )
So, after switch SW 11 activations, the absolute value ABS (VC-VD) of the voltage difference between C point voltage VC and DD point voltage VD satisfies:
ABS ( VC - VD ) = | VC - VD | = | Vr 4 - 1 2 ( P _ SIG - P _ RST ) - { Vr 4 - 1 2 ( P _ RST - P _ SIG ) } |
= | P _ RST - P _ SIG |
That is the absolute value of the absolute value of the voltage difference between C point voltage VC and D point VD and A point and the B primary voltage difference of ordering is identical.In other words, the control circuit 206 of present embodiment ' provide to amplifier circuit 208 ' the absolute value ABS (VC-VD) of voltage difference equal the absolute value of resetting the difference voltage between level P_RST and signal level P_SIG in fact, and C point voltage VC and D point voltage VD are through the over level adjustment.This moment, level adjusted C point voltage VC and D point voltage VD were provided to amplifier circuit 208 ' also output accordingly.
Similarly, the control circuit 206 of present embodiment ' comprise that also switch SW 12, its operation are the operations similar in appearance to switch SW 11, level P_RST ' and between's signal level PP_SIG ' voltage difference so that the voltage difference of C point voltage VC and D point voltage VD equals to reset.In this, and no longer its operation is given unnecessary details.
So, by the operation of switch SW 9-SW12, the line output circuit 20_i ' of present embodiment can adjust effectively provide to amplifier circuit 208 ' the level of signal.
Though in the present embodiment only during the level shift of correspondence, to connect the end of sampling capacitor C1 ' and C2 ' by switch SW 11 short circuits of conducting, and the switch SW 12 by conducting opens circuit and connects the end of sampling capacitor C3 ' and C4 ', make capacitor C 1 ' and end capacitor C 3 of C2 ' ' and the example that the end of C4 ' has identical voltage be that example explains, yet the line output circuit of present embodiment is not limited thereto.
In other example, also can the end that sampling capacitor C1 ' reaches C2 ' be coupled to a datum simultaneously by switch, so, also can make the end of sampling capacitor C1 ' and C2 ' have same voltage level.Similarly, also can the end that sampling capacitor C3 ' reaches C4 ' be connected to this datum simultaneously, make the end of sampling capacitor C3 ' and C4 ' have same voltage level by the switch of correspondence.
The row reading circuit of present embodiment also has a plurality of sample circuits between the sampling date of correspondence corresponding picture element signal is taken a sample.And the row reading circuit of present embodiment is also exported the level of corresponding sample by controlling these a little sample circuits during control circuit is between a plurality of period of output respectively by amplifier circuit.So, compared to traditional row reading circuit, the row reading circuit that the present invention is correlated with also has the less advantage of circuit area.
Though the situation that only has as Fig. 3 and signal output waveform OUT1 as shown in Figure 5 and OUT2 and signal output waveform OUT1 ' and OUT2 ' with the output signal of row reading circuit in the above embodiment of the present invention is that example explains, yet the above embodiment of the present invention only proposes several operational instances of the row reading circuit that the present invention gives prominence to, the actual waveform of the output signal of the row reading circuit that present embodiment proposes is not limited to this, and should be as the criterion with actual conditions.
In sum, though the present invention with the preferred embodiment exposure as above, yet it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various changes that are equal to or replacement.Therefore, protection scope of the present invention is when looking accompanying being as the criterion that the sharp scope of the application's claim defined.

Claims (16)

1. a row reading circuit is taken a sample in order to one first picture element signal that transmits by one first data line in the pel array is reached by one second picture element signal of one second data line transmission, and this row reading circuit comprises:
One first sample circuit and one second sample circuit;
One amplifier circuit; And
One control circuit, in order to this first sample circuit of control between one first sampling date the one first replacement level and one first data level of this first picture element signal are taken a sample, and the one second replacement level and one second data level of this second picture element signal are taken a sample in order to control this second sample circuit between one second sampling date;
Wherein, this control circuit also in order to control this amplifier circuit between one first period of output in this first sample circuit of output resulting one first sampling replacement level and one first sampled data level of taking a sample, and this second sample circuit of output resulting one second take a sample replacement level and one second sampled data level of taking a sample between one second period of output in.
2. row reading circuit according to claim 1, it is characterized in that this first and this second sample circuit comprise respectively:
One first sampling capacitor and one second sampling capacitor respectively in order to during one first son between this first sampling date this first replacement level is taken a sample, reach in order to during one second son between this first sampling date this first data level is taken a sample; And
One the 3rd sampling capacitor and one the 4th sampling capacitor in order to during one the 3rd son between this second sampling date this second replacement level is taken a sample, reach in order to during one the 4th son between this second sampling date this second data level is taken a sample respectively.
3. row reading circuit according to claim 2 is characterized in that this control circuit comprises:
One first switch and a second switch, first input end is coupled to this first data line, second input end is coupled to an end of this first sampling capacitor and first end of this second sampling capacitor respectively, this first and this second switch respectively at this first and this second son during conducting; And
One the 3rd switch and one the 4th switch, first input end is coupled to this second data line, second input end is coupled to an end of the 3rd sampling capacitor and first end of the 4th sampling capacitor respectively, the 3rd and the 4th switch respectively at the 3rd and the 4th son during conducting.
4. row reading circuit according to claim 3 is characterized in that:
This amplifier circuit comprises one first amplifier and one second amplifier; This control circuit also comprises:
One the 5th switch and one the 6th switch, first input end be coupled to respectively this first and this second amplifier input terminal, second input end receives a reference voltage, the 5th and the 6th switch in order to provide in during one resets this reference voltage to this first and this second amplifier input terminal;
Trigger during this replacement in this first and this second period of output between before, and during this replacement, this first and this second period of output between stagger mutually.
5. row reading circuit according to claim 4 is characterized in that this control circuit also comprises:
One minion is closed and an octavo is closed, first input end be coupled to respectively this first and first end of this second sampling capacitor, second input end be coupled to respectively this first and this second amplifier input terminal, the 7th and this octavo about conducting between this first period of output; And
One the 9th switch and 1 the tenth switch, first input end is coupled to first end of the 3rd and the 4th sampling capacitor respectively, second input end be coupled to respectively this first and this second amplifier input terminal, the conducting between this second period of output of the 9th and the tenth switch.
6. row reading circuit according to claim 4 is characterized in that this control circuit also comprises:
One minion is closed and an octavo is closed, first input end be coupled to respectively this first and second end of this second sampling capacitor, second input end be coupled to respectively this first and this second amplifier input terminal, the 7th and this octavo about conducting between this first period of output; And
One the 9th switch and 1 the tenth switch, first input end is coupled to second end of the 3rd and the 4th sampling capacitor respectively, second input end be coupled to respectively this first and this amplifier input terminal, the conducting between this second period of output of the 9th and the tenth switch.
7. row reading circuit according to claim 6 is characterized in that:
The 5th and this minion close also during this first son in conducting, so that second end of this reference voltage to this first sampling capacitor to be provided;
The 6th and this octavo close more during this second son in conducting, so that second end of this reference voltage to this second sampling capacitor to be provided;
The the 5th and the 9th switch more during the 3rd son in conducting, so that second end of this reference voltage to the 3rd sampling capacitor to be provided; And
The the 6th and the tenth switch also during the 4th son in conducting, so that second end of this reference voltage to the 4th sampling capacitor to be provided.
8. row reading circuit according to claim 6 is characterized in that this control circuit also comprises:
The 11 switch, in order to make in during one first level shift this first and first end of this second sampling capacitor have identical voltage level; And
One twelvemo is closed, and makes first end of the 3rd and the 4th sampling capacitor have identical voltage level in during one second level shift.
9. row reading circuit according to claim 2 is characterized in that during this first and the 3rd son for during the identical operations, during this second and the 4th son be identical operations during.
10. row reading circuit according to claim 1, it is characterized in that this first and this second data line be different data line.
11. a row reading circuit is taken a sample in order to one first picture element signal that transmits by one first data line in the pel array is reached by one second picture element signal of one second data line transmission, this row reading circuit comprises:
One amplifier circuit;
One first sample circuit comprises:
One first sampling capacitor and one second sampling capacitor, first termination of this first and second sampling capacitor is received one first reference voltage;
One second sample circuit comprises:
One the 3rd sampling capacitor and one the 4th group of electric capacity, first termination of the 3rd and the 4th sampling capacitor is received this first reference voltage; And
One control circuit comprises:
One first group of switch, in order to this first picture element signal that between one first sampling date, will have one first replacement level and this first picture element signal with one first data level provide respectively to this first and second end of this second sampling capacitor;
One second group of switch provides respectively to second end of the 3rd and the 4th sampling capacitor in order to this second picture element signal that will have one second replacement level between one second sampling date and this second picture element signal with one second data level;
One the 3rd group of switch, in order between one first period of output, couple this first and second end of this second sampling capacitor to this amplifier circuit, with this first replacement level of exporting this first sampling capacitor sampling and this first data level of exporting this second sampling capacitor sampling; And
One the 4th group of switch, in order to second end that between one second period of output, couples the 3rd and the 4th sampling capacitor to this amplifier circuit, with this second replacement level of exporting the sampling of the 3rd sampling capacitor and export this second data level of the 4th sampling capacitor sampling.
12. row reading circuit according to claim 11 is characterized in that:
This amplifier circuit comprises one first amplifier and one second amplifier;
This control circuit also comprises:
One the 5th group of switch, in order to provide in during one resets one second reference voltage to this first and this second amplifier input terminal; And
Trigger during this replacement in this first and this second period of output between before, and during this replacement, this first and this second period of output between stagger mutually.
13. a row reading circuit is taken a sample in order to one first picture element signal that transmits by one first data line in the pel array is reached by one second picture element signal of one second data line transmission, this row reading circuit comprises:
One amplifier circuit;
One first sample circuit comprises:
One first sampling capacitor and one second sampling capacitor;
One second sample circuit comprises:
One the 3rd sampling capacitor and one the 4th sampling capacitor; And
One control circuit comprises:
One first group of switch, in order to this first picture element signal that between one first sampling date, will have one first replacement level and this first picture element signal with one first data level provide respectively to this first and first end of this second sampling capacitor;
One second group of switch provides respectively to first end of the 3rd and the 4th sampling capacitor in order to this second picture element signal that will have one second replacement level between one second sampling date and this second picture element signal with one second data level;
One the 3rd group of switch, in order between one first period of output, couple this first and second end of this second sampling capacitor to this amplifier circuit, with this first replacement level of exporting this first sampling capacitor sampling and this first data level of exporting this second sampling capacitor sampling; And
One the 4th group of switch, in order to second end that between one second period of output, couples the 3rd and the 4th sampling capacitor to this amplifier circuit, with this second replacement level of exporting the sampling of the 3rd sampling capacitor and export this second data level of the 4th sampling capacitor sampling.
14. row reading circuit according to claim 13 is characterized in that also comprising:
One the 5th group of switch, in order to one provide during resetting a reference voltage to this first and this second amplifier input terminal; And
Trigger during this replacement in this first and this second period of output between before, and during this replacement, this first and this second period of output between stagger mutually.
15. row reading circuit according to claim 14 is characterized in that:
The 3rd group and the 5th group of switch also between this first sampling date in conducting, with provide this reference voltage to this first and second end of this second sampling capacitor;
The 4th group and the 5th group of switch also between this second sampling date in conducting, so that second end of this reference voltage to the 3rd and the 4th sampling capacitor to be provided.
16. row reading circuit according to claim 13 is characterized in that this control circuit also comprises:
One the 6th group of switch, in order to make in during one first level shift this first and first end of this second sampling capacitor have identical voltage level, and in during one second level shift, make first end of the 3rd and the 4th sampling capacitor have identical voltage level.
CN2008101762350A 2008-11-14 2008-11-14 Row reading circuit Expired - Fee Related CN101739926B (en)

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CN101739926B CN101739926B (en) 2012-03-14

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