CN101415064B - Image sensing apparatus and imaging system - Google Patents
Image sensing apparatus and imaging system Download PDFInfo
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- CN101415064B CN101415064B CN2008101491096A CN200810149109A CN101415064B CN 101415064 B CN101415064 B CN 101415064B CN 2008101491096 A CN2008101491096 A CN 2008101491096A CN 200810149109 A CN200810149109 A CN 200810149109A CN 101415064 B CN101415064 B CN 101415064B
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Abstract
The invention provides an image sensing apparatus and an imaging system. The image sensing apparatus comprises a pixel including, a column signal line, a readout circuit, an output line, and an output unit. The readout circuit includes a first accumulation unit, a first opening/closing unit, a second accumulation unit, a transmission unit, and a second opening/closing unit. A capacitance of the first accumulation unit is smaller than a capacitance of the second accumulation unit, and the signal held by the second accumulation unit is read out to the output unit based on the capacitance of the second accumulation unit and the capacitance of the output line.
Description
Technical field
The present invention relates to image sensing apparatus and imaging system.
Background technology
Open disclosed technology among the No.2001-45378 according to the Japan Patent spy, in the pel array of a plurality of pixels of on comprising line direction and column direction, arranging, via a plurality of capable control line that on line direction, extends drive signal is supplied to pixel, and via a plurality of column signal lines that on column direction, extend from the pixel read output signal.Build up each end that the unit is connected to column signal line.When just from two read output signals building up the unit, the signal of exporting from pixel accumulates in another accumulation unit.This has shortened the blank period (period that does not have transducer output) and be used for that signal is read into accumulation the whole of unit from pel array reads the period.
Open in the technology of No.11-150255 the Japan Patent spy, build up unit and two amplifiers for two and alternately be connected in a plurality of column signal lines each.The signal of being built up in described two of building up in the unit is amplified and output by one in described two amplifiers, is accumulated in another then and builds up in the unit.Build up the signal of building up in the unit at another and amplified, be read out the output line of following stages then by another amplifier.
Open in the technology of No.2001-45378 the Japan Patent spy, accumulated in one from the signal of pixel of first row of pel array and build up in the unit, built up in unit and accumulate in another from the signal of the pixel of second row.Build up unit from each and be transferred to the signal times of output line of following stages with gain based on the determined electric capacity splitting ratio of capacitance of the capacitance of building up the unit by each and output line.For example, have capacitance C1 when building up the unit, and output line is when having capacitance C2, gain is provided by C1/ (C1+C2).The capacitance of output line comprises its parasitic capacitance and by the capacitance that capacity cell generated that is provided on output line.Open in the sensing technique of No.2001-45378 the Japan Patent spy who uses this electric capacity to cut apart, build up the absolute value hour that unit and another are built up the electric capacity of each in the unit when one, the gain of building up the electric capacity splitting ratio between the electric capacity of unit based on the output line of following stages and each diminishes, and signal to noise ratio reduces.Conversely, build up unit and another and build up each the absolute value of electric capacity in the unit when big when one, the gain of building up the electric capacity splitting ratio between the electric capacity of unit based on output line and each of following stages becomes big, and the signal to noise ratio rising.Yet this has increased by one builds up unit and another and builds up each electrode area in unit, has caused the chip area increase.
Open the technology of No.11-150255 according to the Japan Patent spy, build up the signal of being built up in unit at another and amplify, and be read out following stages, as mentioned above by another amplifier.Therefore, this signal might be read into the output line of following stages, and not consider gain based on the electric capacity splitting ratio.Yet because for a signal, two amplifiers are connected to each in a plurality of column signal lines, so the chip area of image sensing apparatus may increase.In addition, owing to two amplifiers are operated in order to read a signal, therefore in image sensing apparatus, may increase in whole overall power of reading in the period.
Summary of the invention
The invention provides image sensing apparatus and imaging system, itself in addition when at full speed reading picture element signal, also can reduce chip area, and suppress power consumption and increase.
According to first aspect present invention, a kind of image sensing apparatus is provided, comprising: pixel, it comprises photoelectric conversion unit; Column signal line, it is connected to described pixel; Reading circuit, its via described column signal line from described pixel read output signal; Output line, it is connected to described reading circuit, and has electric capacity; And output unit, it is via described output line, and according to from the signal of described reading circuit and output image signal, wherein, described reading circuit comprises: first builds up the unit, and its maintenance reads into the signal of described column signal line; The first cut-off/close unit, the described column signal line of its cut-off/close is built up being connected between the unit with described first; Second builds up the unit; Delivery unit, it will be built up the signal that the unit kept by described first and be sent to the described second accumulation unit; And the second cut-off/close unit, the described delivery unit of its cut-off/close is built up being connected between the unit with described second, described first electric capacity of building up the unit is less than described second electric capacity of building up the unit, builds up signal that the unit kept by described second and built up the electric capacity of the electric capacity of unit and described output line and read into described output unit based on described second.
According to second aspect present invention, a kind of image sensing apparatus is provided, comprising: first pixel; Second pixel; Column signal line, it is connected to described first pixel and described second pixel; Reading circuit, its via described column signal line from described first pixel and the described second pixel read output signal; Driver element, it drives described first pixel, described second pixel and described reading circuit; Output line, it is connected to described reading circuit, and has electric capacity; And output unit, it is via described output line, and according to from the signal of described reading circuit and output image signal, wherein, described reading circuit comprises: first builds up the unit, and its maintenance reads into the signal of described column signal line; The first cut-off/close unit, the described column signal line of its cut-off/close is built up being connected between the unit with described first; Second builds up the unit; Delivery unit, it will be built up signal that the unit kept by described first and be sent to described second and build up the unit, and its input terminal and lead-out terminal be connected to described first and build up the unit, and its lead-out terminal is connected to described second and builds up the unit; And the second cut-off/close unit, its cut-off/close described first builds up the unit and described delivery unit is built up being connected between the unit with described second, described first builds up the electric capacity of the electric capacity of unit less than the described second accumulation unit, building up signal that the unit kept by described second is built up the electric capacity of the electric capacity of unit and described output line and is read into described output unit based on described second, and described first pixel of described drive unit drives, described second pixel and described reading circuit, with during first period, build up the unit from described first and read the signal of described first pixel, and communicate the signals to described second via described delivery unit and build up the unit, and during second period after described first period, make described first to build up the unit signal of described second pixel that outputs to described column signal line is built up, and build up the unit from described second and read the signal of described first pixel, and communicate the signals to described output unit.
According to third aspect present invention and fourth aspect, a kind of imaging system is provided, it comprises: according to the image sensing apparatus of corresponding first aspect of the present invention and second aspect; Optical system, it forms image on the image planes of described image sensing apparatus; Signal processing unit, it handles the signal of exporting from described image sensing apparatus, to generate view data.
According to the present invention, even at full speed reading in the picture element signal, also might reduce chip area and suppress power consumption increases.
According to below in conjunction with the description of accompanying drawing to exemplary embodiment, further feature of the present invention will become apparent.
Description of drawings
Fig. 1 is the view that illustrates according to the layout of the image sensing apparatus of first embodiment of the invention;
Fig. 2 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown;
Fig. 3 is the sequential chart that the operation of reading circuit is shown;
Fig. 4 is the circuit diagram that the circuit arrangement of delivery unit is shown;
Fig. 5 illustrates the block diagram of use according to the layout of the imaging system of the image sensing apparatus of first embodiment;
Fig. 6 is the view that illustrates according to the layout of the image sensing apparatus 300 of second embodiment of the invention;
Fig. 7 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown;
Fig. 8 is the view that illustrates according to the layout of the image sensing apparatus 600 of third embodiment of the invention;
Fig. 9 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown;
Figure 10 is the sequential chart that the operation of reading circuit is shown;
Figure 11 is the view that is used to explain reset potential;
Figure 12 is the circuit diagram (modified example) that the circuit arrangement of the row of one in the reading circuit is shown;
Figure 13 is the view that illustrates according to the layout of the image sensing apparatus 800 of fourth embodiment of the invention;
Figure 14 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown;
Figure 15 is the sequential chart that the operation of reading circuit is shown;
Figure 16 is the circuit diagram that the layout of output unit is shown;
Figure 17 is the view that illustrates according to the layout of the image sensing apparatus 900 of fifth embodiment of the invention;
Figure 18 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown;
Figure 19 is the sequential chart that the operation of reading circuit is shown;
Figure 20 is the sequential chart that the operation of reading circuit is shown;
Figure 21 is the view that illustrates according to the layout of the image sensing apparatus 1000 of sixth embodiment of the invention;
Figure 22 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown;
Figure 23 is the sequential chart that the operation of reading circuit is shown;
Figure 24 is the sequential chart that the operation of reading circuit is shown.
Embodiment
The present invention is particularly at video camera, digital still video camera, the widely used image sensing apparatus of image input device or the like that is used for image reading apparatus.
With reference to the image sensing apparatus 100 of Fig. 1 description according to first embodiment of the invention.Fig. 1 is the view that illustrates according to the layout of the image sensing apparatus 100 of first embodiment of the invention.
Pel array PA comprises a plurality of pixel A 11 to B24, and it is pressed two-dimensional approach (with matrix form) and arranges.For convenience of description, will be example at this array with 4 * 4 pixels.
In the pixel A 11 to B24 each comprises photoelectric conversion unit PD.Photoelectric conversion unit PD is a photodiode for example.
Vertical scanning circuit (VSR) 101 supplies to pixel A 11 to B24 via row control line CL1 to CL4 with drive signal.For example, vertical scanning circuit (VSR) 101 makes pixel of each row among the pel array PA that signal is outputed to one of correspondence among the column signal line RL1 to RL4.
The first cut-off/close unit group 103 is included as a plurality of first cut-off/close unit that each row provide.
First builds up unit group 104 is included as a plurality of first accumulation unit that each row provide.First builds up the signal that the unit keeps outputing to column signal line RL1 to RL4.
The second cut-off/close unit group 106 is included as a plurality of second cut-off/close unit that each row provide.Second builds up unit group 107 is included as a plurality of second accumulation unit that each row provide.
The 3rd cut-off/close unit group 108 is included as a plurality of the 3rd cut-off/close unit that each row provide.The 3rd cut-off/close unit cut-off/close second is built up being connected between unit and the first horizontal output line 121 or the second horizontal output line 122.For example, the 3rd cut-off/close unit is built up the unit and the first horizontal output line 121 or the second horizontal output line 122 with second and is set to closure state, builds up the unit with second thus and is electrically connected to the first horizontal output line 121 or the second horizontal output line 122.
Horizontal scanning circuit (HSR) 102 makes that successively the horizontal time-base (HSR) of the layout will supply to each row in the reading circuit is effective, thus the 3rd cut-off/close unit of closed each row successively.By this operation, horizontal scanning circuit (HSR) 102 makes the 3rd cut-off/close unit group 108 from each row (second build up unit) read output signal of reading circuit 110, and via the first horizontal output line 121 and the second horizontal output line 122 described signal is outputed to output unit 120.
In the first horizontal output line 121 and the second horizontal output line 122 each is connected to output unit 120 with reading circuit 110 (second build up unit).
Next the layout of reading circuit 110 is described with reference to Fig. 2.Fig. 2 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit 110 is shown.To the circuit that be connected to column signal line RL1 be described mainly.This situation also is applied to be connected to the circuit of all the other column signal line RL2 to RL4.
For example, first pixel A 11 and second pixel B 11 (Fig. 1) are connected to the upstream side of column signal line RL1.The downstream that unit 203, delivery unit 204, the second cut-off/close unit 205, the second accumulation unit 206 and the 3rd cut-off/close unit 220 are connected to column signal line RL1 is successively built up in the first cut-off/close unit 210, first.The first horizontal output line 121 and the second horizontal output line 122 (Fig. 1) are connected to the following stages of the 3rd cut-off/close unit 220.
The first cut-off/close unit 210 comprises optical signalling switch 201 and noise signal switch 202.First builds up unit 203 comprises that optical signalling is built up unit (that is, be used for first of optical signalling and build up the unit) Cts1 and noise signal is built up unit (that is, be used for first of noise signal and build up the unit) Ctn1.Delivery unit 204 comprises optical signalling buffer amplifier AMS and noise signal buffer amplifier AMN, and they are impedance transformers.The second cut-off/close unit 205 comprises optical signalling switch 231 and noise signal switch 232.Second builds up unit 206 comprises that optical signalling is built up unit (that is, be used for second of optical signalling and build up the unit) Cts2 and noise signal is built up unit (that is, be used for second of noise signal and build up the unit) Ctn2.The 3rd cut-off/close unit 220 comprises optical signalling switch 207 and noise signal switch 208.
In the circuit arrangement of row shown in Figure 2, each switch 201 or the like can or comprise nmos pass transistor, or comprises the PMOS transistor.
Next the operation of reading circuit 110 will be described.Fig. 3 is the sequential chart that the operation of reading circuit 110 is shown.All signals described in Fig. 3 all are effective at high level.It should be noted that to provide signal in the effective situation of low level by all signal logic level that reverse.In Fig. 3, signal psi TS1, φ TN1 and φ TSN2 are supplied to reading circuit 110 from vertical scanning circuit (VSR) 101.Signal HSR is supplied to reading circuit 110 from horizontal scanning circuit (HSR) 102.
During the BLKa period (that is, second period), making the effective while of φ TN1, connect switch 202, thereby noise signal is built up Ctn1 accumulation in unit outputs to column signal line RL1 from first pixel A 11 noise signal.Making the effective while of φ TS1, connecting switch 201, thereby optical signalling is built up Cts1 accumulation in unit outputs to column signal line RL1 from first pixel A 11 optical signalling.That is to say that first builds up unit 203 builds up the signal that outputs to column signal line RL1 from first pixel A 11.
During the BLKc period (that is, first period), making the effective while of φ TSN2, connect switch 231 and 232.Optical signalling buffer amplifier AMS builds up unit Cts1 from optical signalling and reads the optical signalling of first pixel A 11, and sends it to optical signalling accumulation unit Cts2.Noise signal buffer amplifier AMN builds up unit Ctn1 from noise signal and reads the noise signal of first pixel A 11, and sends it to noise signal accumulation unit Ctn2.That is to say that delivery unit 204 is built up unit 203 from first and read the signal of first pixel A 11, and send it to the second accumulation unit 206.
At period BLKc (promptly, first period) during the BLKb period afterwards (that is, second period), making the effective while of φ TN1, connect switch 202, thereby noise signal is built up Ctn1 accumulation in unit outputs to column signal line RL1 from second pixel B 11 noise signal.Making the effective while of φ TS1, connecting switch 201, thereby optical signalling is built up Cts1 accumulation in unit outputs to column signal line RL1 from second pixel B 11 optical signalling.That is to say that first builds up unit 203 builds up the signal that outputs to column signal line RL1 from second pixel B 11.
During period BLKb (that is, second period), in the feasible effective while of signal HSR1 that is used for the column signal line RL1 of horizontal time-base HSR, connect switch 207 and 208, read the signal of first pixel A 11 to build up unit 206 from second.More particularly, the electric capacity of building up unit Cts2 by optical signalling is cut apart with the electric capacity between the electric capacity of the first horizontal output line 121, and the optical signalling of first pixel A 11 is read into the first horizontal output line 121 from optical signalling accumulation unit Cts2.Therefore, via the first horizontal output line 121 optical signalling of first pixel A 11 is sent to output unit 120.The electric capacity of building up unit Ctn2 by noise signal is cut apart with the electric capacity between the electric capacity of the second horizontal output line 122, and the noise signal of first pixel A 11 is read into the second horizontal output line 122 from noise signal accumulation unit Ctn2.Therefore, via the second horizontal output line 122 noise signal of first pixel A 11 is sent to output unit 120.Output unit 120 calculate the optical signalling that transmitted via the first horizontal output line 121 and the noise signal that transmitted via the second horizontal output line 122 between difference, and the differential wave between them outputed to following stages as picture signal.
Repeat operation described above.
Though it should be noted that the operation of except horizontal time-base HSR, having described reading circuit 110 about column signal line RL1, identical about the operation of the reading circuit 110 of all the other column signal line RL2 to RL4 with Fig. 3.In horizontal time-base HSR, after the effectual time of the signal HSR1 that is used for column signal line RL1, make that successively the signal HSR2 to HSR4 that is used for all the other column signal line RL2 to RL4 (Fig. 1) is effective.
To be sent to the second period BLKc that builds up unit 206 by the signal that the first accumulation unit 203 is kept and be shorter than the period BLKa that the signal of first pixel A 11 is read into the first accumulation unit 203.To be sent to the second period BLKc that builds up unit 206 by the signal that the first accumulation unit 203 is kept and be shorter than the period BLKb that the signal of second pixel B 11 is read into the first accumulation unit 203.This be because the area of reading circuit 110 less than the area (for example, having several millimeters areas) of pel array PA to the limit of tens millimeters long.That is to say that the required time of area of signal being transmitted reading circuit 110 is shorter than the required time of area of signal being transmitted pel array PA.
First electric capacity (electrode area) of building up unit 203 can be less than the electric capacity of the second accumulation unit 206.Reason is as follows.
Open among the No.2001-45378 in the disclosed technology the Japan Patent spy, be connected to that each two of building up in the unit in a plurality of column signal lines must have and another builds up the identical electric capacity (electrode area) in unit, thereby make the gain balance that is used to read, as mentioned above.When signal each from described two accumulation unit are read into the horizontal output line, determine to read gain according to the electric capacity splitting ratio between the electric capacity of the electric capacity of building up the unit and horizontal output line.Too low in order to prevent to read gain, described two accumulation unit boths must have big electric capacity (electrode area).As a result, chip area increases, and the chip production rate must reduce.
Yet, in this embodiment, between the first accumulation unit 203 and the second accumulation unit 206, providing delivery unit 204, it comprises optical signalling buffer amplifier AMS and noise signal buffer amplifier AMN.Delivery unit 204 supplies to the second accumulation unit 206 with the signal corresponding with the electric charge that is kept by the first accumulation unit 203, rather than will directly be supplied to the second accumulation unit 206 by the electric charge self that the first accumulation unit 203 is kept.Signal is read in the output unit 120 cutting apart by electric capacity, this electric capacity that prevents that first capacitive effect second of building up unit 203 from building up between the electric capacity of the electric capacity of unit 206 and the first horizontal output line 121 or the second horizontal output line 122 is cut apart.This be because even build up unit 203 and have when building up the littler electric capacity in unit 206 when first than second, signal is built up the executable operations that unit 203 reads into the second accumulation unit 206 from first does not also use electric capacity to cut apart.Therefore, might when improving gain and signal to noise ratio, at full speed read the high quality graphic data, and not increase chip area, and not reduce the chip production rate.That is to say,, even at full speed reading in the picture element signal, also might reduce deterioration in image quality, and reduce chip area according to this embodiment.
Open in the technology of No.11-150255 the Japan Patent spy, build up unit and two amplifiers for two and alternately be connected in a plurality of column signal lines each according to the mode corresponding with signal.The signal of being built up in described two of building up in the unit is built up in the unit at another then and is built up by an amplification in described two amplifiers.Build up the signal of being built up in the unit at another and amplify, and be read out the output line of following stages, as mentioned above by another amplifier.In the case, do not use electric capacity to cut apart from described two executable operations of building up the unit read output signal.Therefore, might be independent of two electric capacity of building up the unit and come read output signal, and not reduce gain.Yet because two amplifiers are connected in a plurality of column signal lines each, so the chip area of image sensing apparatus may increase.In addition, owing to two amplifiers are operated for reading a signal, therefore in image sensing apparatus, may increase in whole overall power of reading in the period.
Yet in this embodiment, for a signal, only amplifier is connected to each in a plurality of column signal lines.Therefore, can reduce the chip area of image sensing apparatus.In addition, only an amplifier is operated for reading a signal (that is, optical signalling or noise signal).Therefore, open the technology of No.11-150255 with the Japan Patent spy and compare, can suppress the power consumption in the image sensing apparatus.That is to say, might even also reduce chip area in the picture element signal and suppress power consumption to increase at full speed reading.
The buffer amplifier AMS of delivery unit 204 and AMN can be designed as and apply gain.Perhaps, can be that 1 buffer only is used to avoid any minimizing of building up the gain that unit 203 and electric capacity splitting ratio between the second accumulation unit 206 cause because of first simply with gain.Fig. 4 illustrates and serving as the example that gain is the buffer amplifier of 1 voltage follower.
Fig. 5 illustrates the example of the imaging system of using image sensing apparatus 100 of the present invention.
92 pairs of incident lights of lens reflect, and go up the formation object images in the image planes (pel array PA) of image sensing apparatus 100.
The object images that image sensing apparatus 100 will be formed on the image planes (pel array PA) is converted to picture signal.Image sensing apparatus 100 is read picture signal from pel array PA, and exports this picture signal.
Sensing signal treatment circuit 95 is connected to image sensing apparatus 100, to handle the picture signal of being exported from image sensing apparatus 100.
A/D converter 96 is connected to sensing signal treatment circuit 95, being converted to picture signal (digital signal) from the processed images signal (analog signal) that sensing signal treatment circuit 95 is exported.
Image signal processing unit 97 is connected to A/D converter 96, to carry out arithmetic processing (for example, being used for the various corrections of the picture signal (digital signal) exported from A/D converter 96), generates view data thus.View data is fed into memory cell 87, exterior I/F unit 89, overall situation control/arithmetical unit 99 and recording medium control I/F unit 94.
Exterior I/F unit 89 is connected to image signal processing unit 97, thereby is transferred to external equipment (for example personal computer) from the view data that image signal processing unit 97 is exported via exterior I/F unit 89.
Overall situation control/arithmetical unit 99 is connected to sequential generation unit 98, image signal processing unit 97 and recording medium is controlled I/F unit 94, with comprehensive control they.
Recording medium 88 is connected to recording medium control I/F unit 94 removably.Be recorded on the recording medium 88 via recording medium control I/F unit 94 from the view data of image signal processing unit 97 outputs.
By above-mentioned layout, when image sensing apparatus 100 can obtain good picture signal, can obtain good image (view data).
Next with reference to Fig. 6 and Fig. 7 image sensing apparatus 300 according to second embodiment of the invention is described.Fig. 6 is the view that illustrates according to the layout of the image sensing apparatus 300 of second embodiment of the invention.Fig. 7 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown.Below the part that is different from first embodiment will be described mainly, with the description of omitting for same section.
Except reading circuit 310, image sensing apparatus 300 has the basic layout identical with first embodiment.The difference of the reading circuit 310 and first embodiment is that it comprises delivery unit group 305.
As shown in Figure 7, the delivery unit 504 that is included in each row in the delivery unit group 305 comprises optical signalling source electrode follower SFs and noise signal source electrode follower SFn.Optical signalling source electrode follower SFs comprises nmos pass transistor MS and constant current source Is.Noise signal source electrode follower SFn comprises nmos pass transistor MN and constant current source In.
MOS transistor MS receives by first optical signalling of building up unit 203 via grid and builds up the signal that unit Cts1 is kept, and will the signal corresponding with the signal that is input to grid outputs to second optical signalling of building up unit 206 via source electrode and build up unit Cts2.
MOS transistor MN receives by first noise signal of building up unit 203 via grid and builds up the signal that unit Ctn1 is kept, and will the signal corresponding with the signal that is input to grid outputs to second noise signal of building up unit 206 via source electrode and build up unit Ctn2.
The delivery unit 504 that comprises optical signalling source electrode follower SFs and noise signal source electrode follower SFn can be by the raise input impedance and reduce output impedance of simple layout.Delivery unit 504 supplies to the second accumulation unit 206 with the signal corresponding with the electric charge that is kept by the first accumulation unit 203, rather than will directly supply to the second accumulation unit 206 by the electric charge self that the first accumulation unit 203 is kept, as among first embodiment.
Among the optical signalling source electrode follower SFs of delivery unit 504 and the noise signal source electrode follower SFn each can comprise that the PMOS transistor substitutes nmos pass transistor (MOS transistor MS or MN).
Next with reference to the image sensing apparatus 600 of Fig. 8 to Figure 11 description according to third embodiment of the invention.Fig. 8 is the view that illustrates according to the layout of the image sensing apparatus 600 of third embodiment of the invention.Fig. 9 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown.Figure 10 is the sequential chart that the operation of reading circuit is shown.Figure 11 is the view that is used to explain reset potential.Below the part that is different from first embodiment and second embodiment will be described mainly, with the description of omitting for same section.
Except reading circuit 610, image sensing apparatus 600 has the basic layout identical with second embodiment with first embodiment.Be that it is built up between unit group 107 and the 3rd cut-off/close unit group 108 second and comprises the first reset unit group 609 outside reading circuit 610 and first embodiment and second embodiment different.
Build up first reset unit 709 that each row that is included in the first reset unit group 609 are provided between unit 206 and the 3rd cut-off/close unit 220 second, as shown in Figure 9.First reset unit 709 comprises optical signalling reset transistor MRS and noise signal reset transistor MRN.The current potential V2 that optical signalling reset transistor MRS builds up unit Cts2 to optical signalling resets.The current potential V2 that noise signal reset transistor MRN builds up unit Ctn2 to noise signal resets.That is to say that 709 couples second current potential V2 that build up unit 206 of first reset unit reset.
If first reset unit 709 can reset to the second current potential V2 that builds up unit 206, then it can be provided at except second position of building up between unit 206 and the 3rd cut-off/close unit 220 Anywhere.
Be outside the operation of reading circuit and first embodiment and second embodiment different following some, as shown in figure 10.
During period BLKc (that is, first period), making the effective while of φ CTR, connect the optical signalling reset transistor MRS and the noise signal reset transistor MRN of first reset unit 709.At this moment, the second cut-off/close unit 205 is in " cut-out ".Therefore, 709 couples of second current potential V2 that build up unit 206 that are electrically connected from delivery unit 504 disconnections of first reset unit reset.More particularly, establishing V1 is the current potential of the first accumulation unit 203, and Vthn is the threshold voltage of nmos pass transistor MS and MN, and V2 is the current potential of the second accumulation unit 206.At this moment, 709 couples second current potential V2 that build up unit 206 of first reset unit reset, to satisfy following formula:
V2≤V1-Vthn ...(1)
Making the effective while of φ TSN2, connecting switch 231 and 232, so that the nmos pass transistor MS of optical signalling source electrode follower SFs and the nmos pass transistor MN of noise signal source electrode follower SFn are electrically connected to the second accumulation unit 206.At this moment, the nmos pass transistor MS current potential V2 that optical signalling built up unit Cts2 is elevated to and builds up the corresponding current potential of signal that unit Cts1 is kept by optical signalling from the current potential (formula (1)) that is resetted by first reset unit 709.The current potential V2 that nmos pass transistor MN builds up noise signal unit Ctn2 is elevated to and builds up the corresponding current potential of signal that unit Ctn1 is kept by noise signal from the current potential (formula (1)) that is resetted by first reset unit 709.That is to say that when being electrically connected to second when building up unit 206, nmos pass transistor MS and MN are elevated to the second current potential V2 that builds up unit 206 and the corresponding current potential of signal that is kept by the first accumulation unit 203 from the current potential that is resetted by first reset unit 709.
Explain that with reference to Figure 11 first reset unit 709 should reset to the second current potential V2 that builds up unit 206 reason by the represented current potential of formula (1).Consideration is connected to the formed circuit of capacitive load CL by the source follower SF that will comprise nmos pass transistor NM and constant current source Ic via switch SW.If Vg is a grid potential, Vd is a drain potential, and Vs is a source potential, and Vth is a threshold voltage, and Id is the drain current of nmos pass transistor NM.If Ib is the predetermined current value Ib that is supplied with from constant current source Ic, VCL is the current potential of capacitive load CL.
Make be used to connect the effective sequential Ton of signal psi TSN2 of switch SW before, operation changes according to the initial value of the current potential VCL of capacitive load CL.The current potential V2 that the current potential VCL of capacitive load CL and second builds up unit 206 is corresponding.The current potential V1 that current potential Vg and first builds up unit 203 is corresponding.Determine the current potential VCL of capacitive load CL by the difference between the drain current Id of the current value I b of constant current source Ic and nmos pass transistor NM.If before being used to connect the sequential Ton of switch SW,
VCL≤Vg-Vth ...(2)
Then at sequential Ton, connect the nmos pass transistor NM of source follower SF, thereby drain current Id flows between the drain electrode of nmos pass transistor and source electrode.If circuit operation shown in Figure 11 is in pentode (pentode), then
Id∝(Vg-Vth)
2 ...(3)
Therefore, nmos pass transistor NM is to the instantaneous charging of capacitive load CL, and rising current potential VCL.Nmos pass transistor NM with source potential Vs (=VCL) to change into almost be (Vg-Vth).After sequential Ton passes time Δ T1, electric current I d=Ib flows, and obtains stable state.
On the other hand, if before being used to connect the sequential Ton of switch SW,
VCL>Vg-Vth ...(4)
Then switch SW is in " cut-out " at sequential Ton.Therefore, drain current Id does not flow between drain electrode and source electrode.Constant current source Ic removes electric charge according to current value I b from capacitive load CL, and reduces the current potential VCL of capacitive load CL with the time per unit estimated rate.Constant current source Ic with the source potential Vs of nmos pass transistor NM (=VCL) to change into almost be (Vg-Vth).After sequential Ton passes time Δ T2, electric current I d=Ib flows, and obtains stable state.In the case, can shorten the time of the current potential VCL that is used to reduce capacitive load CL by the current value I b that increases constant current source Ic.Yet, because current value I b is always mobile, and the current drain increase, so the quality of image sensing apparatus is poor.In order to suppress current drain, the current value I b of constant current source Ic must be little.This has produced following trend:
ΔT1<ΔT2 ...(5)
As shown in figure 11.
Therefore, in this embodiment, build up unit 206 when delivery unit 504 disconnects electrical connection second, first reset unit 709 is reset to the second current potential V2 that builds up unit 206 by the represented current potential of formula (1).This has shortened period BLKc, and has reduced the current drain of image sensing apparatus 600.
As shown in figure 12, delivery unit 704a can comprise optical signalling source electrode follower SFsa and noise signal source electrode follower SFna.Optical signalling source electrode follower SFsa comprises PMOS transistor MSa and constant current source Isa.Noise signal source electrode follower SFna comprises PMOS transistor MNa and constant current source Ina.The first reset unit 709a resets to disconnect the second current potential V2 that builds up unit 206 that is electrically connected from delivery unit 704a.More particularly, establishing V1 is the current potential of the first accumulation unit 203, and Vthp is the transistorized threshold voltage of PMOS, and V2 is the current potential of the second accumulation unit 206.At this moment, the first reset unit 709a resets to the second current potential V2 that builds up unit 206, to satisfy following formula:
V2≥V1+Vthp ...(6)
When being electrically connected to second when building up unit 206, PMOS transistor MSa and MNa are reduced to the second current potential V2 that builds up unit 206 and the corresponding current potential of signal that is kept by the first accumulation unit 203 from the current potential that is resetted by the first reset unit 709a.
Next with reference to the image sensing apparatus 800 of Figure 13 to Figure 16 description according to fourth embodiment of the invention.Figure 13 is the view that illustrates according to the layout of the image sensing apparatus 800 of fourth embodiment of the invention.Figure 14 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown.Figure 15 is the sequential chart that the operation of reading circuit is shown.Below the part that is different from first embodiment to the, three embodiment will be mainly described, and description will be omitted for same section.
Except reading circuit 810, image sensing apparatus 800 has the identical basic layout with first embodiment to the, three embodiment.The difference of reading circuit 810 and first embodiment to the, three embodiment is that it comprises " the first cut-off/close unit group, first is built up unit group and delivery unit group " 803 and second cut-off/close unit group 806.
The first cut-off/close unit 1110, the first accumulation unit 1103 and the delivery unit 1104 that are included in each row in " the first cut-off/close unit group, first is built up unit group and delivery unit group " 803 have circuit arrangement shown in Figure 14.
More particularly, first build up counter-rotating input terminal and the lead-out terminal that unit 1103 is connected to delivery unit 1104.The second cut-off/close unit 1105 also is connected to the lead-out terminal of delivery unit 1104.The terminal that is used to supply with reference potential Vref is connected to the counter-rotating input terminal of delivery unit 1104.Arrange by this, delivery unit 1104 calculate reference signal Vref with based on the difference between the signal of signal that is fed back via the first accumulation unit 1103 from lead-out terminal and the signal that outputs to column signal line RL1, and export this differential wave.Therefore delivery unit 1104 will be sent to second by the signal that the first accumulation unit 1103 is kept via the second cut-off/close unit 1105 and build up unit 206.Delivery unit 1104 supplies to the second accumulation unit 206 with the signal corresponding with the electric charge that is kept by the first accumulation unit 1103.The lead-out terminal of the second cut-off/close unit, 1105 cut-off/close delivery units 1104 is built up being connected between the unit 206 (Cts2, Ctn2) with second.
With reference to Figure 14, short circuit or open circuit are carried out in the path between 1101 couples of column signal line RL1 in cut-off/close unit and the capacitor C 0.The feedback path of the 1102 pairs of delivery units 1104 in cut-off/close unit carries out short circuit or open circuit.
The layout of reading circuit 810 is commonly called the column amplifier system, and it can multiply by the gain corresponding with ratio C0/Cf.The first capacitor C f (Cf1, Cf2, Cf3) that builds up unit 1103 can change according to the open/close state (being in the quantity of " connection " state of switch) of the first cut-off/close unit 1110.Therefore, might gain be set according to application purpose.Figure 14 illustrates the example of having selected Cf1.
Be outside the operation of reading circuit 810 and first embodiment to the, three embodiment different following some, as shown in figure 15.
During period BLKa (that is, second period), make that signal psi VL is effective, will be input to C0 from the noise signal (VN) that first pixel A 11 is exported via column signal line RL1 and cut-off/close unit 1101.Making the effective while of signal psi PC0R, cut-off/close unit 1102 is being connected.First two terminals building up the capacitor C f (Cf1, Cf2, Cf3) of unit 1103 are reset to Vref, thus with the charge discharge that kept to power supply or GND, and acquisition reset mode.When making that signal psi PC0R is invalid, cut-off/close unit 1102 is cut off, will be input to C0 from the optical signalling (VS+VN) that first pixel A 11 is exported via column signal line RL1 and cut-off/close unit 1101.At this moment, by following formula:
Vout1＝(VS+VN-VN)＊Co/Cf+Vref+Voffset
...(7)
Represented signal appears at the lead-out terminal place of delivery unit 1104.That is to say, appear as Vout1 based on the output of Vref, it is by eliminating noise component(s) from the optical signalling of first pixel A 11 and resulting signal times being obtained with gain C0/Cf.Voffset is the migration noise of delivery unit 1104.Therefore, first builds up the signal that first pixel A 11 is built up in unit 1103, and this signal is provided by following formula:
Vcf＝Vout1-Vref
＝(VS+VN-VN)＊Co/Cf+Voffset?...(8)
During period BLKc (that is, first period), making the effective while of signal psi TS, will build up the optical signalling accumulation unit Cts2 that unit 1103 is sent to the second accumulation unit 206 from first by the represented signal Vout1 of formula (7) via switch 1231.Second optical signalling of building up unit 206 is built up unit Cts2 inhibit signal Vout1.Making that signal psi TS is invalid, and making the effective while of signal psi PC0R, building up unit 1103 to first and reset.By following formula
Vout2＝Voffset ...(9)
Represented signal appears at the lead-out terminal place of delivery unit 1104.After this, making that signal psi PC0R is invalid, and making the effective while of signal psi TN, will build up the noise signal accumulation unit Ctn2 that unit 1103 is sent to the second accumulation unit 206 from first by the represented signal Vout2 of formula (9) via switch 1232.Second noise signal of building up unit 206 is built up unit Ctn2 inhibit signal Vout2.
Before signal being write the second accumulation unit 206, first reset unit 709 can reset to second current potential of building up unit 206 temporarily.
During period BLKb (that is, second period) after the BLKc period (that is, first period), make that signal psi VL is effective, will be input to C0 from the noise signal (VN) that second pixel B 11 is exported via column signal line RL1 and cut-off/close unit 1101.Making the effective while of signal psi PC0R, cut-off/close unit 1102 is being connected.First two terminals building up the capacitor C f (Cf1, Cf2, Cf3) of unit 1103 are reset to Vref, thus with the charge discharge that kept to power supply or GND, and acquisition reset mode.When making that signal psi PC0R is invalid, cut-off/close unit 1102 is cut off, will be input to C0 from the optical signalling (VS+VN) that second pixel B 11 is exported via column signal line RL1 and cut-off/close unit 1101.At this moment, the signal identical with formula (7) appears at the lead-out terminal place of delivery unit 1104.That is to say, appear as Vout1 based on the output of Vref, it is by eliminating noise component(s) from the optical signalling of second pixel B 11 and resulting signal times being obtained with gain C0/Cf.Voffset is the skew of delivery unit 1104.Therefore, first build up the signal of the 1103 accumulations signal identical in unit as second pixel B 11 with formula (8).
During period BLKb (that is, second period), in the feasible effective while of signal HSR1 that is used for the column signal line RL1 of horizontal time-base HSR, switch 207 and 208 is in " connection ", reads the signal of first pixel A 11 to build up unit 206 from second.More particularly, the electric capacity of building up unit Cts2 by optical signalling is cut apart with the electric capacity between the electric capacity of the first horizontal output line 121, and the signal Vout1 of first pixel A 11 is read into the first horizontal output line 121 from optical signalling accumulation unit Cts2.Therefore, via the first horizontal output line 121 the signal Vout1 of first pixel A 11 is sent to output unit 120.The electric capacity of building up unit Ctn2 by noise signal is cut apart with the electric capacity between the electric capacity of the second horizontal output line 122, and the signal Vout2 of first pixel A 11 is read into the second horizontal output line 122 from noise signal accumulation unit Ctn2.Therefore, via the second horizontal output line 122 the signal Vout2 of first pixel A 11 is sent to output unit 120.Output unit 120 calculates
ΔV＝Vout1-Vout2
＝(VS+VN-VN)＊Co/Cf+Vref ...(10)
Difference between the signal Vout2 (formula (9)) that is transmitted as the signal Vout1 that is transmitted via the first horizontal output line 121 (formula (7)) and via the second horizontal output line 122, and this differential wave Δ V outputed to following stages as picture signal.This differential wave Δ V is the signal that obtains by the migration noise of eliminating delivery unit 1104.
More particularly, the delivery unit 1104 in the reading circuit 810 is carried out operation that transmits noise signal and the operation that transmits optical signalling in identical column amplifier.Therefore, delivery unit 1104 can be sent to the second accumulation unit 206 with noise signal and the optical signalling that comprises the same offset noise.The output unit 120 calculating noise signals of following stages and the difference between the optical signalling, the picture signal of the migration noise of column amplifier has been eliminated in acquisition thus.Delivery unit 1104 supplies to the second accumulation unit 206 with the signal corresponding with the electric charge that is kept by the first accumulation unit 1103, rather than will directly supply to the second accumulation unit 206 by the electric charge self that the first accumulation unit 1103 is kept, as among first embodiment.
Can use the output unit 1220 of both-end type, as shown in figure 16.
Image sensing apparatus 800 can only output to following stages with signal Vout1, and the switch 1232, the noise signal that are not provided in the reading circuit shown in Figure 14 810 are built up unit Ctn2, reset transistor MRN and switch 208.The signal processing unit of following stages (Fig. 5) can be eliminated the signal Vout2 of offset component of each row of delivery unit 1104.
For example, for each row, acquisition is called as the output of the pixel of OB pixel, and it is not subjected to rayed in image sensing apparatus 800.The OB pixel can make its photodiode conductively-closed.Perhaps, for each row, obtain dark signal.The signal of exporting from pixel is stored in memory cell 87 or the like as correction data as signal Vout2.In each the shooting, image signal processing unit 97 or the like is easily eliminated offset component thus from signal Vout1 subtraction signal Vout2.During assembling video camera or video camera, in each the shooting, to video camera or video camera power supply the time, perhaps, can preserve correction data according to the change of the behaviour in service of video camera or video camera.
When delivery unit 1104 transmits picture element signal during period BLKa or BLKb, that is to say that when waiting for period BLKc when keeping picture element signal in Cf when, certain noise may enter column signal line RL1.Can avoid this situation effectively by following operation: be provided with by the φ VL among the indicated Figure 15 of solid line, thereby cut-off/close unit 1101 disconnects provisionally in the end of period BLKa or BLKb, picture element signal is sampled and hold it among the Cf.
Next with reference to the image sensing apparatus 900 of Figure 17 to Figure 19 description according to fifth embodiment of the invention.Figure 17 is the view that illustrates according to the layout of the image sensing apparatus 900 of fifth embodiment of the invention.Figure 18 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown.Figure 19 is the sequential chart that the operation of reading circuit is shown.Below the part that is different from the 3rd embodiment will be described mainly, with the description of omitting for same section.
Except reading circuit 910, image sensing apparatus 900 has the basic layout identical with the 3rd embodiment.Be that it comprises delivery unit group 905, the second reset unit group 915 and the 4th cut-off/close unit group 911 outside reading circuit 610 and the 3rd embodiment different.Each a plurality of delivery units 1304 of being provided of row of pel array PA are provided delivery unit group 905.Each a plurality of second reset units 1315 of being provided of row of pel array PA are provided the second reset unit group 915.Each a plurality of the 4th cut-off/close unit 1310 of being provided of row of pel array PA are provided the 4th cut-off/close unit group 911.
In the 3rd embodiment, delivery unit 504 is sent to the second accumulation unit 206 via source follower SFs that separates and SFn with noise signal and optical signalling.Therefore, variation between source follower SFs and the SFn produces fixed pattern noise, and it makes deterioration in image quality.That is to say that the noise signal that is kept by the second accumulation unit 206 comprises different source follower skews with optical signalling.More particularly, because the threshold voltage of the nmos pass transistor MS of source follower SFs is different from the threshold voltage of the nmos pass transistor MN of source follower SFn, therefore can not eliminate migration noise by the difference between calculating noise signal and the optical signalling, and still have fixed pattern noise.Fixed pattern noise changes between each row, and therefore generates vertical banded noise based on the picture signal that is obtained in image.
Yet in the 5th embodiment, first noise signal builds up unit Ctn1 or first optical signalling is built up the input terminal that unit Cts1 is connected to delivery unit 1304 selectively.Second noise signal builds up unit Ctn2 or second optical signalling accumulation unit Cts2 is connected to lead-out terminal selectively.More particularly, first noise signal is built up unit Ctn1 and is connected to delivery unit 1304 via noise signal switch 1312, and first optical signalling accumulation unit Cts1 connects via optical signalling switch 1311.Second noise signal is built up unit Ctn2 and is connected to delivery unit 1304 via noise signal switch 232, and second optical signalling accumulation unit Cts2 connects via optical signalling switch 231.This allows delivery unit 1304 via public source follower SFsn noise signal or optical signalling to be sent to the second accumulation unit 206 selectively.Therefore, the noise signal that is kept by the second accumulation unit 206 can comprise identical fixed pattern noise with optical signalling.That is to say, can eliminate the fixed pattern noise that the variations in threshold voltage by the nmos pass transistor MSN of source follower SFsn generates by the difference between calculating noise signal and the optical signalling.
More particularly, reading circuit 910 is driven, as shown in figure 19.Notice that φ CRT is with shown in Figure 10 identical.
During period BLKc (that is, first period, seeing Figure 10), in the effective while of φ CTR, middle R is also effective.Reset transistor MRA is to the current potential of the grid of the nmos pass transistor MSN of source follower SFsn reset (for example, being reset to earth level).
In the effective while of φ TS2, φ TS3 is also effective.To be sent to second optical signalling by the optical signalling that first optical signalling accumulation unit Cts1 is kept via optical signalling switch 1311, delivery unit 1304 and optical signalling switch 231 and build up unit Cts2.
Then, make that once more φ R is effective.Reset transistor MRA is once more to the current potential of the grid of the nmos pass transistor MSN of source follower SFsn reset (for example, being reset to earth level).
In the effective while of φ TN2, φ TN3 is also effective.To be sent to second noise signal by the noise signal that first noise signal accumulation unit Ctn1 is kept via noise signal switch 1312, delivery unit 1304 and noise signal switch 232 and build up unit Ctn2.
Thereby make φ TN2 effectively before make φ R effectively make reset transistor MRA carry out the reason that resets once more once more with being described in.Building up optical signalling that unit Cts1 kept by first optical signalling changes according to the amount of incident light.Therefore, the signal (residue signal) that remains among the parasitic capacitance Cp1 of input terminal (input node NX1) of delivery unit 1304 also greatly changes according to light.During the effectual time of φ TN2, delivery unit 1304 is from lead-out terminal output and signal that is kept by first noise signal accumulation unit Ctn1 and the corresponding signal of residue signal with variation.If do not make once more that φ R is effective, then by the given linear deterioration of the amount of incident light.This may hinder and obtain satisfied signal.
If the effectual time of φ TN2 and φ TN3 is placed on before the effectual time of φ TS2 and φ TS3, as shown in figure 20, need not then to make that φ R is effective once more.Reason is as follows.
Building up noise signal that unit Ctn1 kept by first noise signal almost is to be independent of the amount of incident light and constant.Therefore, remain in that signal (that is residue signal) in the parasitic capacitance of input terminal of delivery unit 1304 also almost is independent of light and constant.During the effectual time of φ TS2, delivery unit 1304 from lead-out terminal output with the signal that is kept by first noise signal accumulation unit Ctn1 and almost be the constant corresponding signal of residue signal.Even without making φ R effective once more, by the given linearity of the amount of incident light also deterioration not, and gain only slightly reduces.The amount that gain reduces is corresponding to the ratio of the capacitance of first optical signalling accumulation unit Cts1 with the parasitic capacitance of the input terminal of delivery unit 1304.
The parasitic capacitance of delivery unit 1304 is tens fF for example.The electric capacity that first optical signalling is built up unit Cts1 is typically designed as several pF.In the case, the amount that reduces about the gain in driving method shown in Figure 19 is several percentage points, can not bring problem like this.Compare with the driving method of Figure 19, because do not make once more that φ R is effective, so the driving method of Figure 20 can shorten readout time.
Next with reference to the image sensing apparatus 1000 of Figure 21 to Figure 23 description according to sixth embodiment of the invention.Figure 21 is the view that illustrates according to the layout of the image sensing apparatus 1000 of sixth embodiment of the invention.Figure 22 is the circuit diagram that the circuit arrangement of the row of one in the reading circuit is shown.Figure 23 is the sequential chart that the operation of reading circuit is shown.Below the part that is different from the 5th embodiment will be described mainly, with the description of omitting for same section.
Except reading circuit 1010, image sensing apparatus 1000 has the basic layout identical with the 5th embodiment.The difference of reading circuit 1010 and the 5th embodiment is that it had not both had the first reset unit group 609, does not also have the second reset unit group 915, but comprises delivery unit group 1005.Delivery unit group 1005 is included as a plurality of delivery units 1404 that each row of pel array PA provide.
Buffer amplifier AMSN amplifies input signal and exports, and is similar to the source follower SFsn of the 5th embodiment.
In the 5th embodiment, reset transistor MRA (seeing Figure 18) is to the parasitic capacitance Cp1 of the input node NX1 of source follower SFsn reset (initialization).This has eliminated the residual charge from parasitic capacitance Cp1, and prevents by the given linear deterioration of the amount of incident light.
In the 6th embodiment, under the transistorized situation that the parasitic capacitance Cp2 that is not provided for the input node NX2 of buffer amplifier AMSN resets,, prevent degradation by the given linearity of the amount of incident light by following operation.
Be outside the operation of reading circuit 1010 and the 5th embodiment different following some, as shown in figure 23.
At sequential t1, make that φ TN1 is effective, so that being transferred to noise signal from column signal line RL1, noise signal builds up unit Ctn1.Simultaneously, make that φ TN2 is effective, with noise signal transmission to the input node NX2 of buffer amplifier AMSN, and the current potential of importing node NX2 is set to reset level Vn.That is to say that the initial potential Vn of input node NX2 equals the current potential that noise signal is built up unit Ctn1.Owing to use from the noise signal of pixel output to come input node NX2 is resetted, therefore might it be resetted being not used under the transistorized situation that parasitic capacitance Cp2 is resetted.
At sequential t2, make that φ TN2 is invalid, to disconnect the connection in path from column signal line RL1 to node NX2.Finish resetting of parasitic capacitance Cp2 thus.
At sequential t3, make that φ TN1 is invalid.Owing to cut off noise signal switch 202, so noise signal is built up unit Ctn1 maintenance noise signal.
At sequential t4, make that φ TS1 is effective.Connect switch 201, building up unit Cts1 to optical signalling via the optical signal transmission that column signal line RL1 is transmitted.
At sequential t5, make that φ TS1 is invalid.Cut off switch 201, and optical signalling is built up the optical signalling that Cts1 maintenance in unit is transmitted.If Vs is the signal voltage of this moment.Optical signalling is built up unit Cts1 and is preserved voltage (Vn+Vs).
At sequential t6, make that φ TN2 is effective, cut apart with the electric capacity between the capacitance of the capacitance of building up unit Ctni by noise signal and parasitic capacitance Cp2, will build up the noise signal that unit Ctn1 kept by noise signal and read into node NX2.At this moment, owing to build up the voltage that unit Ctn1 kept and the voltage both who is kept by parasitic capacitance Cp2 is Vn by noise signal, so the voltage of node NX2 does not change.That is to say that the noise signal that reads into node NX2 is:
Vxn＝Vn ...(11)
In addition, make that φ TN3 is effective, be sent to noise signal with the noise signal that will read into node NX2 via buffer amplifier AMSN and build up unit Ctn2.
At sequential t7, make that φ TN3 is invalid.Owing to cut off switch 232, so noise signal is built up the noise signal that Ctn2 maintenance in unit is transmitted.
At sequential t8, make that φ TN2 is invalid, to cut off switch 1312.
At sequential t9, make that φ TS2 is effective, cut apart and will build up the optical signalling that unit Cts1 kept by optical signalling and read into node NX2 with the electric capacity between the capacitance of the capacitance of building up unit Cts1 by optical signalling and parasitic capacitance Cp2.
If C1 is the capacitance that optical signalling is built up unit Cts1.Build up the electrode pair of reference side (ground connection side) electrode of unit Cts1 is built up by the represented electric charge of following formula in the face of optical signalling:
Q1＝C1＊(Vs+Vn) ...(12)
If Cp is the capacitance of parasitic capacitance Cp2.Node NX2 is to being built up by the represented electric charge of following formula:
Qp＝Cp＊Vn ...(13)
The optical signalling that reads into node NX2 is provided by following formula:
Vxs＝(Q1+Qp)/(C1+Cp)
＝{C1/(C1+Cp)}＊Vs+Vn ...(14)
In addition, make that φ TS3 is effective, be sent to optical signalling with the optical signalling that will read into node NX2 via buffer amplifier AMSN and build up unit Cts2.At sequential t10, make that φ TS3 is invalid.Owing to cut off switch 231, so optical signalling is built up the optical signalling that Cts2 maintenance in unit is transmitted.
At sequential t11, make that φ TS2 is invalid, to cut off switch 1311.
Then, output unit 120 (seeing Figure 21) calculate by the represented Vxn of formula (11) with by the difference between the represented Vxs of formula (14), with generation by the given picture signal of following formula:
ΔV＝Vxn-Vxs
＝{C1/(C1+Cp)}＊Vs ...(15)
Obtain from wherein having eliminated the picture signal Δ V of noise signal Vn, as indicated by formula (15).
As mentioned above, according to this embodiment, might be under the situation that second reset unit (reset transistor MRA) is not provided the parasitic capacitance of the input node of delivery unit be resetted.
This has prevented the deterioration by the given linearity of the amount of incident light.
In the 6th embodiment, NX2 resets to node, thereby noise signal is built up unit Ctn1 and node NX2 is equipotential.After this, the electric capacity between the capacitance of the capacitance of building up unit Ctn1 by noise signal and the parasitic capacitance Cp2 of node NX2 is cut apart and will be read into node NX2 by the noise signal that accumulation unit Ctn1 is kept.
Replace, can reset, thereby optical signalling is built up unit Cts1 and node NX2 is equipotential node NX2.After this, can build up that electric capacity between the capacitance of parasitic capacitance Cp2 of the capacitance of unit Cts1 and node NX2 is cut apart and will read into node NX2 by optical signalling by building up the optical signalling that unit Cts1 kept.
In the case, make that during period φ TS2 is effective, rather than during period, make φ TN2 effectively (seeing Figure 23), as shown in figure 24 from time t1 to t2 from time t4i to t12i.
At sequential t12i, make that φ TS2 is invalid.Optical signalling is built up each the preservation voltage (Vn+Vs) among unit Cts1 and the node NX2.Owing to use from the optical signalling of pixel output to come input node NX2 is resetted, therefore might parasitic capacitance Cp2 be resetted being not used under the transistorized situation that parasitic capacitance Cp2 is resetted.
At sequential t6, make that φ TN2 is effective, cut apart and will build up the noise signal that unit Ctn1 kept by noise signal and read into node NX2 with the electric capacity between the capacitance of the capacitance of building up unit Ctn1 by noise signal and parasitic capacitance Cp2.
If C2 is the capacitance that noise signal is built up unit Ctn1.The electrode pair of reference side (ground connection side) electrode of face of noise signal pcl product unit Ctn1 is built up by the represented electric charge of following formula:
Q2＝C2＊Vn ...(16)
If Cp is the capacitance of parasitic capacitance Cp2.Node NX2 is to being built up by the represented electric charge of following formula:
Qp＝Cp＊(Vs+Vn) ...(17)
The noise signal that reads into node NX2 is provided by following formula:
Vxn＝(Q2+Qp)/(C2+Cp)
＝{Cp/(C2+Cp)}＊Vs+Vn ...(18)
At sequential t9, make that φ TS2 is effective, cut apart and will build up the optical signalling that unit Cts1 kept by optical signalling and read into node NX2 with the electric capacity between the capacitance of the capacitance of building up unit Cts1 by optical signalling and parasitic capacitance Cp2.At this moment, the optical signalling that reads into node NX2 is provided by following formula:
Vxs＝Vs+Vn ...(19)
Then, output unit 120 (seeing Figure 21) calculate by the represented Vxn of formula (18) with by the difference between the represented Vxs of formula (19), with generation by the given picture signal of following formula:
ΔV＝Vxn-Vxs
＝{C2/(C2+Cp)}＊Vs ...(20)
Obtain from wherein having eliminated the picture signal Δ V of noise signal Vn, as indicated by formula (20).
As mentioned above, according to this modified example, might be under the situation that second reset unit (Figure 18 is described to be resetted to transistor MRA) is not provided the parasitic capacitance of the input node of delivery unit be resetted.This has prevented the deterioration by the given linearity of incident light quantity.
Though described the present invention, should be understood that to the invention is not restricted to disclosed exemplary embodiment with reference to exemplary embodiment.The scope of claims is consistent with the most wide in range explanation, thereby comprises modification and equivalent configurations and function that all are such.
Claims (14)
1. image sensing apparatus comprises:
Pixel, it comprises photoelectric conversion unit;
Column signal line, it is connected to described pixel;
Reading circuit, its via described column signal line from described pixel read output signal;
Output line, it is connected to described reading circuit; And
Output unit, it is according to from the signal of described reading circuit, via described output line output image signal,
Wherein, described reading circuit comprises:
First builds up the unit, and its maintenance reads into the signal of described column signal line,
The first cut-off/close unit, the described column signal line of its cut-off/close is built up being connected between the unit with described first,
Second builds up the unit,
Impedance transformer, it will be built up the signal that the unit kept by described first and be sent to the described second accumulation unit, and
The second cut-off/close unit, the described impedance transformer of its cut-off/close is built up being connected between the unit with described second,
Described first builds up the capacitance of the capacitance of unit less than the described second accumulation unit, and
Ratio based between the capacitance of described second capacitance of building up the unit and described output line is read out described output unit by the described second accumulation signal that the unit kept.
2. equipment as claimed in claim 1, wherein,
Described reading circuit further comprises: being connected between unit and the described output line built up in the 3rd cut-off/close unit, its cut-off/close described second,
Described the 3rd cut-off/close unit is built up described second and being connected between unit and the described output line is arranged on closure state, so that the described second accumulation unit is connected to described output line, and reads by the described second accumulation signal that the unit kept.
3. equipment as claimed in claim 1, wherein,
Described impedance transformer will with build up the corresponding signal of electric charge that the unit kept by described first and supply to described second and build up the unit.
4. equipment as claimed in claim 3, wherein,
Described impedance transformer comprises MOS transistor, and
Described MOS transistor receives by the described first accumulation signal that the unit kept via grid, and via source electrode the signal corresponding with the signal that is input to described grid is outputed to the described second accumulation unit.
5. equipment as claimed in claim 1, wherein,
Described reading circuit further comprises: reset unit, it resets to described second current potential of building up the unit.
6. equipment as claimed in claim 5, wherein,
Described impedance transformer comprises nmos pass transistor,
If V1 is the current potential of the described first accumulation unit, Vthn is the threshold voltage of described nmos pass transistor, and V2 is the current potential of the described second accumulation unit, and described reset unit resets to disconnect the described second current potential V2 that builds up the unit that is electrically connected from described impedance transformer, to satisfy:
V2≤V1-Vthn, and
When being electrically connected to described second when building up the unit, the current potential that described nmos pass transistor will described second be built up the unit is from being elevated to by the current potential that described reset unit resetted and by the described first accumulation corresponding current potential of signal that the unit kept.
7. equipment as claimed in claim 5, wherein,
Described impedance transformer comprises the PMOS transistor,
If V1 is the current potential of the described first accumulation unit, Vthp is the transistorized threshold voltage of described PMOS, and V2 is the current potential of the described second accumulation unit, and described reset unit resets to disconnect the described second current potential V2 that builds up the unit that is electrically connected from described impedance transformer, to satisfy:
V2 〉=V1-Vthp, and
When being electrically connected to described second when building up the unit, the current potential that described PMOS transistor will described second be built up the unit is from being reduced to by the current potential that described reset unit resetted and by the described first accumulation corresponding current potential of signal that the unit kept.
8. equipment as claimed in claim 1, wherein,
Described first builds up the unit comprises:
First noise signal is built up the unit, and its maintenance outputs to the noise signal of described column signal line, and
First optical signalling is built up the unit, and its maintenance outputs to the optical signalling of described column signal line,
Described second builds up the unit comprises:
Second noise signal is built up the unit, and build up the signal that the unit kept by described first noise signal and be transferred into this second noise signal accumulation unit, and
Second optical signalling is built up the unit, and build up the signal that the unit kept by described first optical signalling and be transferred into this second optical signalling accumulation unit,
Described impedance transformer has: input terminal, and it is connected to, and described first noise signal is built up the unit and described first optical signalling is built up the unit; And lead-out terminal, it is connected to, and described second noise signal is built up the unit and described second optical signalling is built up the unit, and
Described output unit is exported described picture signal by calculating by described second noise signal accumulation signal that the unit kept and by the difference that described second optical signalling is built up between the signal that the unit kept.
9. equipment as claimed in claim 1, wherein,
First pixel and second pixel are connected to described column signal line,
During first period, described impedance transformer is built up the unit with the signal of described first pixel from described first and is sent to the described second accumulation unit, and during second period after described first period, described first builds up the unit builds up the signal of described second pixel that is connected to described column signal line, and
During described second period, the signal of described first pixel is built up the unit from described second and is sent to described output unit.
10. equipment as claimed in claim 9, wherein,
Described first period is shorter than described second period.
11. an image sensing apparatus comprises:
First pixel;
Second pixel;
Column signal line, it is connected to described first pixel and described second pixel;
Reading circuit, its via described column signal line from described first pixel and the described second pixel read output signal;
Driver element, it drives described first pixel, described second pixel and described reading circuit;
Output line, it is connected to described reading circuit; And
Output unit, it is according to from the signal of described reading circuit, via described output line output image signal,
Wherein, described reading circuit comprises:
First builds up the unit, and its maintenance reads into the signal of described column signal line,
The first cut-off/close unit, the described column signal line of its cut-off/close is built up being connected between the unit with described first,
Second builds up the unit,
Impedance transformer, it will be built up the signal that the unit kept by described first and be sent to the described second accumulation unit, wherein said impedance transformer has input terminal and lead-out terminal, described first builds up the unit is connected between input terminal and the lead-out terminal, and lead-out terminal is connected to described second and builds up the unit, and
The second cut-off/close unit, its cut-off/close described first build up the unit and described impedance transformer is built up being connected between the unit with described second,
Described first builds up the capacitance of the capacitance of unit less than the described second accumulation unit,
Ratio based between the capacitance of described second capacitance of building up the unit and described output line is read out described output unit by the described second accumulation signal that the unit kept, and
Described first pixel of described drive unit drives, described second pixel and described reading circuit are during first period, build up the unit from described first and read the signal of described first pixel, and via described impedance transformer the described first described signal of building up the unit maintenance is sent to described second and builds up the unit, and during second period after described first period, make described first to build up the unit signal of described second pixel that outputs to described column signal line is built up, and build up the unit from described second and read the signal of described first pixel, and the described second described signal of building up the unit maintenance is sent to described output unit.
12. equipment as claimed in claim 11, wherein,
During second period, described impedance transformer amplify via described first build up the unit from the signal of described lead-out terminal feedback with the signal that outputs to described column signal line be difference between the based signal, with the generation differential wave.
13. an imaging system comprises:
The described image sensing apparatus of claim 1;
Optical system, it forms image on the image planes of described image sensing apparatus; And
Signal processing unit, it is handled from the signal of described image sensing apparatus output, to generate view data.
14. an imaging system comprises:
The described image sensing apparatus of claim 11;
Optical system, it forms image on the image planes of described image sensing apparatus; And
Signal processing unit, it is handled from the signal of described image sensing apparatus output, to generate view data.
Applications Claiming Priority (6)
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| JP2007240182 | 2007-09-14 | ||
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| JP2007-240182 | 2007-09-14 | ||
| JP2008217326A JP4673396B2 (en) | 2007-09-14 | 2008-08-26 | Imaging apparatus and imaging system |
| JP2008217326 | 2008-08-26 | ||
| JP2008-217326 | 2008-08-26 |
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| CN 201010291848 Division CN101945204B (en) | 2007-09-14 | 2008-09-12 | Image sensing device and image formation system |
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| CN101415064A CN101415064A (en) | 2009-04-22 |
| CN101415064B true CN101415064B (en) | 2010-11-17 |
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| CN 201010291848 Expired - Fee Related CN101945204B (en) | 2007-09-14 | 2008-09-12 | Image sensing device and image formation system |
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| FR2929055B1 (en) * | 2008-03-19 | 2010-05-28 | Commissariat Energie Atomique | SYSTEM FOR CONVERTING CHARGES IN VOLTAGE AND METHOD FOR CONTROLLING SUCH A SYSTEM |
| JP5161676B2 (en) * | 2008-07-07 | 2013-03-13 | キヤノン株式会社 | Imaging apparatus and imaging system |
| JP2012006257A (en) * | 2010-06-24 | 2012-01-12 | Canon Inc | Image processing apparatus and method |
| US8637800B2 (en) * | 2011-04-19 | 2014-01-28 | Altasens, Inc. | Image sensor with hybrid heterostructure |
| JP6223000B2 (en) | 2012-08-23 | 2017-11-01 | キヤノン株式会社 | Imaging device |
| JP2015142351A (en) | 2014-01-30 | 2015-08-03 | キヤノン株式会社 | Imaging apparatus and imaging system |
| JP6341688B2 (en) * | 2014-02-25 | 2018-06-13 | キヤノン株式会社 | Solid-state imaging device and imaging system |
| FR3091113B1 (en) * | 2018-12-21 | 2021-03-05 | Trixell | Matrix detector with controlled impedance line conductors |
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| JP3774499B2 (en) * | 1996-01-24 | 2006-05-17 | キヤノン株式会社 | Photoelectric conversion device |
| JPH10233964A (en) * | 1997-02-20 | 1998-09-02 | Nikon Corp | Solid-state image pickup device for forming binary signal |
| JP3667186B2 (en) * | 2000-02-29 | 2005-07-06 | キヤノン株式会社 | Signal transfer device and solid-state imaging device using the same |
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| JP4510523B2 (en) * | 2004-06-02 | 2010-07-28 | キヤノン株式会社 | Solid-state imaging device and imaging system |
| JP4290071B2 (en) * | 2004-06-02 | 2009-07-01 | キヤノン株式会社 | Solid-state imaging device and imaging system |
| JP2005354484A (en) * | 2004-06-11 | 2005-12-22 | Canon Inc | Amplification type memory device and solid state image pick-up device |
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- 2008-09-12 RU RU2008136807/09A patent/RU2390878C1/en not_active IP Right Cessation
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| US6377304B1 (en) * | 1998-02-05 | 2002-04-23 | Nikon Corporation | Solid-state image-pickup devices exhibiting faster video-frame processing rates, and associated methods |
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Also Published As
| Publication number | Publication date |
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| CN101415064A (en) | 2009-04-22 |
| RU2390878C1 (en) | 2010-05-27 |
| CN101945204B (en) | 2013-03-20 |
| CN101945204A (en) | 2011-01-12 |
| JP2009089367A (en) | 2009-04-23 |
| RU2008136807A (en) | 2010-03-20 |
| JP4673396B2 (en) | 2011-04-20 |
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