CN101729207A - Method and device for acquiring signaling - Google Patents
Method and device for acquiring signaling Download PDFInfo
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Abstract
The invention discloses a method and a device for acquiring a signaling. The method comprises the following steps of: firstly, performing code pattern conversion on signaling data of E1 links, and extracting synchronous clocks from the signaling data; then performing bit level convergence on the signaling data of each E1 link after the code pattern conversion according to the synchronous clocks; and finally acquiring the signaling data from the converged E1 link. The device comprises an E1 interface unit, a bit convergence unit and a signaling acquisition unit, wherein the E1 interface unit extracts the synchronous clock from an E1 line; and the bit convergence unit converges the signaling data in the E1 link step by step on the basis of beat of a bit clock when a frame clock arrives according to data channel information of a link provided by a telecom operator. Compared with the prior art that convergence processing granularity is only a time slot, the method and the device further improve effective utilization rate of the E1 link and reduce link resource waste when the signaling data with the data rate less than 64Kbit/s in the E1 link is processed.
Description
Technical field
The present invention relates to the telephonic communication technical field, relate in particular to a kind of signal collecting method and apparatus.
Background technology
Based on European E1 (Europe 1) standard in telephonic communication field, each Frame that transmits in the link comprises 32 time slots, and each time slot is 8 bits.In using usually, as a data passage, its data rate is 64Kbit/s or its integral multiple to the E1 link with one or several 8 bit (bit) time slots.But in some application scenario, in the Abis interface link, be to save bandwidth, sometimes only with certain the several bit in 8 bit time slots as a data channel.Such as with two bits as a data channel, its data rate is 16Kbit/s, if with four bits as a data channel, its data rate is 32Kbit/s.
In the E1 signaling monitoring system, obtain tested signaling data and carry out analyzing and processing, be called collection.Need the signaling data of acquisition process often to disperse very much in the tested link, gather path, the signaling data that disperses need be made its continuous arrangement by digital switching technology, be called convergence for saving.
Patent CN1925433 has introduced a kind of module to gathering behind the E1 signaling exchanging convergence, realizes other exchange of " time slot " level by the configuration to existing time gas exchange device, promptly exchanges and the granularity that restrains is 8 bit time slots.The defective of doing like this is, if with this module application in the occasion of data channel less than 8 bits, be in the E1 link data rate less than the signaling data of 64Kbit/s through after this module convergence, still have a large amount of unused bits, thereby cause the serious waste of resources of level acquisition process unit, back.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of signal collecting method and apparatus, the convergence of realization bit levels, the link circuit resource waste situation when minimizing is handled less than the signaling data of 64Kbit/s speed in the E1 link.
The technical solution used in the present invention is that described signal collecting method comprises:
Signaling data to the E1 link carries out yard type conversion and therefrom extracts synchronised clock;
According to synchronised clock the signaling data through the E1 link after the conversion of sign indicating number type is carried out the convergence of bit levels;
From the E1 link after the convergence, gather signaling data.
Described signaling data to the E1 link carries out the conversion of yard type and comprises: HDB3 (the High Density Bipolar of order 3 with the signaling data of E1 link during from input, three rank high density bipolars) sign indicating number or AMI (Alternative Mark Inversion, alternate mark inversion) sign indicating number converts NRZ (Non Return to Zero, non-return-to-zero) sign indicating number to.
The described synchronised clock that extracts from the signaling data of E1 link comprises:
Carry out frame head identification by signaling data frame, extract the frame clock each bar E1 link;
From the frame clock, optimize as frame clock according to link priority and Link State indication information with reference to signal;
To produce synchronised clock after phase-locked with reference to the frame clock of signal, synchronised clock comprises frame clock and bit clock.
Describedly signaling data through the E1 link after the sign indicating number type conversion is carried out the convergence of bit levels, comprises following detailed process according to synchronised clock:
Convert the serial signaling data of E1 link to the parallel signaling data;
Data channel information is set up related to the input position of described parallel signaling data with carry-out bit in the link that provides according to telecom operators;
Order according to carry-out bit becomes the output of serial signaling data with described parallel signaling data transaction.
Describedly signaling data through the E1 link after the sign indicating number type conversion is carried out the convergence of bit levels, comprises following detailed process according to synchronised clock:
Data channel information in the link that provides according to telecom operators restrains according to the signaling data step-by-step to every E1 link of the beat of bit clock when the frame clock arrives;
By time gas exchange the signaling data of all E1 links is restrained, improve the effective rate of utilization of E1 link.
Data channel information in the described link that provides according to telecom operators restrains according to the signaling data step-by-step to every E1 link of the beat of bit clock when the frame clock arrives, and comprising:
Deposit the signaling data step-by-step of E1 link in the twoport memory module;
Data channel information in the link that provides according to telecom operators from the section start of the Frame useful signaling data of step-by-step storage E1 link again, is read the signaling number of the E1 link of the storage of step-by-step again from the twoport memory module.
The described signaling data of gathering from the E1 link after the convergence comprises following process:
Data channel information receives signaling data in the data channel according to the beat of bit clock in step 1, the link that provides according to telecom operators;
Step 2, each signaling data that receives is carried out frame head sign identification, the HDLC frame signaling data that identifies is carried out buffer memory according to HDLC (High-Level Data Link Control, High-Level Data Link Control) agreement;
Step 3, the HDLC frame signaling data of buffer memory is carried out CRC (Cyclic Redundancy Check, cyclic redundancy check (CRC)), if errorless, then jump procedure four, otherwise abandon abnormal data;
Step 4, storage are used for further business diagnosis through the errorless HDLC frame signaling data of CRC check.
The present invention also provides a kind of signaling acquisition device, comprises following part:
The E1 interface unit is used for the signaling data of E1 link is carried out yard type conversion and therefrom extracts synchronised clock;
Bit convergence unit is used for according to synchronised clock the signaling data through each the bar E1 link after the conversion of sign indicating number type being carried out the convergence of bit levels;
The signal collecting unit, be used for from the convergence after the E1 link gather signaling data.
Described E1 interface unit comprises transformer module, E1 signaling processing module and clock selecting output module,
Described transformer module is used for noise isolation and input requires the input of E1 link is coupled according to the E1 signaling processing module;
Described E1 signaling processing module is used for carrying out frame head identification by the signaling data to the E1 link, extracts the frame clock and the signaling data of E1 link is carried out sending to bit convergence unit after yard type conversion;
Described clock selecting output module is used for selecting synchronised clock from the frame clock that the E1 signaling processing module is sent and feeds back to the E1 signaling processing module, and exports to bit convergence unit simultaneously.
Described clock selecting output module comprises clock preferred module and the phase-locked module of clock:
Described clock preferred module is used for the frame clock that link priority and Link State indication information send from the E1 signaling processing module and selects one road frame clock to be input to the phase-locked module of described clock as the reference signal;
The phase-locked module of described clock is used for producing frame clock and bit clock according to the phase-locked back of described reference signal, exports to E1 signaling processing module and bit convergence unit simultaneously.
Described E1 interface unit further comprises the lightning protection module, is used for the transient current that is input to described signaling acquisition device that thunderbolt produces is released fast.
Described bit convergence unit comprises:
String and modular converter are used for serial signaling data with the E1 link and convert the parallel signaling data to and send to access module;
Access module is used to store described parallel signaling data, and takes out the parallel signaling data and be sent to parallel serial conversion module under the control of connecting module;
Connecting module, the link data channel information that provides according to telecom operators is provided the input position of described parallel signaling data and carry-out bit is set up related, control access module beat according to bit clock when the frame clock arrives the parallel signaling data are outputed to parallel serial conversion module;
Parallel serial conversion module is used for becoming the serial signaling data to output to the signal collecting unit described parallel signaling data transaction.
Described bit convergence unit comprises:
Data are piled up the unit, and the link data channel information that provides according to telecom operators is provided, and restrain according to the signaling data step-by-step to every E1 link of the beat of bit clock when the frame clock arrives;
TSIU time slot interchange unit is used for by time gas exchange the signaling data of all E1 links being restrained, and improves the effective rate of utilization of E1 link.
Described data are piled up the unit and are comprised:
The data writing module is used for depositing the signaling data step-by-step of E1 link in the twoport memory module;
Data are read module, and the link data channel information that provides according to telecom operators is provided, and from the section start of the Frame useful signaling data of step-by-step storage E1 link again, read the signaling data of the E1 link of the storage of step-by-step again from the twoport memory module;
The twoport memory module is used to store that write and signaling data E1 link to be read.
Described signal collecting unit comprises
The step-by-step receiver module, the link data channel information that is used for providing according to telecom operators is according to the signaling data in the beat reception data channel of bit clock;
The identification cache module is used for according to the HDLC agreement each signaling data that receives being carried out the identification of frame head sign, and the HDLC frame signaling data that identifies is carried out buffer memory;
The CRC check module is used for the HDLC frame signaling data of buffer memory is carried out cyclic redundancy check (CRC), if errorless, then send to the useful data memory module, otherwise abandons abnormal data;
The useful data memory module is used to store through the errorless HDLC frame signaling data of CRC check, uses for further business diagnosis.
Adopt technique scheme, the present invention has following advantage at least:
Signal collecting method and apparatus of the present invention, this method is at first carried out yard type conversion and is therefrom extracted synchronised clock the signaling data of E1 link, according to synchronised clock the signaling data through each the bar E1 link after the conversion of sign indicating number type is carried out the convergence of bit levels then, from the E1 link after the convergence, gather signaling data at last.This device comprises E1 interface unit, bit convergence unit and signal collecting unit, the E1 interface unit extracts synchronised clock from the E1 circuit, data channel information in the link that bit convergence unit provides according to telecom operators, beat according to bit clock when the frame clock arrives is restrained the signaling data step-by-step in the E1 link, only compare with prior art convergence process granularity, further improved the effective rate of utilization of E1 link for time slot.Accordingly, data channel information has improved the efficient of signal collecting according to the signaling data in the beat image data passage of bit clock in the link that the signal collecting unit provides according to telecom operators again.The present invention is applicable to monitor the link circuit resource waste situation when minimizing is handled less than the signaling data of 64Kbit/s data rate in the E1 link as the signaling data of a data path less than 8 bit bit wides.
Description of drawings
Fig. 1 is a signal collecting method flow diagram described in the first embodiment of the invention;
Fig. 2 is a signal collecting method flow diagram described in the second embodiment of the invention;
Fig. 3 is the working state schematic representation of twoport memory block in the second embodiment of the invention;
Fig. 4 is the contrast schematic diagram before and after the convergence of in the second embodiment of the invention every E1 link being carried out self;
Fig. 5 is that signaling acquisition device described in the third embodiment of the invention is formed schematic diagram;
Fig. 6 is that the E1 interface unit is formed schematic diagram in the third embodiment of the invention;
Fig. 7 is that schematic diagram is formed in bit convergence unit in the third embodiment of the invention;
Fig. 8 is that schematic diagram is formed in the signal collecting unit in the third embodiment of the invention;
Fig. 9 is that schematic diagram is formed in bit convergence unit in the fourth embodiment of the invention;
Figure 10 forms schematic diagram for E1 interface unit among the present invention the 5th, six embodiment.
Embodiment
Reach technological means and the effect that predetermined purpose is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to the described signal collecting method and apparatus that the present invention proposes, describe in detail as after.
First embodiment of the invention, as shown in Figure 1, a kind of signal collecting method comprises following concrete steps:
Step S101 carries out a yard type conversion to the signaling data of E1 link, and is concrete, and HDB3 sign indicating number or AMI sign indicating number with the signaling data of E1 link during from input convert the NRZ sign indicating number to.
Step S102 extracts synchronised clock from the signaling data of E1 link, specifically comprise:
A, by the signaling data frame in each bar E1 link being carried out frame head identification, extract the frame clock.Owing to stipulate in the E1 standard: each Frame in the E1 link all can have the frame head sign, can extract the frame clock according to the frame head sign that identifies;
B, from the frame clock, optimize as frame clock with reference to signal according to link priority and Link State indication information, concrete, because can being every E1 chain in advance, the user sets priority, so select the highest E1 link of priority earlier, judge by the Link State indication information whether this E1 link has warning information again, if do not have, the frame clock of then selecting this E1 link is as the reference clock, otherwise select priority time high E1 link to carry out above-mentioned judgement selection course, and the like.
C, to as producing synchronised clock with reference to the phase-locked back of the frame clock of signal, synchronised clock comprises frame clock and bit clock.
Step S103 converts the serial signaling data of E1 link to the parallel signaling data according to the frame clock.
Step S104, data channel information is set up relatedly in the link that provides according to telecom operators to the input position of described parallel signaling data and carry-out bit, becomes the serial signaling data to export described parallel signaling data transaction according to bit clock according to the order of carry-out bit.The purpose of this step is to carry out the signaling data exchange of bit levels between link inside and each bar link, and " useful " data that need to gather are concentrated on the less link as far as possible, and giving up does not need " useless " of acquisition process data.
Step S105, data channel information receives signaling data in the data channel according to the beat of bit clock in the link that provides according to telecom operators;
Step S106 carries out the identification of frame head sign according to the HDLC agreement to each signaling data that receives, and the HDLC frame signaling data that identifies is carried out buffer memory.The HDLC agreement as frame head and postamble sign, is called FLAG with sign indicating number type 01111110.By identification, just can distinguish each HDLC Frame to FLAG.Detailed process is: constantly each data that receives judged, waited for FLAG, if find to have FLAG, so ensuing data that several possibilities are arranged:
1, ensuing data still are FLAG, at this moment just continue circular wait;
2, ensuing data are not FLAG, and are not illegal data, so just think that a HDLC frame begins, and the data that arrive in proper order of reception are put into buffer memory successively, arrive up to next FLAG, show the end of HDLC frame;
3, next invalid data is arranged,, show and made mistakes, at this moment still continue circular wait FLAG and arrive such as continuous 71.
Step S107 carries out CRC check to the HDLC frame signaling data of buffer memory, if errorless, and jump procedure S108 then, otherwise abandon abnormal data.
Step S108, storage is used for further business diagnosis through the errorless HDLC frame signaling data of CRC check.
Second embodiment of the invention, as shown in Figure 2, a kind of signal collecting method comprises following concrete steps:
Step S201 carries out a yard type conversion to the signaling data of E1 link, and is concrete, and HDB3 sign indicating number or AMI sign indicating number with the signaling data of E1 link during from input convert the NRZ sign indicating number to.
Step S202 extracts synchronised clock from the signaling data of E1 link, specifically comprise:
A1, by the signaling data frame in each bar E1 link being carried out frame head identification, extract the frame clock owing to stipulate in the E1 standard: each Frame in the E1 link all can have the frame head sign, can extract the frame clock according to the frame head sign that identifies;
A2, from the frame clock, optimize as frame clock with reference to signal according to link priority and Link State indication information, concrete, because can being every E1 chain in advance, the user sets priority, so select the highest E1 link of priority earlier, the channel status indication information judges whether this E1 link has warning information again, if do not have, the frame clock of then selecting this E1 link is as the reference clock, otherwise select priority time high E1 link to carry out above-mentioned judgement selection course, and the like.
A3, to as producing synchronised clock with reference to the phase-locked back of the frame clock of signal, synchronised clock comprises frame clock and bit clock.
Step S203, data channel information in the link that provides according to telecom operators, the beat according to bit clock when the frame clock arrives is restrained the signaling data step-by-step in every E1 link, specifically comprises:
B1, deposit the signaling data step-by-step in the E1 link in the twoport memory block;
Data channel information in b2, the link that provides according to telecom operators, the useful signaling data from the section start of Frame step-by-step storage E1 link is again read the signaling data in the E1 link of the storage of step-by-step again from the twoport memory block.
The operating state of twoport memory block as shown in Figure 3, data are being arranged team and are being come in from the left side, store frame data into first write area A1 earlier, writing the used time of each frame data is t1.The data of the first write area A1 are read district B1 and sent the time that needs from the section start of Frame step-by-step memory transfer to the first again is t2, t1=t2 is also coming in continuously because of the data of back, if have only district of the first write area A1, the data of back one frame have just been washed out the data of former frame so.So designed two memory blocks, the first write area A1 and the second write area A2, to read by the first write area A1 to the first in the operating time of district B1 carrying out, the data of coming in are put into the second write area A2.Switch so back and forth, just can realize clog-free operation.
Below with data channel that 4 bit bit wides are arranged in the time slot be example, as shown in Figure 4, the contrast schematic diagram before and after the convergence of self carrying out through pair of every E1 link of step 203, introduce the implementation procedure of convergence:
A has represented in some the E1 links that prime E1 interface unit sends here one among Fig. 4, shadow representation be 4 bit data segment in each time slot of gathering of expectation, promptly " useful " position, as can be seen " useful " position on whole E1 link, be dispersed arrangement.Also have the data segment of much representing with blank on the link, these data segments are not the objects that expectation is gathered, and promptly are " useless " positions.
Through after the execution in step 203, become the represented E1 link of B among Fig. 4." useful " position has been sequentially arranged in the leading portion of Frame, has promptly realized the convergence of " useful " data an E1 link inside.
Step S204 restrains the signaling data in all E1 links by time gas exchange, and the data between each bar link are exchanged with 8 bit granularities, and " useful " time slot is concentrated on the least possible link, improves the effective rate of utilization of E1 link.
Step S205, data channel information receives signaling data in the data channel according to the beat of bit clock in the link that provides according to telecom operators;
Step S206 carries out the identification of frame head sign according to the HDLC agreement to each signaling data that receives, and the HDLC frame signaling data that identifies is carried out buffer memory;
Step S207 carries out CRC check to the HDLC frame signaling data of buffer memory, if errorless, and redirect S208 then, otherwise abandon abnormal data;
Step S208, storage is used for further business diagnosis through the errorless HDLC frame signaling data of CRC check.
Third embodiment of the invention, as shown in Figure 5, a kind of signaling acquisition device comprises following part:
The E1 interface unit is used for the signaling data of E1 link is carried out yard type conversion and therefrom extracts synchronised clock.As shown in Figure 6, the E1 interface unit comprises transformer module, E1 signaling processing module and clock selecting output module:
Transformer module is used for noise isolation and input requires the input of E1 link is coupled according to the E1 signaling processing module, and this transformer module can adopt the T1180 model transformer of PULSE company to realize.
The E1 signaling processing module is used for carrying out the frame head identification extraction by the signaling data to the E1 link and goes out the frame clock, and the signaling data of E1 link is carried out sending to bit convergence unit after yard type conversion.Sign indicating number type conversion is meant the NRZ sign indicating number that HDB3 sign indicating number when signaling data with the E1 link is from input or AMI sign indicating number convert the bit convergence cell processing that is fit to the back to.Owing to stipulate in the E1 standard: each Frame in the E1 link all can have the frame head sign, can extract the frame clock according to the frame head sign that identifies.This module can be realized by existing mature technology, such as being realized by the PM4354 chip of PMC company;
The clock selecting output module, be used for selecting synchronised clock and export to bit convergence unit from the frame clock that the E1 signaling processing module is sent, and feeding back to the E1 signaling processing module simultaneously, the E1 signaling processing module carries out sending to bit convergence unit after yard type conversion according to the signaling data of this synchronised clock to the E1 link.The clock selecting output module comprises clock preferred module and the phase-locked module of clock:
The clock preferred module is used for the frame clock that link priority and Link State indication information send from the E1 signaling processing module and selects one road frame clock to be input to the phase-locked module of clock as the reference signal.Concrete, because can being every E1 chain in advance, the user sets priority, so select the highest E1 link of priority earlier, the Link State indication information that logical again E1 signaling processing module sends judges whether this E1 link has warning information, if do not have, the frame clock of then selecting this E1 link is as the reference clock, otherwise selection priority time high E1 link carries out above-mentioned judgement selection course, and the like.
The phase-locked module of clock, be used for producing frame clock and bit clock according to the phase-locked back of described reference signal, export to E1 signaling processing module and bit convergence unit simultaneously, become the synchronous working clock of whole system, the phase-locked module of this clock can be finished by existing integrated device MT9040.
Bit convergence unit is used for according to synchronised clock the signaling data through each the bar E1 link after the conversion of sign indicating number type being carried out the convergence of bit levels.As shown in Figure 7, bit convergence unit comprises string and modular converter, access module, connecting module and parallel serial conversion module:
String and modular converter are used for serial signaling data with the E1 link and convert the parallel signaling data to and send to access module;
Access module is used to store described parallel signaling data, and takes out the parallel signaling data and be sent to parallel serial conversion module under the control of connecting module;
Connecting module, the link data channel information that provides according to telecom operators is provided the input position of described parallel signaling data and carry-out bit is set up related, control access module beat according to bit clock when the frame clock arrives the parallel signaling data are outputed to parallel serial conversion module;
Parallel serial conversion module is used for becoming the serial signaling data to output to the signal collecting unit described parallel signaling data transaction.
Bit convergence unit is that each bar E1 link to be collected is received into, by string and modular converter, becomes parallel data and stores, and enters connecting module then.It is exactly swap table that connecting module is set up the input position foundation related with carry-out bit.Swap table, relation just continues, its content is corresponding with data channel information in the link that telecom operators provide, specific to the present invention, data channel information configuration swap table in the link that will provide according to telecom operators exactly, " useful " bit in each bar link of input is focused on output link get on, thereby reach the purpose that reduces link.Bit convergence unit is exactly to go to set up relation between the input and output according to swap table.This bit convergence unit can make up the required function of finishing with field programmable gate array FPGA.
The signal collecting unit, be used for from the convergence after the E1 link gather signaling data.As shown in Figure 8, the signal collecting unit comprises step-by-step receiver module, identification cache module, CRC check module and useful data memory module:
The step-by-step receiver module, the link data channel information that is used for providing according to telecom operators is according to the signaling data in the beat reception data channel of bit clock;
The identification cache module is used for according to the HDLC agreement each signaling data that receives being carried out the identification of frame head sign, and the HDLC frame signaling data that identifies is carried out buffer memory;
The CRC check module is used for the HDLC frame signaling data of buffer memory is carried out CRC check, if errorless, then send to the useful data memory module, otherwise abandons abnormal data;
The useful data memory module is used to store through the errorless HDLC frame signaling data of CRC check, uses for further business diagnosis.
According to the requirement difference to signaling process, signal collecting module can be made up by embedded processor system, also can cooperate server to finish.
Fourth embodiment of the invention, a kind of signaling acquisition device, roughly the same with device described in the 3rd embodiment, difference is that as shown in Figure 9, bit convergence unit comprises:
Data are piled up the unit, and the link data channel information that provides according to telecom operators is provided, and restrain according to the signaling data step-by-step to every E1 link of the beat of bit clock when the frame clock arrives.Data are piled up the unit and are comprised that data writing module, data read module and twoport memory module:
The data writing module is used for depositing the signaling data step-by-step of E1 link in the twoport memory module;
Data are read module, and the link data channel information that provides according to telecom operators is provided, and from the section start of the Frame useful signaling data of step-by-step storage E1 link again, read the signaling data of the E1 link of the storage of step-by-step again from the twoport memory module;
The twoport memory module is used to store that write and signaling data E1 link to be read.
TSIU time slot interchange unit is used for by time gas exchange the signaling data of all E1 links being restrained, and improves the effective rate of utilization of E1 link.TSIU time slot interchange unit can exchange the data between each bar link with 8 bit granularities, " useful " time slot is concentrated on the least possible link, outputs to the signal collecting unit.The time gas exchange subelement can such as the scale according to the exchange link, can be selected time gas exchange chips such as MT90826, IDT72V73273 by existing techniques in realizing.
Above-mentioned data are piled up the unit and can be realized by FPGA, finish the convergence of data in the link, realize further convergence between each bar link by TSIU time slot interchange unit afterwards.Below with data channel that 4 bit bit wides are arranged in the time slot be example, introduce the implementation procedure of convergence:
A has represented in some the E1 links that prime E1 interface unit sends here one among Fig. 4, shadow representation be 4 bit data segment in each time slot of gathering of expectation, promptly " useful " position, as can be seen " useful " position on whole E1 link, be dispersed arrangement.Also have the data segment of much representing with blank on the link, these data segments are not the objects that expectation is gathered, and promptly are " useless " positions.
After the process data are piled up cell processing, become the represented E1 link of B among Fig. 4." useful " position has been sequentially arranged in the leading portion of Frame, has promptly realized pile up the i.e. convergence of " useful " data an E1 link inside.
Fifth embodiment of the invention, a kind of signaling acquisition device, roughly the same with device described in the 3rd embodiment; difference is; as shown in figure 10, the E1 interface unit further comprises the lightning protection module, is used for the transient current that is input to described signaling acquisition device that thunderbolt produces is released fast.
Sixth embodiment of the invention, a kind of signaling acquisition device, roughly the same with device described in the 4th embodiment; difference is; as shown in figure 10, the E1 interface unit further comprises the lightning protection module, is used for the transient current that is input to described signaling acquisition device that thunderbolt produces is released fast.
By the explanation of embodiment, should be to reach technological means and the effect that predetermined purpose takes to be able to more deeply and concrete understanding to the present invention, yet appended diagram only provide with reference to the usefulness of explanation, be not to be used for the present invention is limited.
Claims (15)
1. a signal collecting method is characterized in that, comprising:
Signaling data to the E1 link carries out yard type conversion and therefrom extracts synchronised clock;
According to synchronised clock the signaling data through the E1 link after the conversion of sign indicating number type is carried out the convergence of bit levels;
From the E1 link after the convergence, gather signaling data.
2. according to the described signal collecting method of claim 1, it is characterized in that described signaling data to the E1 link carries out the conversion of yard type and comprises: High Density Bipolar 3 or alternate mark inversion code sign indicating number with the signaling data of E1 link during from input convert NRZ to.
3. according to the described signal collecting method of claim 1, it is characterized in that the described synchronised clock that extracts comprises from the signaling data of E1 link:
Carry out frame head identification by signaling data frame, extract the frame clock each bar E1 link;
From the frame clock, optimize as frame clock according to link priority and Link State indication information with reference to signal;
To produce synchronised clock after phase-locked with reference to the frame clock of signal, synchronised clock comprises frame clock and bit clock.
4. according to claim 2 or 3 described signal collecting methods, it is characterized in that, describedly signaling data through the E1 link after the sign indicating number type conversion carried out the convergence of bit levels, comprise following detailed process according to synchronised clock:
Convert the serial signaling data of E1 link to the parallel signaling data;
Data channel information is set up related to the input position of described parallel signaling data with carry-out bit in the link that provides according to telecom operators;
Order according to carry-out bit becomes the output of serial signaling data with described parallel signaling data transaction.
5. according to the described signal collecting method of claim 4, it is characterized in that, describedly signaling data through the E1 link after the sign indicating number type conversion carried out the convergence of bit levels, comprise following detailed process according to synchronised clock:
Data channel information in the link that provides according to telecom operators restrains according to the signaling data step-by-step to every E1 link of the beat of bit clock when the frame clock arrives;
By time gas exchange the signaling data of all E1 links is restrained, improve the effective rate of utilization of E1 link.
6. according to claim 1 or 2 or 3 or 5 described signal collecting methods, it is characterized in that, data channel information in the described link that provides according to telecom operators restrains according to the signaling data step-by-step to every E1 link of the beat of bit clock when the frame clock arrives, and comprising:
Deposit the signaling data step-by-step of E1 link in the twoport memory module;
Data channel information in the link that provides according to telecom operators from the section start of the Frame useful signaling data of step-by-step storage E1 link again, is read the signaling number of the E1 link of the storage of step-by-step again from the twoport memory module.
7. according to the described signal collecting method of claim 1, it is characterized in that the described signaling data of gathering comprises following process from the E1 link after the convergence:
Data channel information receives signaling data in the data channel according to the beat of bit clock in step 1, the link that provides according to telecom operators;
Step 2, each signaling data that receives is carried out frame head sign identification, the HDLC frame signaling data that identifies is carried out buffer memory according to the HDLC agreement;
Step 3, the HDLC frame signaling data of buffer memory is carried out cyclic redundancy check (CRC), if errorless, then jump procedure four, otherwise abandon abnormal data;
Step 4, storage are used for further business diagnosis through the errorless HDLC frame signaling data of cyclic redundancy check (CRC).
8. a signaling acquisition device is characterized in that, comprises following part:
The E1 interface unit is used for the signaling data of E1 link is carried out yard type conversion and therefrom extracts synchronised clock;
Bit convergence unit is used for according to synchronised clock the signaling data through each the bar E1 link after the conversion of sign indicating number type being carried out the convergence of bit levels;
The signal collecting unit, be used for from the convergence after the E1 link gather signaling data.
9. described according to Claim 8 signaling acquisition device is characterized in that described E1 interface unit comprises transformer module, E1 signaling processing module and clock selecting output module,
Described transformer module is used for noise isolation and input requires the input of E1 link is coupled according to the E1 signaling processing module;
Described E1 signaling processing module is used for carrying out frame head identification by the signaling data to the E1 link, extracts the frame clock and the signaling data of E1 link is carried out sending to bit convergence unit after yard type conversion;
Described clock selecting output module is used for selecting synchronised clock from the frame clock that the E1 signaling processing module is sent and feeds back to the E1 signaling processing module, and exports to bit convergence unit simultaneously.
10. described according to Claim 8 signaling acquisition device is characterized in that, described clock selecting output module comprises clock preferred module and the phase-locked module of clock:
Described clock preferred module is used for the frame clock that link priority and Link State indication information send from the E1 signaling processing module and selects one road frame clock to be input to the phase-locked module of described clock as the reference signal;
The phase-locked module of described clock is used for producing frame clock and bit clock according to the phase-locked back of described reference signal, exports to E1 signaling processing module and bit convergence unit simultaneously.
11. described according to Claim 8 signaling acquisition device is characterized in that, described E1 interface unit further comprises the lightning protection module, is used for the transient current that is input to described signaling acquisition device that thunderbolt produces is released fast.
12. described according to Claim 8 signaling acquisition device is characterized in that, described bit convergence unit comprises:
String and modular converter are used for serial signaling data with the E1 link and convert the parallel signaling data to and send to access module;
Access module is used to store described parallel signaling data, and takes out the parallel signaling data and be sent to parallel serial conversion module under the control of connecting module;
Connecting module, the link data channel information that provides according to telecom operators is provided the input position of described parallel signaling data and carry-out bit is set up related, control access module beat according to bit clock when the frame clock arrives the parallel signaling data are outputed to parallel serial conversion module;
Parallel serial conversion module is used for becoming the serial signaling data to output to the signal collecting unit described parallel signaling data transaction.
13. described according to Claim 8 signaling acquisition device is characterized in that, described bit convergence unit comprises:
Data are piled up the unit, and the link data channel information that provides according to telecom operators is provided, and restrain according to the signaling data step-by-step to every E1 link of the beat of bit clock when the frame clock arrives;
TSIU time slot interchange unit is used for by time gas exchange the signaling data of all E1 links being restrained, and improves the effective rate of utilization of E1 link.
14. described according to Claim 8 signaling acquisition device is characterized in that, described data are piled up the unit and are comprised:
The data writing module is used for depositing the signaling data step-by-step of E1 link in the twoport memory module;
Data are read module, and the link data channel information that provides according to telecom operators is provided, and from the section start of the Frame useful signaling data of step-by-step storage E1 link again, read the signaling data of the E1 link of the storage of step-by-step again from the twoport memory module;
The twoport memory module is used to store that write and signaling data E1 link to be read.
15. described according to Claim 8 signaling acquisition device is characterized in that, described signal collecting unit comprises
The step-by-step receiver module, the link data channel information that is used for providing according to telecom operators is according to the signaling data in the beat reception data channel of bit clock;
The identification cache module is used for according to High-Level Data Link Control HDLC agreement each signaling data that receives being carried out frame head identification, and the HDLC frame signaling data that identifies is carried out buffer memory;
The CRC check module is used for the HDLC frame signaling data of buffer memory is carried out cyclic redundancy check (CRC), if errorless, then send to the useful data memory module, otherwise abandons abnormal data;
The useful data memory module is used to store through the errorless HDLC frame signaling data of cyclic redundancy check (CRC), uses for further business diagnosis.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594514A (en) * | 2012-03-28 | 2012-07-18 | 广东宜通世纪科技股份有限公司 | Signaling link access and identification method |
| CN102970690A (en) * | 2012-10-08 | 2013-03-13 | 贺志鹏 | Method aligning terminal side internet protocol (IP) data with wireless signaling time |
| CN109784318A (en) * | 2019-03-13 | 2019-05-21 | 西北工业大学 | The recognition methods of Link16 data-link signal neural network based |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100444561C (en) * | 2005-08-29 | 2008-12-17 | 中兴通讯股份有限公司 | Signal collecting module with exchanging convergence function |
| CN101651846B (en) * | 2009-09-16 | 2011-12-07 | 中兴通讯股份有限公司 | Signaling acquisition device and method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594514A (en) * | 2012-03-28 | 2012-07-18 | 广东宜通世纪科技股份有限公司 | Signaling link access and identification method |
| CN102594514B (en) * | 2012-03-28 | 2014-12-10 | 广东宜通世纪科技股份有限公司 | Signaling link access and identification method |
| CN102970690A (en) * | 2012-10-08 | 2013-03-13 | 贺志鹏 | Method aligning terminal side internet protocol (IP) data with wireless signaling time |
| CN102970690B (en) * | 2012-10-08 | 2016-01-27 | 贺志鹏 | A kind of end side IP data and wireless signaling time unifying method |
| CN109784318A (en) * | 2019-03-13 | 2019-05-21 | 西北工业大学 | The recognition methods of Link16 data-link signal neural network based |
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