CN101728381A - Active component array substrate, liquid-crystal display panel and driving method thereof - Google Patents
Active component array substrate, liquid-crystal display panel and driving method thereof Download PDFInfo
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- CN101728381A CN101728381A CN200810201153A CN200810201153A CN101728381A CN 101728381 A CN101728381 A CN 101728381A CN 200810201153 A CN200810201153 A CN 200810201153A CN 200810201153 A CN200810201153 A CN 200810201153A CN 101728381 A CN101728381 A CN 101728381A
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Abstract
The invention relates to an active component array substrate which comprises a plurality of scanning lines, a plurality of data lines of the scanning lines and a plurality of pixel areas, wherein each pixel area comprises a plurality of pixel groups arranged along the directions of the data lines; each pixel group is provided with a plurality of pixels arranged adjacently along the directions of the data lines; the pixels in each pixel group are electrically connected to one data line; the scanning lines are configured at intervals among the pixels; and the data lines corresponding to each pixel area are adjacently configured at the same side of each pixel area.
Description
Technical field
The invention relates to a kind of substrate and display floater, and particularly relevant a kind of active assembly array substrate and display panels and driving method thereof with this active assembly array substrate.
Background technology
In recent years, because photoelectric technology and semiconductor fabrication maturing, drive the flourish of flat-panel screens (FlatPanel Display), LCD (Liquid Crystal Display wherein, LCD) because of having advantages such as low voltage operating, radiationless line scattering, in light weight and volume be little, replace traditional cathode-ray tube display gradually, and become the main flow of display product.
LCD mainly is made of display panels (Liquid Crystal Panel) and backlight module (BlackLight Module).After seeing through area source (using white light source usually) the process display panels that backlight module provided, can carry out the demonstration of GTG.
On the color representation as for LCD, usually in display panels, use in addition colour mixture of light that chromatic filter layer makes backlight module, reach color and present.For example, with Thin Film Transistor-LCD (Thin-Film Transistor Liquid Crystal Display, TFT-LCD) be example, the pairing chromatic filter layer of each pixel (Color Filter) normally is made of a plurality of colored look resistances (color photoresist), wherein colored look resistance for example comprises redness, green and blue look resistance, and the size of resistance of all kinds and arrangement pitches are all less than the cognizable size range of human eye, so the LCD that human eye is seen can present different color light (ruddiness, green glow and blue light) colour that mixes shows.Yet light will make the penetration of light descend, and then makes LCD produce the problem of luminance shortage through after the resistance of all kinds of chromatic filter layer.
In order to improve the shortcoming of LCD brightness deficiency, existing multiple prior art is suggested in succession, wherein a kind of method is to use light-emitting diode as the light source in the backlight module, this light-emitting diode can provide ruddiness, green glow and blue light to display panels respectively, utilize the penetrance of control different colours light, can mix the light of different colours, after the light of different colours passes through the control of the different GTGs of display panels again, can be so that LCD be done full-color demonstration, to reach the effect that brightness increases.
Specifically, above-mentioned LCD must be subdivided into the time of the full-color picture of original demonstration the time of the time of red display picture, green display frame and the time of blue display frame again.For example, (hertz, in the time of Hz), red display picture, green display frame and blue display frame three's frequency of operation is respectively 180 hertz when the display frequency of LCD is 60 hertz.In other words, when the picture frame time of LCD is that sixtieth (1/60) is during second, above-mentioned red subgraph frame time, green subgraph frame time and blue subgraph frame time are 1/180th (1/180) second, instantaneous switching redness like this, green and blue display frame, and then make the observer see complete image in the time at original picture frame.This kind utilizes observer's persistence of vision principle, sequential collocation is done in red display picture, green display frame and blue display frame and the method that obtains full-color demonstration be called space look preface method (Field Color Sequential Method, FCS).
Utilize above-mentioned space look preface method, can be so that LCD be omitted the making of chromatic filter layer, and then reach the effect that brightness promotes.Yet, this method is the original picture frame time with LCD to shorten to 1/3rd, in other words, original charging interval of each pixel reduces to original 1/3rd, make this kind LCD face the problem of pixel charging interval deficiency and pairing liquid crystal reaction time deficiency, cause the mistake of LCD to show that probability increases.
In order to solve the problem of above-mentioned LCD reaction time deficiency, existing multiple technologies are suggested in succession, wherein a kind of method is to use the special faster liquid crystal kind of reaction speed, for example optical compensation curved (optically compensated bend, OCB) type liquid crystal.Yet, select for use special liquid crystal can make that the cost of manufacture of LCD is higher.
In United States Patent (USP) case number US20070030233, the mode that proposes a kind of segmentation driving active assembly array substrate promotes the reaction speed of LCD.In detail, Fig. 1 is the United States Patent (USP) case active assembly array substrate schematic diagram that number US20070030233 is proposed.Please refer to Fig. 1, have multi-strip scanning line 10, many data wires 20, a plurality of pixel electrode 40 and the driving components 30 in order to control each pixel electrode 40 on the active assembly array substrate 100, wherein each pixel electrode 40 is connected with corresponding scanning line 10 and data wire electrical 20.In the segmentation type of drive of above-mentioned active assembly array substrate 100, must open multi-strip scanning line 10a, 10b, 10c simultaneously, and arrange in pairs or groups many data wire 20a, 20b, 20c import different pieces of information voltage simultaneously to different pixel electrodes 40.Mistake input for fear of data voltage, the designer usually must be with many data wire 20a, 20b, 20c layout in the zone of pixel electrode 40, that is to say, there are many data wire 20a, 20b, 20c to run through pixel electrode 40, make many data wire 20a, 20b, 20c be disposed at below with delegation's pixel electrode 40 with delegation.Yet this kind layout type will make pixel electrode and data wire produce coupling capacitance, cause LCD to produce problems such as cross-talk easily, influence the display quality of LCD.On the other hand, in pixel region, during many data wires of layout, also will face the problem that LCD aperture opening ratio (aperture ratio) descends.
Summary of the invention
The invention provides a kind of active assembly array substrate, it can promote the reaction time of each pixel.
The present invention provides a kind of display panels again, and it has higher brightness and than the advantage of high display quality.
The present invention proposes a kind of driving method in addition, and it is suitable for driving above-mentioned display panels, can promote the reaction time of display panels under the look preface method of space.
The present invention proposes a kind of active assembly array substrate, and this active assembly array substrate comprises multi-strip scanning line, many data wires vertical with scan line and a plurality of pixel region.Each pixel region comprises a plurality of pixel groups of arranging along the data wire direction, and each pixel groups has a plurality of pixels along the adjacent arrangement of data line direction, pixel in each pixel groups is electrically connected to same data wire, be configured between the pixel to scan line spacings, and each pixel region corresponding data lines is configured in the same side of each pixel region adjacent to each other.
In an embodiment of the present invention, the pixel groups in each pixel region comprises one first pixel groups, one second pixel groups and one the 3rd pixel groups, and second pixel groups is between first pixel groups and the 3rd pixel groups.In one embodiment, each pixel region corresponding data lines comprises one first data wire, one second data wire and one the 3rd data wire, and first data wire, second data wire and the 3rd data wire electrically connect with first pixel groups, second pixel groups and the 3rd pixel groups respectively.In another embodiment, first data line bit of each pixel region correspondence is between first pixel groups and second data wire, and second data line bit is between second pixel groups and the 3rd data wire.
In an embodiment of the present invention, each pixel groups corresponding data lines has a main traverse line and many source electrode connecting lines, data wire electrically connects by source electrode connecting line and pixel respectively, and wherein the length of main traverse line is along with main traverse line increases progressively to the increase of the beeline of the pixel of correspondence.In one embodiment, the pairing at least one data wire of each pixel region more comprises a lead and a bridging conductor, inferior lead be parallel to main traverse line and be disposed at main traverse line and corresponding pixel groups between, inferior lead is in parallel with main traverse line by bridging conductor, and wherein main traverse line, bridging conductor, inferior lead and source electrode connecting line are to arrange according to the direction of transfer of data wire signal.In another embodiment, inferior lead is positioned on the bearing of trend of adjacent data wire, and wherein time lead can be many conduction line segments parallel to each other, and bridging conductor can be many conduction line segments parallel to each other.
In an embodiment of the present invention, each pixel comprises a pixel electrode and a driving component, and driving component electrically connects pixel electrode, corresponding scanning line and corresponding data line.In one embodiment, pixel electrode and data wire do not overlap each other.In another embodiment, pixel comprises that also one shares electrode, constitutes storage capacitors between this shared electrode and each pixel electrode.
In an embodiment of the present invention, the pixel in each pixel region is along the alignment arrangement in fact each other of data wire direction.
The present invention proposes a kind of display panels in addition, and this display panels comprises active assembly array substrate, subtend substrate and liquid crystal layer.Active assembly array substrate comprises multi-strip scanning line, many and scan line vertical data line.In addition, each pixel region comprises first pixel groups, second pixel groups and the 3rd pixel groups.First pixel groups has a plurality of first pixels, and wherein first pixel is electrically connected to first data wire in corresponding scanning line and the data wire.Second pixel groups has a plurality of second pixels, and wherein second pixel is electrically connected to one second data wire in corresponding scanning line and the data wire.The 3rd pixel groups has a plurality of the 3rd pixels, and wherein the 3rd pixel is electrically connected to one the 3rd data wire in corresponding scanning line and the data wire.First pixel in each pixel region, second pixel and the 3rd pixel are arranged along the data line direction, and pairing first data wire of each pixel region, second data wire and the 3rd data wire are configured in the same side of each pixel region adjacent to each other, and each pixel region corresponding scanning beam compartment of terrain is configured between first pixel, between second pixel and between the 3rd pixel.Liquid crystal layer is between active assembly array substrate and subtend substrate.
In an embodiment of the present invention, display panels has first viewing area, second viewing area and the 3rd viewing area corresponding to the 3rd pixel groups corresponding to second pixel groups corresponding to first pixel groups, in first viewing area in pairing n row first pixel, second viewing area in pairing n row second pixel and the 3rd viewing area pairing n be listed as the conversion that the 3rd pixel is done brightness simultaneously, n 〉=1 wherein.
In an embodiment of the present invention, the length of each the 3rd data wire is greater than the length of each second data wire, and the length of each second data wire is greater than the length of each first data wire.
In an embodiment of the present invention, each second data wire comprises main traverse line, inferior lead, bridging conductor and many source electrode connecting lines.Inferior lead is positioned at the bearing of trend of first data wire, and inferior lead is in parallel with main traverse line by bridging conductor.The source electrode connecting line connects with corresponding second pixel respectively, and wherein main traverse line, bridging conductor, inferior lead and source electrode connecting line are to arrange according to the direction of transfer of the second data wire signal.
In an embodiment of the present invention, each the 3rd data wire comprises main traverse line, inferior lead, bridging conductor and many source electrode connecting lines.Inferior lead is positioned at the bearing of trend of first data wire and second data wire, and inferior lead is in parallel with main traverse line by bridging conductor.The source electrode connecting line connects with corresponding the 3rd pixel respectively, and wherein main traverse line, bridging conductor, inferior lead and source electrode connecting line are to arrange according to the direction of transfer of the 3rd data wire signal.
In an embodiment of the present invention, each first pixel, each second pixel and each the 3rd pixel comprise a driving component and a pixel electrode respectively.In one embodiment, pixel electrode and data wire do not overlap each other.In another embodiment, first pixel, second pixel and the 3rd pixel comprise that more one shares electrode, constitute storage capacitors between shared electrode and each pixel electrode.
The present invention proposes a kind of driving method in addition, be suitable for driving above-mentioned display panels, this driving method comprise the scan line of opening the first pixel groups correspondence in regular turn, in regular turn open the second pixel groups corresponding scanning beam, open the 3rd pixel groups corresponding scanning beam in regular turn, the method that wherein data signals is write each first pixel, each second pixel and each the 3rd pixel comprises the following steps.At first, open the pairing article one scan line of first pixel groups, second pixel groups and the 3rd pixel groups simultaneously, simultaneously one group of data signals is imported first row of first pixel groups, first row of second pixel groups and first row of the 3rd pixel groups by each first data wire, each second data wire and each the 3rd data wire respectively.Then, close the pairing article one scan line of first pixel groups, second pixel groups and the 3rd pixel groups simultaneously.Afterwards, open pairing next the bar scan line of first pixel groups, second pixel groups and the 3rd pixel groups simultaneously, simultaneously another group data signals is imported the next column of first pixel groups, the next column of second pixel groups and the next column of the 3rd pixel groups by each first data wire, each second data wire and each the 3rd data wire respectively.
Based on top described, the present invention utilizes the configuration of data wire and pixel, active assembly array substrate or display panels can be divided into three subregions of carrying out synchronously, can effectively promote each pixel assigned operate time whereby, therefore active assembly array substrate proposed by the invention or display panels can have higher display quality when promoting brightness.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the schematic diagram of existing a kind of active assembly array substrate;
Fig. 2 is the schematic diagram of a kind of active assembly array substrate of the present invention;
Fig. 3 is the schematic diagram of a kind of display panels of the present invention;
Fig. 4 is a kind of front elevational schematic of display panels when showing of Fig. 3.
Embodiment
Fig. 2 is the schematic diagram of a kind of active assembly array substrate of the present invention.Please refer to Fig. 2, active assembly array substrate 200 comprises multi-strip scanning line S, many data wires vertical with scan line S 220 and a plurality of pixel region U.Each pixel region U comprises a plurality of pixel groups 230 of arranging along data wire 220 directions, as shown in Figure 2, be to be that example explains with three groups of pixel groups 230, that is to say, pixel groups 230 among each pixel region U for example can be the first pixel groups 230A, the second pixel groups 230B and the 3rd pixel groups 230C, and wherein the second pixel groups 230B for example can be between the first pixel groups 230A and the 3rd pixel groups 230C.
In addition, each pixel groups 230 has a plurality of pixels 240 along the arrangement adjacent one another are of data wire 220 directions, and in the present embodiment, the pixel 240 in each pixel groups 230 is along the alignment arrangement in fact each other of data wire 220 directions.Detailed says, the first pixel groups 230A for example has a plurality of first pixel 240A, the second pixel groups 230B and for example has a plurality of second pixel 240B, and the 3rd pixel groups 230C for example has a plurality of the 3rd pixel 240C.In other words, as shown in Figure 2, in the same pixel region U of delegation of active assembly array substrate 200,, from top to bottom formed by second pixel 240B of the first pixel 240A of a plurality of adjacent arrangements, adjacent arrangement and the 3rd pixel 240C of adjacent arrangement in regular turn along the direction of data line 220.
Please continue with reference to Fig. 2, pixel 240 in each pixel groups 230 is electrically connected to same data wire 220, that is to say, each first pixel 240A is electrically connected to same first data wire 220A, each second pixel 240B is electrically connected to same second data wire 220B, and each the 3rd pixel 240C is electrically connected to same article the 3rd data wire 220C.Specifically, each pixel region U the first data wire 220A, the second data line 220B of correspondence and the same side that the 3rd data wire 220C is configured in pixel region U adjacent to each other.Certainly, the present invention does not limit the number that is disposed at the same side data wire.In addition, in the present embodiment, the first data wire 220A for example is between the first pixel groups 230A and the second data wire 220B, and the second data wire 220B is between the second pixel groups 230B and the 3rd data wire 220C.In addition, each scan line S then is configured between each pixel 240 compartment of terrain.
What deserves to be mentioned is that each data wire 220 has a main traverse line 222 and many source electrode connecting lines 224, comparatively clear in order to make illustrated sign, in Fig. 2 be with the second row pixel region U the data wire 220 of correspondence be the sign of masterpiece member.Each data wire 220 is by each source electrode connecting line 224 and each corresponding pixel 240 electric connection.And, the length of the main traverse line 222 of 230 respective data lines 220 of each pixel groups along with main traverse line 222 to the increase of the beeline of respective pixel and increase progressively.For example, in the present embodiment, the first data wire 220A, the main traverse line 222 of the second data line 220B and the 3rd data line 220C is respectively the first main traverse line 222A, the second main traverse line 222B and the 3rd main traverse line 222C, the first main traverse line 222A is D1 to the beeline between the first pixel 240A, the second main traverse line 222B is D2 to the beeline between the second pixel 240B, distance between the 3rd main traverse line 222C to the three pixel 240C is D3, as shown in Figure 2, because distance D 1＜D2＜D3, therefore, the length of the first main traverse line 222A is less than the length of the second main traverse line 222B, and the length of the second main traverse line 222B is less than the length of the 3rd main traverse line 222C.In other words, the pairing first data wire 220A of pixel region U, the second data line 220B are different with the length of the 3rd data wire 220C, can be so that the second data wire 220B and the 3rd data wire 220C need not use the layout designs of cross-line, can ingeniously the dodge layout of the first data wire 220A, and data signals directly is passed to the second pixel 240B and the 3rd pixel 240C by the source electrode connecting line 224 of correspondence, so the present invention can reduce the load of overall data line 220.
Moreover, in order further to reduce by the impedance of the second data line 220B and the 3rd data line 220C, as shown in Figure 2, the second data line 220B and the 3rd data wire 220C for example more comprise a lead 226 and a bridging conductor 228 respectively, with the second data wire 220B is that example explains, the inferior lead 226 of the second data line 220B is parallel to the second main traverse line 222B, and be disposed between the second pixel groups 230B of the second main traverse line 222B and correspondence, 226 in the inferior lead of the second data wire 220B is in parallel with the second main traverse line 222B by bridging conductor 228, in the present embodiment, inferior lead 226 for example is to be positioned on the bearing of trend of the first adjacent data wire 220A, and the second main traverse line 222B of the second data wire 220B, bridging conductor 228, inferior lead 226 and source electrode connecting line 224 are to arrange according to the direction of transfer of the signal of the second data wire 220B.In addition, inferior lead 226 can be the conduction line segment of wall scroll as the second data wire 220B, also can be made up of many conduction line segments parallel to each other as the 3rd data wire 220C, and the present invention does not limit the allocation position and the placement position of time lead 226.In addition, bridging conductor 228 for example is many conduction line segments parallel to each other, but not as limit.Each member of the 3rd data wire 220C and the second data wire 220B are similar, are not repeated.
In addition, each pixel 240 comprises a pixel electrode 242 and a driving component 246, and wherein driving component 246 electrically connects pixel electrode 242, corresponding scanning line S and corresponding data line 220.And in the present embodiment, each pixel 240 comprises that more one shares electrode 244, constitutes storage capacitors between this shared electrode 244 and each pixel electrode 242, to promote the display quality of pixel, in Fig. 2, the first pixel 240A that is listed as with second row first is that masterpiece indicates.Specifically, the present invention is different from prior art, is the same side that many data wires 220 is disposed at each pixel electrode 242.And, in the present embodiment, pixel electrode 242 does not overlap each other with data wire 220, therefore the present invention also can significantly reduce the coupling capacitance effect between data wire 220 and the pixel electrode 242, signal when effectively reducing 240 demonstrations of 220 pairs of pixels of data line disturbs, and promotes the display quality of pixel 240.
Fig. 3 is the schematic diagram of a kind of display panels of the present invention.Please refer to Fig. 3, this display panels 300 comprises arbitrary embodiment, subtend substrate 310 and the liquid crystal layer 320 as above-mentioned active assembly array substrate 200.The basic building block of active assembly array substrate 200 is not repeated as described in Figure 2.Liquid crystal layer 320 is between active assembly array substrate 200 and subtend substrate 310.
Fig. 4 is a kind of front elevational schematic of display panels when showing of Fig. 3, wherein the active assembly array substrate of display panels 300 for example is the active assembly array substrate 200 that Fig. 2 illustrated.Please be simultaneously with reference to Fig. 2 and Fig. 4, display panels 300 has the first viewing area 330A, the second viewing area 330B and the 3rd viewing area 330C corresponding to the 3rd pixel groups 230C corresponding to the second pixel groups 230B corresponding to the first pixel groups 230A.Specifically, the pairing n row first pixel 340A, the pairing n row second pixel 340B of the second viewing area 330B and the pairing n of the 3rd viewing area 330C are listed as the 3rd pixel 340C and synchronously make luminance transformation among the first viewing area 330A, wherein n 〉=1.As shown in Figure 4, first of the first viewing area 330A, the second viewing area 330B and the 3rd viewing area 330C row are synchronously being done the conversion of brightness.In other words, the present invention can be divided into the display frame of display panels 300 three sub-viewing areas, and these three sub-viewing areas can show simultaneously, make the assigned data signals of each pixel increase input time, to overcome the problem of available liquid crystal display reaction time deficiency.
Because display panels 300 can be divided into display frame three sub-viewing areas, and synchronously shows three sub-viewing areas, so can increase the time that each pixel data signal writes effectively.For example, as shown in Figure 4, give article one scan line S of cut-in voltage to the first a viewing area 330A correspondence simultaneously
A1, article one scan line S of the second viewing area 330B correspondence
BArticle one scan line S of the 1 and the 3rd viewing area 330C correspondence
C1, be listed as the 3rd pixel 340C with first of first row, the second pixel 340B of first row, the first pixel 340A, the second viewing area 330B that respectively will other data signals input to the first viewing area 330A and the 3rd viewing area 330C, make first of first row, the second pixel 340B of first row, the first pixel 340A, the second viewing area 330B of the first viewing area 330A among Fig. 4 and the 3rd viewing area 330C be listed as the 3rd pixel 340C and synchronously making luminance transformation.The type of drive that below will enumerate a kind of display panels 300 elaborates.
Please refer to Fig. 2 and Fig. 4, this driving method comprises opens the first pixel groups 230A corresponding scanning beam S in regular turn
A, open the second pixel groups 230B corresponding scanning beam S in regular turn
B, open the 3rd pixel groups 230C corresponding scanning beam S in regular turn
C, and scan line S
A, S
B, S
CBe to do synchronously to open, in more detail, the method that wherein data signals is write each first pixel 240A, each second pixel 240B and each the 3rd pixel 240C comprises the following steps.Open the first pixel groups 230A, the second pixel groups 230B and the pairing article one scan line of the 3rd pixel groups 230C S at first, simultaneously
A1, S
B1, S
C1, with simultaneously with one group of data signals respectively by first row of each first data wire 220A, each second data wire 220B and each first pixel groups 230A of each the 3rd data wire 220C input, first row of each second pixel groups 230B and first row of each the 3rd pixel groups 230C.
Then, please refer to Fig. 2, close the pairing first order scan line of first pixel groups 230A S simultaneously
A1, the pairing first order scan line of second pixel groups 230B S
BThe pairing article one scan line of the 1 and the 3rd pixel groups 230C S
C1.Afterwards, open pairing next the bar scan line S of the first pixel groups 230A, the second pixel groups 230B and the 3rd pixel groups 230C simultaneously, wherein next bar scan line S for example is the pairing second scan line of the first pixel groups 230A S among Fig. 2
A2, the pairing second scan line of second pixel groups 230B S
BThe pairing second scan line of the 2 and the 3rd pixel groups 230C S
C2.Then, simultaneously another group data signals is imported the secondary series of the first pixel groups 230A, the secondary series of the second pixel groups 230B and the secondary series of the 3rd pixel groups 230C by each first data wire 220A, each second data wire 220B and each the 3rd data wire 220C respectively.So, open three pixel groups corresponding scanning beam simultaneously, and open article one in each pixel groups 230 in regular turn to the last item scan line.
Please refer to Fig. 4, active assembly array substrate 200 of the present invention or display panels 300 utilize above-mentioned driving method, the display frame of display panels 300 can be divided into three sub-viewing areas, simultaneously three sub-viewing areas are shown respectively.In other words, in existing display panels, red subgraph frame time, green subgraph frame time and blue subgraph frame time are 1/180th second (1/180), that is to say, scan line on its active assembly array substrate must be unlocked in 1/180 second in regular turn, the number of scanning lines that makes this display panels is the N bar, and the assigned opening time of each scan line is 1/180N second in the then existing LCD.Active assembly array substrate 200 of the present invention or display panels 300, can be in the identical subgraph frame time, display frame is divided into for example three sub-viewing areas, these three viewing areas are to show simultaneously, that is to say, the assigned opening time of each scan line of the present invention is 1/60N second, so the present invention can effectively increase the assigned opening time of scan line, makes that the start time of each pixel is more abundant.Therefore, the present invention can give full play to the advantage of space look preface method, remedies the shortcoming of each pixel response deficiency of time, makes the display panels omitted chromatic filter layer, also can instantaneous switching sub-display frame of all kinds, do full-color demonstration in real time.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention should be with being as the criterion that claim was defined.
Claims (23)
1. an active assembly array substrate is characterized in that, comprising:
The multi-strip scanning line;
Many data wires are vertical with more described scan line; And
A plurality of pixel regions, each more described pixel region comprises a plurality of pixel groups of arranging along more described data wire direction, and each more described pixel groups has a plurality of pixels along the arrangement adjacent one another are of more described data wire direction, more described pixel in each described pixel groups is electrically connected to same data wire, be configured between the more described pixel to more described scan line spacings, and the pairing more described data wire of each more described pixel region is configured in the same side of each more described pixel region adjacent to each other.
2. active assembly array substrate as claimed in claim 1, it is characterized in that, more described pixel groups in each described pixel region comprises one first pixel groups, one second pixel groups and one the 3rd pixel groups, and described second pixel groups is between described first pixel groups and described the 3rd pixel groups.
3. active assembly array substrate as claimed in claim 2, it is characterized in that, the pairing more described data wire of each described pixel region comprises one first data wire, one second data wire and one the 3rd data wire, and described first data wire, described second data wire and described the 3rd data wire electrically connect with described first pixel groups, described second pixel groups and described the 3rd pixel groups respectively.
4. active assembly array substrate as claimed in claim 3, it is characterized in that, pairing described first data line bit of each described pixel region is between described first pixel groups and described second data wire, and described second data line bit is between described second pixel groups and described the 3rd data wire.
5. active assembly array substrate as claimed in claim 1, it is characterized in that, the pairing described data wire of each described pixel groups has a main traverse line and many source electrode connecting lines, and described data wire electrically connects by more described source electrode connecting line and more described pixel respectively.
6. active assembly array substrate as claimed in claim 5 is characterized in that, the length of more described main traverse line is along with more described main traverse line increases progressively to the increase of the beeline of corresponding more described pixel.
7. active assembly array substrate as claimed in claim 5, it is characterized in that, have at least one more to comprise a lead and a bridging conductor in the pairing more described data wire of each described pixel region, described lead be parallel to described main traverse line and be disposed at described main traverse line and corresponding described pixel groups between, described time lead is in parallel with described main traverse line by described bridging conductor.
8. active assembly array substrate as claimed in claim 7 is characterized in that, described main traverse line, described bridging conductor, described lead and described source electrode connecting line are to arrange according to the direction of transfer of described data wire signal.
9. active assembly array substrate as claimed in claim 7 is characterized in that, described time lead is positioned on the bearing of trend of those adjacent data wires.
10. active assembly array substrate as claimed in claim 7 is characterized in that, described time lead comprises many conduction line segments parallel to each other.
11. active assembly array substrate as claimed in claim 7 is characterized in that, described bridging conductor comprises many conduction line segments parallel to each other.
12. active assembly array substrate as claimed in claim 1 is characterized in that, each described pixel comprises a pixel electrode and a driving component, and described driving component electrically connects described pixel electrode, corresponding scanning line and corresponding data line.
13. active assembly array substrate as claimed in claim 12 is characterized in that, more described pixel electrode and more described data wire do not overlap each other.
14. active assembly array substrate as claimed in claim 12 is characterized in that, more described pixel comprises that also one shares electrode, constitutes storage capacitors between described shared electrode and each the described pixel electrode.
15. active assembly array substrate as claimed in claim 1 is characterized in that, the more described pixel in each described pixel region is along the alignment arrangement in fact each other of more described data wire direction.
16. a display panels is characterized in that, comprising:
One active assembly array substrate, it comprises:
The multi-strip scanning line;
Many data wires are vertical with more described scan line;
A plurality of pixel regions, each described pixel region comprises:
One first pixel groups has a plurality of first pixels, and more described first pixel is electrically connected to corresponding more described scan line and one first data wire in the more described data wire;
One second pixel groups has a plurality of second pixels, and more described second pixel is electrically connected to corresponding more described scan line and one second data wire in the more described data wire;
One the 3rd pixel groups has a plurality of the 3rd pixels, and more described the 3rd pixel is electrically connected to corresponding more described scan line and one the 3rd data wire in the more described data wire;
Wherein, more described first pixel in each described pixel region, more described second pixel and more described the 3rd pixel are arranged along more described data line direction, pairing described first data wire of each described pixel region, described second data wire and described the 3rd data wire are configured in the same side of each described pixel region adjacent to each other, are configured between more described first pixel to the pairing more described scan line spacings of each described pixel region, between more described second pixel and between more described the 3rd pixel;
One subtend substrate; And
One liquid crystal layer, between this active assembly array substrate and this subtend substrate, corresponding one first viewing area of more wherein said first pixel groups, corresponding one second viewing area of more described second pixel groups and corresponding one the 3rd viewing area of more described the 3rd pixel groups, pairing n is listed as in more described first pixel, described second viewing area pairing n and is listed as that pairing n is listed as the conversion that more described the 3rd pixel is done brightness simultaneously in more described second pixel and described the 3rd viewing area in described first viewing area, wherein n 〉=1.
17. display panels as claimed in claim 16 is characterized in that, the length of each described the 3rd data line is greater than the length of each described second data wire, and the length of each described second data wire is greater than the length of each described first data wire.
18. display panels as claimed in claim 16 is characterized in that, each described second data line comprises:
One main traverse line;
A lead is positioned at the bearing of trend of described first data wire;
One bridging conductor, described time lead is in parallel with described main traverse line by described bridging conductor; And
Many source electrode connecting lines, more described source electrode connecting line connect with corresponding second pixel respectively,
Wherein said main traverse line, described bridging conductor, described lead and described source electrode connecting line are to arrange according to the direction of transfer of the described second data wire signal.
19. display panels as claimed in claim 16 is characterized in that, each described the 3rd data line comprises:
One main traverse line;
A lead is positioned at the bearing of trend of described first data wire and described second data wire;
One bridging conductor, described time lead is in parallel with described main traverse line by described bridging conductor; And
Many source electrode connecting lines, more described source electrode connecting line connect with corresponding the 3rd pixel respectively,
Wherein said main traverse line, described bridging conductor, described lead and more described source electrode connecting line are to arrange according to the direction of transfer of described the 3rd data wire signal.
20. display panels as claimed in claim 16 is characterized in that, each more described first pixel, each more described second pixel and each more described the 3rd pixel comprise a driving component and a pixel electrode respectively.
21. display panels as claimed in claim 20 is characterized in that, more described pixel electrode and more described data wire do not overlap each other.
22. display panels as claimed in claim 20 is characterized in that, more described first pixel, more described second pixel and more described the 3rd pixel comprise that more one shares electrode, constitute storage capacitors between described shared electrode and each the described pixel electrode.
23. a driving method is suitable for driving display panels as claimed in claim 16, it is characterized in that, this driving method comprises:
Open in regular turn the more described first pixel groups corresponding scanning beam, in regular turn open the more described second pixel groups corresponding scanning beam, open more described the 3rd pixel groups corresponding scanning beam in regular turn, the method that wherein data signals is write each first pixel, each second pixel and each the 3rd pixel comprises:
Open more described first pixel groups, more described second pixel groups and the pairing article one scan line of more described the 3rd pixel groups simultaneously, simultaneously one group of data signals is imported first row of first row of more described first pixel groups, more described second pixel groups and first row of more described the 3rd pixel groups by more described first data wire, more described second data wire and more described the 3rd data wire respectively;
Close more described first pixel groups, more described second pixel groups and the pairing article one scan line of more described the 3rd pixel groups simultaneously;
Open pairing next the bar scan line of more described first pixel groups, more described second pixel groups and more described the 3rd pixel groups simultaneously, simultaneously another group data signals is imported the next column of the next column of more described first pixel groups, more described second pixel groups and the next column of more described the 3rd pixel groups by more described first data wire, more described second data wire and more described the 3rd data wire respectively.
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| CN2008102011537A CN101728381B (en) | 2008-10-14 | 2008-10-14 | Active component array substrate, liquid-crystal display panel and driving method thereof |
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| CN2008102011537A CN101728381B (en) | 2008-10-14 | 2008-10-14 | Active component array substrate, liquid-crystal display panel and driving method thereof |
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| CN101728381B CN101728381B (en) | 2012-05-30 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111430419A (en) * | 2020-04-01 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Horizontal pixel structure, hybrid arrangement panel and manufacturing method |
| CN112243097A (en) * | 2019-07-18 | 2021-01-19 | 京鹰科技股份有限公司 | Image sensing device and image sensing method |
| CN113325644A (en) * | 2021-05-31 | 2021-08-31 | Tcl华星光电技术有限公司 | Display panel and electronic device |
| CN113838865A (en) * | 2020-08-21 | 2021-12-24 | 友达光电股份有限公司 | Pixel array substrate |
-
2008
- 2008-10-14 CN CN2008102011537A patent/CN101728381B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112243097A (en) * | 2019-07-18 | 2021-01-19 | 京鹰科技股份有限公司 | Image sensing device and image sensing method |
| CN112243097B (en) * | 2019-07-18 | 2023-07-11 | 京鹰科技股份有限公司 | Image sensing device and image sensing method |
| CN111430419A (en) * | 2020-04-01 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Horizontal pixel structure, hybrid arrangement panel and manufacturing method |
| CN113838865A (en) * | 2020-08-21 | 2021-12-24 | 友达光电股份有限公司 | Pixel array substrate |
| CN113838865B (en) * | 2020-08-21 | 2023-04-28 | 友达光电股份有限公司 | Pixel array substrate |
| CN113325644A (en) * | 2021-05-31 | 2021-08-31 | Tcl华星光电技术有限公司 | Display panel and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101728381B (en) | 2012-05-30 |
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