CN101724843A - Plasma precleaning method - Google Patents
Plasma precleaning method Download PDFInfo
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- CN101724843A CN101724843A CN200810224584A CN200810224584A CN101724843A CN 101724843 A CN101724843 A CN 101724843A CN 200810224584 A CN200810224584 A CN 200810224584A CN 200810224584 A CN200810224584 A CN 200810224584A CN 101724843 A CN101724843 A CN 101724843A
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Abstract
The invention relates to a plasma precleaning method which comprises the following steps of: carrying out a degassing operation on a substrate, wherein the temperature of the substrate subjected to the degassing operation is T1; and carrying out a plasma etching operation on the substrate subjected to the degassing operation, wherein the temperature of a reaction cavity carrying out the plasma etching operation is T2, and the plasma etching operation comprises the following steps of: carrying out a cooling operation on the substrate subjected to the degassing operation; and carrying out the plasma etching operation on the substrate subjected to the cooling operation. The method can reduce gate oxide damages.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of plasma precleaning method.
Background technology
Plasma body is a kind of neutrality, high-energy and Ionized gas, in a process cavity, utilizes tetanic stream or ac magnetic field or all can cause the ionization of gas atom with some electron source bombarding gas atom.Current, in the manufacture of semiconductor,, and be widely used in each step that unicircuit is made because plasma body can provide the gas reaction that occurs in silicon chip surface required most of energy.For example, in high-density plasma chemical vapor deposition (HDPCVD) or physical vapor deposition (PVD), in the heat energy field with plasma ionization and excite a gas source to come deposition film; In addition, the Another application of plasma body is optionally to remove the part of metal or thin-film material by plasma etching.
Current, before carrying out deposition or etching reaction, need the plasma body pre-cleaning operation is carried out in substrate usually, as shown in Figure 1, the concrete steps of carrying out described plasma body pre-cleaning operation comprise step 11: degas operation is carried out in substrate, and the temperature that experiences the substrate of described degas operation is T
1Step 12: the plasma etching operation is carried out in the substrate of experiencing described degas operation, and the temperature of carrying out the reaction chamber of described plasma etching operation is T
2, T
2Less than T
1
Yet, in the actual production, often there is a certain amount of gate oxide damage in the device that forms through the plasma body pre-cleaning operation, described gate oxide damage will influence the performance of described device, and and then influence production capacity.How to reduce described gate oxide damage and become the subject matter that those skilled in the art endeavour to solve.
The notification number of announcing on October 18th, 2006 may further comprise the steps for a kind of etching technics that can prevent device plasma damage in the etching polysilicon is provided in the Chinese patent application of " CN1848387A ": run through etching, main etching, the release of accumulation electric charge and over etching.Wherein assemble in the electric charge release steps by adjusting conduction process gas N
2With carrier gas He ratio and flow, and the radio frequency power of adjusting process and reaction pressure, can effectively eliminate the non-equilibrium electric charge accumulation that high electronegativity reactant gases causes in the etching process, reach the effect of avoiding gate oxide breakdown.
Yet, when using aforesaid method and reducing described gate oxide damage, need to introduce gathering electric charge release steps, though aforesaid method all has good adaptability to different shape, types of devices, but, in that aforesaid method and traditional technology are carried out in the process of processing procedure integration, need carry out a large amount of debugging to described gathering electric charge release steps, R﹠D costs are huge.
Summary of the invention
The invention provides a kind of plasma precleaning method, can reduce the gate oxide damage.
A kind of plasma precleaning method provided by the invention comprises,
Degas operation is carried out in substrate, and the temperature that experiences the substrate of described degas operation is T
1
The plasma etching operation is carried out in the substrate of experiencing described degas operation, and the temperature of carrying out the reaction chamber of described plasma etching operation is T
2, T
2Less than T
1
Especially, the step of carrying out the operation of described plasma etching comprises:
The cooling operation is carried out in the substrate of experiencing described degas operation;
The plasma etching operation is carried out in the substrate of experiencing described cooling operation.
Compared with prior art, technique scheme has the following advantages:
The plasma precleaning method that technique scheme provides, by carrying out between the operation of described degas operation and plasma etching, the cooling operation is carried out in the substrate of experiencing described degas operation, with the temperature difference between the reaction chamber that reduces to experience the substrate of described degas operation in the prior art and carry out described plasma etching operation, to reduce because the temperature of described substrate is higher than plasma etching that the temperature of the reaction chamber of carrying out described plasma etching operation causes operates and carry out the intensification of degree, and cause thus after via the operation of set plasma etching, exceed the electric charge coupling of gate oxide ability to bear in the device that in described substrate, forms and the gate oxide that causes damages.
Description of drawings
Fig. 1 is a schematic flow sheet of carrying out the plasma body pre-cleaning operation in the prior art;
Fig. 2 is a schematic flow sheet of carrying out the plasma body pre-cleaning operation in the first embodiment of the invention;
Temperature was to the impact effect contrast synoptic diagram of device performance when Fig. 3 carried out the plasma body pre-cleaning operation for explanation;
Fig. 4 contrasts synoptic diagram for using the preferred embodiment of the present invention with the defects detection result who uses the device that forms behind the prior art execution plasma body pre-cleaning operation;
Fig. 5 is for using the preferred embodiment of the present invention and the WAT detected result contrast synoptic diagram of using the device that forms behind the prior art execution plasma body pre-cleaning operation;
Fig. 6 is for using the preferred embodiment of the present invention and the reliability detected result contrast synoptic diagram of using the device that forms behind the prior art execution plasma body pre-cleaning operation.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 2, as the first embodiment of the present invention, the concrete steps of carrying out the plasma body pre-cleaning operation comprise step 21: degas operation is carried out in substrate, and the temperature that experiences the substrate of described degas operation is T
1Step 22: the cooling operation is carried out in the substrate of experiencing described degas operation; Step 23: the plasma etching operation is carried out in the substrate of experiencing described cooling operation, and the temperature of carrying out the reaction chamber of described plasma etching operation is T
2, T
2Less than T
1
Described substrate can be in the manufacture of semiconductor any need to carry out the plasma body pre-cleaning operation at goods, as, need to carry out the plasma body pre-cleaning operation forming between the operation of adhesive linkage that dual-damascene structure and deposition cover the diapire of described dual-damascene structure and sidewall, at this moment, described substrate for go up the definition device active region at substrate (substrate) and finish shallow trench isolation from, then form grid structure and source region and drain region after, and then deposit first interlayer dielectric layer, and in described first interlayer dielectric layer, form behind the dual-damascene structure and form at goods; Perhaps, continue to fill described dual-damascene structure, after in described first interlayer dielectric layer, forming the first layer interconnection line, continue deposition N-1 interlayer dielectric layer, and in described N-1 interlayer dielectric layer, form behind the dual-damascene structure and form at goods.Obviously, the number N of described interlayer dielectric layer can be any natural number, and as 1,3,5,7 or 9 etc., the concrete number of described interlayer dielectric layer is determined according to product requirement.Described grid structure comprises the side wall and the gate oxide of grid, all around gate.Described grid structure also can comprise the blocking layer that covers described grid and side wall.Described substrate is including but not limited to the silicon materials that comprise element, and for example the silicon of monocrystalline, polycrystalline or non-crystal structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).
Can adopt PECVD (plasma enhanced CVD), SACVD (inferior normal pressure chemical vapor deposition) or LPCVD traditional technologys such as (low-pressure chemical vapor phase depositions) to form described medium layer.Described medium layer can be advanced low-k materials, and described advanced low-k materials includes but not limited to black diamond (Black Diamond, a kind of BD) or among the coral.Described medium layer material also can be including but not limited to unadulterated silicon-dioxide (SiO
2), phosphorosilicate glass (PSG), borosilicate glass (BSG), boron-phosphorosilicate glass (BPSG), fluorine silex glass (FSG) or have a kind of or its combination in the advanced low-k materials.
Described degas operation (degas) in order to remove above-mentioned substrate in the storing process, carry out in the pitch time between each step and carrying out the moisture of introducing after the wet clean operation that may carry out before the described plasma etching operation.Usually, the temperature range when carrying out described degas operation in the reaction chamber is 200 degrees centigrade-300 degrees centigrade (as 250 degrees centigrade), experience described degas operation after, the temperature of above-mentioned substrate is T
1, T
1Scope be 200 degrees centigrade-300 degrees centigrade (as 250 degrees centigrade).
After experiencing described degas operation; for described substrate is continued subsequent deposition or etching operation; usually also need the plasma clean operation is carried out in described substrate; described plasma clean operation still is the plasma etching operation in essence; promptly; utilize plasma etch process before continuing subsequent deposition or etching operation; removal residue in described substrate surface impurity (as; in transfer process, be adsorbed in the micronic dust [described protection gas means described substrate residing atmosphere surrounding in transfer process] in the described suprabasil protection gas; and; after described substrate placed reaction chamber, by peeling off and be attached to described suprabasil particulate etc. on the described reaction chamber wall).In the presents, will continue before subsequent deposition or the etching operation described substrate, for purify described substrate (as, remove moisture, decon) operation carried out is referred to as the plasma body pre-cleaning operation.
After experiencing described degas operation, the temperature T of described substrate
1Be generally 200 degrees centigrade-300 degrees centigrade (as 250 degrees centigrade), and in the practice, the temperature of the plasma etching operation of proceeding then is generally room temperature, promptly, in the conventional art, carry out in the process of described plasma body pre-cleaning operation, the temperature variation of described substrate is bigger, needs by the temperature T after the described degas operation of experience
1Room temperature when the described plasma etching of execution is operated is close.
After analyzing, the present inventor thinks, the gate oxide damage that exists in the device of foregoing experience plasma body pre-cleaning operation, and promptly relevant with described substrate bigger temperature variation in plasma body pre-washing process.
Particularly, the present inventor thinks after analyzing, the formation reason of described gate oxide damage is: in traditional plasma body pre-washing technology, the temperature of carrying out described plasma etching operation is a room temperature, promptly, at ambient temperature, the plasma body of being introduced by the operation of described plasma etching influence that device is caused is can be received; But, because in the actual production, before carrying out described plasma etching operation, also need carry out described degas operation, and the temperature of reaction chamber is higher when carrying out described degas operation, as 200 degrees centigrade-300 degrees centigrade (as 250 degrees centigrade), after the described degas operation of feasible experience, the temperature of described substrate is generally 200 degrees centigrade-300 degrees centigrade (as 250 degrees centigrade), then, pyritous substrate like this is placed under the room temperature environment, when carrying out the operation of described plasma etching, to make the temperature of carrying out described plasma etching operation be higher than room temperature, temperature raises and will cause described plasma body more active, makes described plasma body aggravate the influence that device causes, promptly, active action of plasma is easier to exceed the electric charge coupling of gate oxide ability to bear behind described device, and makes the gate oxide damaged in the described device.
For above-mentioned analysis, the present inventor has carried out antenna ratio (antenna ratio) detection and has been verified.Described antenna ratio is used for weighing the probability that antenna effect can take place a chips.
Metal wire or polysilicon conductors such as (poly) in the IC chip, just like antenna one by one, when the free electric charge, these " antennas " just can collect them, antenna is long more, and the electric charge of collection is also just many more, when electric charge is abundant, will discharge, this effect is described antenna effect.
In CMOS technology, P type substrate is to want ground connection, if these have been collected between the conductor of electric charge and substrate electric path is arranged, and these electric charges will be gone to substrate and get on so, will can not cause what influence; If this path does not exist, these electric charges still will bleed off, so, will in any discharge to where causing irremediable consequence, in general, the easiest place of being injured is exactly a gate oxide.
The definition of " antenna ratio " is: the area of the conductor (generally being metal) of formation so-called " antenna " and the ratio of the gate oxide area that is linked to each other.The size of grid is more little, and the number of plies of metal is many more, and the possibility that antenna effect takes place is just big more.
As shown in Figure 3, the ordinate zou leakage current is in order to indicate the degree of described gate oxide damaged, and as seen, curve 1 and 2 is represented base reservoir temperature respectively when being 340 degrees centigrade and 145 degrees centigrade leakage current is with the change curve of " antenna ratio ".Along with the rising of the temperature of the substrate of carrying out described plasma etching operation (as, when rising to 340 degrees centigrade) by 145 degrees centigrade, corresponding identical leakage current, " the antenna ratio " of the substrate correspondence that temperature is lower is bigger, that is, the substrate that temperature is lower can obtain the identical leakage current that the higher substrate of temperature obtains down at littler " antenna ratio " down at bigger " antenna ratio "; Perhaps, for identical " antenna ratio ", the leakage current of the substrate correspondence that temperature is lower is less than the leakage current of the higher substrate correspondence of temperature.
Thus, the present inventor is by carrying out between the operation of described degas operation and plasma etching, the cooling operation is carried out in the substrate of experiencing described degas operation, with the temperature difference between the reaction chamber that reduces to experience the substrate of described degas operation in the conventional art and carry out described plasma etching operation, to reduce because the temperature of described substrate is higher than plasma etching operation the carrying out intensification of degree that the temperature of the reaction chamber of carrying out described plasma etching operation causes, and cause thus after via the operation of set plasma etching, the electric charge coupling that exceeds the gate oxide ability to bear in the device that in described substrate, forms, and the gate oxide damaged in the described device that causes.As shown in Figure 3, curve 3 representatives are to the change curve of substrate cooling back leakage current with " antenna ratio ".
Described cooling operation both can independently carried out in the hypothermic response chamber, also can operate in the same reaction chamber with described plasma etching and carry out; Described cooling operation operates in the same reaction chamber with described plasma etching to be carried out, and is beneficial to simplify the operation, and reduces the transfer number of described substrate between the differential responses chamber, then, reduces the probability that produces defective.
Described cooling operation operates in when carrying out in the same reaction chamber with described plasma etching, and employing will be experienced the mode of substrate vacant scheduled time in the reaction chamber of carrying out described plasma etching operation of described degas operation and carry out described cooling operation.Term " vacant " means after described degas operation is experienced in described substrate, described substrate is placed in the reaction chamber of carrying out described plasma etching operation, but described plasma etching operation is not carried out in described substrate.
What in fact, described substrate was carried out in described reaction chamber is the heat exchange of nature.Thus, the not only generation of described heat exchange for the benefit of, but also the described cooling operation of for the benefit of in same reaction chamber, carrying out follow-up plasma etching operation is produced the little influence of trying one's best, when carrying out described vacant operation, also should comprise an amount of buffer gas in the described reaction chamber, described buffer gas can be Ar, N
2Or He.When described buffer gas was Ar, its flow velocity can be 50sccm-200sccm, as, 100sccm, 150sccm.
The described scheduled time is unsuitable long, to avoid causing production efficiency low excessively for reducing the improvement that described gate oxide damage introduced; The described scheduled time is also unsuitable too short, to prevent owing to described cooling operation is carried out not thoroughly, after causing experiencing described cooling operation, the temperature difference between the reaction chamber of the described plasma etching reaction of described substrate and execution is still excessive, causes for reducing the deleterious that described gate oxide damage improves.Thus, preferably, the described scheduled time is 10 seconds-30 seconds.
Through as the above analysis, the temperature of substrate that experiences described cooling operation is low more, is beneficial to the damage that reduces described gate oxide more, because the temperature of reaction when carrying out described plasma etching operation is a room temperature, therefore, the temperature that experiences the substrate of described cooling operation can be equal to or less than room temperature.As example, the temperature that experiences the substrate of described degas operation is T
1, the temperature of reaction chamber is T when carrying out described plasma etching operation
2The time, the temperature that the substrate of experiencing described degas operation reduces in the process of carrying out described cooling operation is more than or equal to T
1-T
2
Be the improve effect of checking technique scheme to described gate oxide damage, the present inventor's correspondence is carried out the device that forms behind the plasma body pre-cleaning operation with above-mentioned preferred version with the application traditional scheme and is detected:
As shown in Figure 4, as seen, compare with using traditional scheme, after using above-mentioned preferred version and carrying out the plasma body pre-cleaning operation, in arbitrary wafer, concentrate the distributed areas of leakage current, and more approach target value.
In addition, (it is qualified to have detected) wafer that the present inventor's correspondence obtains when carrying out the plasma body pre-cleaning operation with above-mentioned preferred version with the application traditional scheme has carried out wafer acceptability test (WAT), specifically tested the square resistance (Rs) of the interconnection line that forms, as shown in Figure 5, the result shows, compare when carrying out the plasma body pre-cleaning operation with the application traditional scheme, after using above-mentioned preferred version execution plasma body pre-cleaning operation, the variation of the square resistance of the interconnection line of formation can be left in the basket.
(it is qualified to have detected) wafer that the present inventor's correspondence obtains when carrying out the plasma body pre-cleaning operation with above-mentioned preferred version with the application traditional scheme has carried out reliability test, and (test conditions is 250 degrees centigrade, 168 hours), as shown in Figure 6, as seen, compare with 2 with the device 1 of using the traditional scheme acquisition, the resistance change rate difference of using device 3 that technical scheme provided by the invention obtains and 4 very little (ordinate zou exists the chip of defective to account for the per-cent of comparable chip count when representing corresponding arbitrary resistance change rate shown in X-coordinate), stable performance.
To sum up, when using technique scheme and improving described gate oxide damage, can not produce detrimentally affect to the electric property and the reliability of wafer.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete processing parameter is determined according to product requirement and processing condition.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (9)
1. a plasma precleaning method comprises,
Degas operation is carried out in substrate, and the temperature that experiences the substrate of described degas operation is T
1
The plasma etching operation is carried out in the substrate of experiencing described degas operation, and the temperature of carrying out the reaction chamber of described plasma etching operation is T
2, T
2Less than T
1
It is characterized in that the step of carrying out described plasma etching operation comprises:
The cooling operation is carried out in the substrate of experiencing described degas operation;
The plasma etching operation is carried out in the substrate of experiencing described cooling operation.
2. plasma precleaning method according to claim 1 is characterized in that: the step of carrying out the operation of described cooling operation and plasma etching is carried out in same reaction chamber.
3. plasma precleaning method according to claim 2 is characterized in that: employing will be experienced the mode of substrate vacant scheduled time in the reaction chamber of carrying out described plasma etching operation of described degas operation and carry out described cooling operation.
4. plasma precleaning method according to claim 3 is characterized in that: the described scheduled time is 10 seconds-30 seconds.
5. plasma precleaning method according to claim 4 is characterized in that: when carrying out described cooling operation, comprise Ar in the described reaction chamber.
6. plasma precleaning method according to claim 5 is characterized in that: the flow velocity of Ar is 50sccm-200sccm.
7. plasma precleaning method according to claim 1 is characterized in that: the temperature of reaction when carrying out the operation of described plasma etching is a room temperature.
8. plasma precleaning method according to claim 7 is characterized in that: the temperature that experiences the substrate of described cooling operation is equal to or less than room temperature.
9. plasma precleaning method according to claim 8 is characterized in that: the temperature that the substrate of experiencing described degas operation reduces in the process of carrying out described cooling operation is more than or equal to T
2-T
1
Priority Applications (1)
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|---|---|---|---|
| CN200810224584A CN101724843A (en) | 2008-10-21 | 2008-10-21 | Plasma precleaning method |
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|---|---|---|---|
| CN200810224584A CN101724843A (en) | 2008-10-21 | 2008-10-21 | Plasma precleaning method |
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| CN101724843A true CN101724843A (en) | 2010-06-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110268503A (en) * | 2017-02-13 | 2019-09-20 | 爱德华兹有限公司 | Cleaning method |
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2008
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110268503A (en) * | 2017-02-13 | 2019-09-20 | 爱德华兹有限公司 | Cleaning method |
| CN110268503B (en) * | 2017-02-13 | 2022-07-19 | 爱德华兹有限公司 | Cleaning method |
| US11517942B2 (en) | 2017-02-13 | 2022-12-06 | Edwards, S.R.O. | Cleaning method |
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Application publication date: 20100609 |