CN101723312A - Method for preparing tri-dimension-limited crystal-facet-dependent silicon nanostructures - Google Patents
Method for preparing tri-dimension-limited crystal-facet-dependent silicon nanostructures Download PDFInfo
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- CN101723312A CN101723312A CN200810224109A CN200810224109A CN101723312A CN 101723312 A CN101723312 A CN 101723312A CN 200810224109 A CN200810224109 A CN 200810224109A CN 200810224109 A CN200810224109 A CN 200810224109A CN 101723312 A CN101723312 A CN 101723312A
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Abstract
The invention provides a method for preparing a tri-dimension-limited crystal-facet-dependent silicon nanostructure, which is characterized by comprising the following steps: (a) taking silicon-on-insulator (SOI) as a substrate; (b) scribing on the substrate along the crystal orientation (110) as a reference direction for exposure; (c) performing heat oxidation on the substrate to generate a silica mask layer; (d) adopting electron-beam exposure to generate a plane figure; (e) eroding the silica mask layer by using isotropic corrosive liquids; and (f) obtaining the tri-dimension-limited crystal-facet-dependent silicon nanostructure on the silicon layer below the silica mask layer by using isotropic wet corrosion.
Description
Technical field
The present invention relates to the semiconductor micro-nano manufacture field in the nanoelectronic technology, relate in particular to a kind of manufacture craft of utilizing electron beam exposure to combine with the anisotropic silicon wet etching, (100) to silicon-on-insulator (SOI) substrate on preparation can be applied to the processing method of three-dimensional restriction silicon nanostructure of the crystal-facet-dependent of quantum device
Background technology
The nanoelectronic technology is a most important branch in the nanometer technology, the main research contents of nanoelectronic technology be characteristic size be the 0.1-100 nanometer range nanostructured processing and have the research and development of the electronic device of quantum effect.Traditional quantum device has only utilized the corpuscular property in the electronics duality principle, realizes Signal Processing by the quantity that controls electronics.Along with the raising of integrated level, the speed of circuit, power consumption all become serious problem.In comparatively ideal quantum device, not the number that passes through the control electronics separately, mainly be to realize certain function by the phase place of controlling electronic wave, therefore, quantum device has higher corresponding speed and lower power consumption, has good development prospect.For the realization of quantum device, must there be corresponding micro-nano process technology to be complementary with it.
Electron beam exposure is a kind of high-resolution photoetching technique that grows up from the SEM technical foundation sixties in last century.Twentieth century is since the nineties, beautiful, day some research departments adopt electron beam lithographies to succeed in developing 0.1 micron cmos device in succession, the HEMT device of 0.04 micron MOSFET and 0.05 micron.Now, the technical merit of electron beam exposure has been advanced to nanoscale, and state-of-the-art e-beam direct-writing exposure system can focus on 2 nanometers to beam spot, and the thinnest figure that exposes is 8 nanometers.Undoubtedly, electron beam exposure will become the strong candidate of quantum effect device fabrication of new generation.
The anisotropic silicon wet etching is mainly used in the preparation of the micron dimension structure in MEMS field in the past, as diaphragm in pressure or the acceleration sensor or cantilever beam structures.This technology mainly is to utilize the different crystal faces of silicon to have this characteristic of different corrosion rates in corrosive liquid, can process various micro-structurals on silicon substrate.
Quantum device will be realized working under the room temperature and necessarily require its characteristic size in the scope less than 10 nanometers, and small surface undulation all can cause the disturbance of quantum effect, therefore, requires prepared nanostructured surface very smooth, reduces to rise and fall as far as possible.The anisotropic wet corrosion can obtain to depend on the structure of crystal face, can obtain to be much better than the etching surface that other lithographic method obtains.Smooth surface also helps reducing the influence of surface state to device performance simultaneously.In recent years, in the preparation of the nanostructured of single-electron device, the anisotropic wet corrosion also was widely adopted.Wherein, the most representative Tokyo Univ Japan industrial research institute has carried out long term research aspect silicon based single electron transistor.Their groundwork in this respect is a technology of utilizing electron beam exposure to combine with the anisotropic silicon wet etching, and is auxiliary again with technologies such as oxidations, prepares the single-electronic transistor that can at room temperature work on the SOI substrate.For realizing the restriction of size on the vertical direction, in the starting stage of preparation single-electronic transistor technology, the top layer silicon of SOI substrate is thinned to 20 nanometers.Utilize the prepared single-electronic transistor of this technology can at room temperature observe coulomb blockade effect and differential conductance effect.[H.Ishikuro?and?T.Hiramoto.Quantum?mechanical?effects?in?thesilicon?quantum?dot?in?a?single-electron?transistor，AppliedPhysics?Letters，71，1997，p.3691]。
Yet, owing to adopted the technology of top layer silicon attenuate, the thickness of the top layer silicon except that the nanostructured region also only has the 20-50 nanometer, this brings very big difficulty for follow-up ohmic contact craft, simultaneously, thin top layer silicon also can increase the resistance of device, makes the power consumption of device increase, and is unfavorable for the integrated on a large scale of device.
Summary of the invention
The object of the present invention is to provide a kind of processing method that on the top layer silicon of SOI substrate, prepares the three-dimensional restriction silicon nanostructure of crystal-facet-dependent, to reach the simplification processing step, reduce silicon nanostructure quantum size difference, reduce the loss of the top layer silicon of non-nano structural region, reduce the purpose of place circuitous resistance.
The invention provides a kind of preparation method of three-dimensional restriction silicon nanostructure of crystal-facet-dependent, it is characterized in that, comprise the steps:
(a) with silicon-on-insulator as substrate;
(b) in substrate upper edge＜110〉the crystal orientation direction carries out scribing, the reference direction during as exposure;
(c) substrate is carried out thermal oxide, generate the earth silicon mask layer;
(d) adopt electron beam exposure, generate planar graph;
(e) adopt isotropic etch liquid that the earth silicon mask layer is corroded;
(f) adopt the anisotropic wet corrosion again, on the silicon layer under the earth silicon mask layer, obtain the three-dimensional restriction silicon nanostructure of crystal-facet-dependent.
Wherein the high preferred orientation of the top layer silicon of silicon-on-insulator material be (100) to.
Wherein electron beam exposure is to adopt eurymeric electron beam adhesive PMMA as resist.
The planar graph that wherein adopts electron beam exposure to generate, this figure are the regional both ends opens of realizing three-dimensional restriction on the basis of nanometer bargraphs at needs, and the nanometer line orientations is parallel with the scribing direction during exposure.
Wherein isotropic etch liquid is the mixed liquor of hydrofluoric acid, ammonium fluoride and water.
Wherein the anisotropic wet corrosive liquid is the mixed solution of TMAH, isopropyl alcohol and water.
From technique scheme as can be seen, the present invention has following beneficial effect:
(1) utilizes the present invention, the structure that the anisotropic wet caustic solution that adopts in the sample corrosion process obtains is the crystal face restriction, therefore the surface is very smooth, can effectively overcome silicon based single electron transistor because the inconsistency of the quantum electric property that the quantum dot size difference is brought.
2, utilize the present invention,, realized that so promptly the generation of quantum effect has guaranteed that again the thickness of the silicon that other is regional is not influenced by corrosion process need not sample is carried out just to obtain all enough little size on three dimensions under the situation of reduction processing.This makes follow-up ohmic contact craft can adopt common process to be prepared, and simultaneously, keeps less device resistance, more helps the integrated on a large scale of device.
Description of drawings
About aforementioned and other technology contents, characteristics and effect of the present invention, in the detailed description of following cooperation preferred embodiment with reference to the accompanying drawings, can clearly present, wherein:
Fig. 1 is through thermal oxide, the side view of the SOI substrate behind the whirl coating;
Fig. 2 limits the flow chart of silicon nanostructure for the three-dimensional of making crystal-facet-dependent.
The specific embodiment
Fig. 1 is the process thermal oxide, and the side view of the SOI material behind the whirl coating comprises:
(1) silicon-on-insulator SOI substrate comprises silicon base 1, buried oxide layer 2 and top layer silicon 3;
(2) carry out thermal oxide at the SOI material surface, generate the earth silicon mask layer 4 of 20 nanometer thickness;
(3) in thermal oxide earth silicon mask laminar surface spin coating PMMA EL4 electron beam adhesive 5, the spin coating rotating speed is 3000rpm, and glue is thick to be about about 200nm.
See also Fig. 2, Figure 2 shows that the flow chart of the three-dimensional restriction silicon nanostructure of making crystal-facet-dependent, the preparation method of the three-dimensional restriction silicon nanostructure of a kind of crystal-facet-dependent of the present invention comprises the steps:
Step S10: with silicon-on-insulator as substrate, the high preferred orientation of the top layer silicon of this silicon-on-insulator material be (100) to;
Step S20: in substrate upper edge＜110〉the crystal orientation direction carries out scribing, the reference direction during as exposure;
Step S30: substrate is carried out thermal oxide, generate the earth silicon mask layer;
Step S40: adopt electron beam exposure, generate planar graph, this electron beam exposure is to adopt eurymeric electron beam adhesive PMMA as resist, the planar graph that described employing electron beam exposure generates, this figure is a regional both ends open of realizing three-dimensional restriction on the basis of nanometer bargraphs at needs, and the nanometer line orientations is parallel with the scribing direction during exposure;
Step S50: adopt isotropic etch liquid that the earth silicon mask layer is corroded;
Step S60: adopt the anisotropic wet corrosion again, on the silicon layer under the earth silicon mask layer, obtain the three-dimensional restriction silicon nanostructure of crystal-facet-dependent, described isotropic etch liquid is the mixed liquor of hydrofluoric acid, ammonium fluoride and water, and described anisotropic wet corrosive liquid is the mixed solution of TMAH, isopropyl alcohol and water.
The method that combines with the anisotropic silicon wet etching based on electron beam exposure provided by the present invention is applicable to the preparation of nanostructured in the novel silicon quantum device.In the nanostructured preparation of existing quantum device, for realizing the small size requirement of nanostructured, the Exposure mode of many employing high-resolution is realized the size restrictions on the horizontal direction, and the method that the many employings of size restrictions are in vertical direction carried out attenuate with the top layer silicon of SOI material realizes, but, the thickness of thin top layer silicon brings certain difficulty can for follow-up technologies such as Ohmic contact, and can bring bigger resistance to device, and thin top layer silicon thickness can not be used for other preparation of devices, is unfavorable for the integrated on a large scale of device.The present invention utilizes the silicon nanostructure of the three-dimensional restriction of characteristic preparation of mask graph design cleverly and anisotropic silicon wet etching, its key feature is need not that sample is carried out reduction processing just can obtain all enough little size on three dimensions, and institute's machine silicon nanostructured is characterised in that: limit by particular crystal plane each side; For the nanostructured part, the zone of nano wire upper shed all can be corroded on vertical direction and the horizontal direction in the anisotropic wet corrosion process in the exposure figure, the final crystal face that forms by two downward-sloping inside contractions docks the sunk structure that forms, other regional top layer silicon thickness is not subjected to the influence of corrosion process, also the thickness behind the maintenance preparation mask has realized that so promptly the generation of quantum effect has guaranteed that again other regional technology is unaffected.Simultaneously owing to adopt anisotropic etch, the nanostructured that obtains all with specific crystal face as the restriction crystal face, so body structure surface is very smooth, has reduced the influence of surface state to device performance effectively.
Embodiment
Based on the flow chart of the silicon nanostructure of the three-dimensional of preparation crystal-facet-dependent illustrated in fig. 2 restriction, the method for silicon nanostructure that the present invention is prepared the three-dimensional restriction of crystal-facet-dependent below in conjunction with specific embodiment further describes.
A kind of process implementing method of utilizing electron beam exposure provided by the invention specifically comprises the steps:
Reference direction when (1) determining electron beam exposure: since (100) to the sign limit of SOI substrate along＜110 the crystal orientation direction, can be used as the reference edge of scribing, in follow-up electronic beam exposure process, the reference direction when being further used as electron beam exposure;
(2) thermal oxide: the top layer silicon on the SOI substrate shown in Fig. 13 is carried out thermal oxide, form the thick earth silicon mask layer 4 of one deck 20nm on the surface of top layer silicon 3, the silica of this layer thermal oxide in follow-up technology as anisotropic wet corrosion mask layer.
(3) spin coating electron beam adhesive: at silica 4 surperficial spin coating one deck electron beam adhesive 5PMMA EL4 of the thermal oxide shown in Fig. 1, the rotating speed of gluing is 3000rpm, and the thickness of the glue that obtains is about 200nm, and pre-bake temperature is 180 ℃, and baking is 10 minutes on hot plate.
(4) electron beam exposure: have the SOI substrate surface of electron beam adhesive 5PMMA EL4 to carry out electron beam exposure in spin coating, exposure figure is designed to the version in the nano wire upper shed.Develop by the mixed liquor of tetramethyl two pentanones (MIBK) with isopropyl alcohol (IPA), isopropyl alcohol (IPA) photographic fixing is transferred to designed exposure figure on the electron beam adhesive 5 after nitrogen dries up, and carries out post bake in baking oven, and temperature is 110 ℃, and the time is 10 minutes.
(5) corrosion of earth silicon mask layer: utilize the mixed liquor of hydrofluoric acid (HF), ammonium fluoride (NH4F) and water (H2O) that the sample after handling in (4) is carried out isotropic etch, etching time 20 seconds, remove electron beam adhesive with acetone, at this moment, exposure figure has been transferred to the earth silicon mask layer from glue-line.
(6) formation of the three-dimensional restriction of crystal-facet-dependent silicon nanostructure: with TMAH
(TMAH), the mixed solution of isopropyl alcohol (IPA) and water (H2O) is as silicon anisotropic etching liquid, finally prepares the silicon nanostructure of the three-dimensional restriction that crystal face relies on silicon.The zone of nano wire upper shed all can be corroded on vertical direction and the horizontal direction in the anisotropic wet corrosion process in the exposure figure, the final crystal face that forms by two downward-sloping inside contractions docks the sunk structure that forms, other regional top layer silicon thickness is not subjected to the influence of corrosion process, also the thickness behind the maintenance preparation mask.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the preparation method of the three-dimensional of crystal-facet-dependent restriction silicon nanostructure is characterized in that, comprises the steps:
(a) with silicon-on-insulator as substrate;
(b) in substrate upper edge＜110〉the crystal orientation direction carries out scribing, the reference direction during as exposure;
(c) substrate is carried out thermal oxide, generate the earth silicon mask layer;
(d) adopt electron beam exposure, generate planar graph;
(e) adopt isotropic etch liquid that the earth silicon mask layer is corroded;
(f) adopt the anisotropic wet corrosion again, on the silicon layer under the earth silicon mask layer, obtain the three-dimensional restriction silicon nanostructure of crystal-facet-dependent.
2. the preparation method of the three-dimensional of crystal-facet-dependent according to claim 1 restriction silicon nanostructure is characterized in that, wherein the high preferred orientation of the top layer silicon of silicon-on-insulator material be (100) to.
3. the preparation method of the three-dimensional of crystal-facet-dependent according to claim 1 restriction silicon nanostructure is characterized in that, wherein electron beam exposure is to adopt eurymeric electron beam adhesive PMMA as resist.
4. the three-dimensional of crystal-facet-dependent according to claim 3 limits the preparation method of silicon nanostructure, it is characterized in that, the planar graph that wherein adopts electron beam exposure to generate, this figure is a regional both ends open of realizing three-dimensional restriction on the basis of nanometer bargraphs at needs, and the nanometer line orientations is parallel with the scribing direction during exposure.
5. the preparation method of the three-dimensional of crystal-facet-dependent according to claim 1 restriction silicon nanostructure is characterized in that wherein isotropic etch liquid is the mixed liquor of hydrofluoric acid, ammonium fluoride and water.
6. the three-dimensional of crystal-facet-dependent according to claim 1 limits the preparation method of silicon nanostructure, and its characteristic is that wherein the anisotropic wet corrosive liquid is the mixed solution of TMAH, isopropyl alcohol and water.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157371A (en) * | 2011-03-23 | 2011-08-17 | 北京大学 | Method for producing monocrystalline silicon nanometer structure |
| CN103050155A (en) * | 2012-11-06 | 2013-04-17 | 国家核电技术有限公司 | Accident relieving device as well as manufacturing method, nuclear power station pressure container and accident relieving method of accident relieving device |
| CN104600196A (en) * | 2015-01-09 | 2015-05-06 | 浙江大学 | Preparation method of conductive organic matter/silicon nanowire solar cell and product thereof |
| CN110690103A (en) * | 2019-09-06 | 2020-01-14 | 西安电子科技大学 | Nanoscale thinning method, direct band gap strain SOI and preparation method thereof |
-
2008
- 2008-10-15 CN CN200810224109A patent/CN101723312A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157371A (en) * | 2011-03-23 | 2011-08-17 | 北京大学 | Method for producing monocrystalline silicon nanometer structure |
| CN102157371B (en) * | 2011-03-23 | 2012-08-22 | 北京大学 | Method for producing monocrystalline silicon nanometer structure |
| CN103050155A (en) * | 2012-11-06 | 2013-04-17 | 国家核电技术有限公司 | Accident relieving device as well as manufacturing method, nuclear power station pressure container and accident relieving method of accident relieving device |
| CN104600196A (en) * | 2015-01-09 | 2015-05-06 | 浙江大学 | Preparation method of conductive organic matter/silicon nanowire solar cell and product thereof |
| CN104600196B (en) * | 2015-01-09 | 2017-08-01 | 浙江大学 | A kind of preparation method of conductive organic matter/silicon nanometer line solar battery and products thereof |
| CN110690103A (en) * | 2019-09-06 | 2020-01-14 | 西安电子科技大学 | Nanoscale thinning method, direct band gap strain SOI and preparation method thereof |
| CN110690103B (en) * | 2019-09-06 | 2021-11-19 | 西安电子科技大学 | Nanoscale thinning method, direct band gap strain SOI and preparation method thereof |
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Application publication date: 20100609 |