CN101719772A - Low-frequency time-code lock phase receiver - Google Patents
Low-frequency time-code lock phase receiver Download PDFInfo
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- CN101719772A CN101719772A CN 200910218988 CN200910218988A CN101719772A CN 101719772 A CN101719772 A CN 101719772A CN 200910218988 CN200910218988 CN 200910218988 CN 200910218988 A CN200910218988 A CN 200910218988A CN 101719772 A CN101719772 A CN 101719772A
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Abstract
The invention relates to a low-frequency time-code lock phase receiver which is formed by connecting a time-code signal amplifying circuit, an active filter circuit, a gain optional amplifying circuit, a lock phase loop circuit, a voltage comparator circuit and a pulse shaping drive circuit, wherein the output end of the time-code signal amplifying circuit is connected with the active filter circuit; the output end of the active filter circuit is connected with the gain optional amplifying circuit; the output end of the gain optional amplifying circuit is connected with the lock phase loop circuit; the output end of the lock phase loop circuit is connected with the voltage comparator circuit; and the output end of the voltage comparator circuit is connected with the pulse shaping drive circuit. The low-frequency time-code lock phase receiver has the advantages of strong capacity of resisting disturbance, high sensitivity, light weight, low energy consumption, large storage capacity, automatic recording of measured data and positioned data, simple and convenient operation, and the like and is necessary measurement equipment for users who research the signal propagation characteristics of low-frequency time-code signals.
Description
Technical field
The invention belongs to the telecommunication technology field, be specifically related to low-frequency time-code lock phase receiver.
Background technology
Existing low-frequency time-code time service broadcast platform, transmitting power 100KW, 24 hours continuous broadcast has covered the most of area of China.
Ionosphere is the part of earth upper atmosphere, and owing to solar ultraviolet, X-radiation, atmosphere a large amount of free electrons and ion have been occurred by partly ionization in upper atmosphere, radio direction of wave travel, phase place, amplitude etc. are changed.In the effective coverage range that solves low-frequency time-code broadcast platform,, need carry out quantitative and qualitative ground and analyze the technical problem of lower ionosphere electron concentration low-frequency time-code carrier signal phase delay transit that variation causes.Usually, measure receiving equipment and several hundred kilometers is arranged to thousands of kilometers apart from transmitting station, the signal of measuring the receiving equipment reception is very faint, add various industrial interference and electronic jamming that the city exists, the signal to noise ratio and anti-interference, the receiving sensitivity that improve receiver are the technical problems that current low-frequency time-code Service of Timing field needs emphasis to solve.
Summary of the invention
Technical problem to be solved by this invention is to provide that a kind of antijamming capability is strong, highly sensitive, in light weight, energy consumption is low, memory capacity is big, the data measured of record and locator data, low-frequency time-code lock phase receiver easy and simple to handle automatically.
Solving the problems of the technologies described above the technical scheme that is adopted is that it comprises: the time code signal amplifying circuit that the low-frequency time-code analog signal that is received is amplified; Active filter circuit, the input termination time code signal amplifying circuit of this circuit; The optional amplifying circuit that gains, the input of this circuit is connected to the source filter circuit; Phase-locked loop circuit, the input termination of this circuit optional amplifying circuit that gains; Voltage comparator circuit, the input termination phase-locked loop circuit of this circuit; It also comprises the shaping pulse drive circuit, the input termination voltage comparator circuit of this circuit.
Phase-locked loop circuit of the present invention is: 10 pin of a termination integrated circuit U2 of capacitor C 7,6 pin of another termination integrated circuit U3 also connect an end of capacitor C 8 by resistance R 16,2 pin of integrated circuit U3 connect the adjustable end of potentiometer P5 by resistance R 17,1 pin and 10 pin connect the end of potentiometer P5 and the end of 5V positive source and potentiometer P4,16 pin connect the end of potentiometer P4 by resistance R 13,15 pin connect the other end and the adjustable end of potentiometer P4 by resistance R 12,14 pin connect an end of capacitor C 6,13 pin and 12 pin connect the two ends of capacitor C 4 and capacitor C 5 respectively, 4 pin connect an end of capacitor C 3,5 pin connect an end of capacitor C 2,8 pin connect the other end and the ground of capacitor C 2 and capacitor C 3,7 pin connect an end of capacitor C 8 and an end of resistance R 15, the other end of 3 pin and 9 pin connecting resistance R15 also connects in-phase input end 2 pin of the integrated circuit U4 of voltage comparator circuit, the other end ground connection of capacitor C 8 and capacitor C 6 and potentiometer P5 by resistance R 14; The model of integrated circuit U2 is AD625; The model of integrated circuit U3 is NE564.
Voltage comparator circuit of the present invention is: in-phase input end 2 pin of integrated circuit U4 connect 9 pin of integrated circuit U3 by resistance R 14, inverting input 3 pin connect the adjustable end of potentiometer P6 by resistance R 20, positive power source terminal 8 pin connect the end of potentiometer P6 and 5V positive source and connect output by resistance R 18, output 7 pin connect an end of capacitor C 9, the other end ground connection of 1 pin and 4 pin and potentiometer P6 also connects input 1 pin of the integrated circuit U5A of the other end of capacitor C 9 and shaping pulse drive circuit by resistance R 19; The model of integrated circuit U4 is LM311.The model of integrated circuit U5A is 74HCl4.
Shaping pulse drive circuit of the present invention is: input 1 pin of integrated circuit U5A connects the other end of capacitor C 9, input 3 pin that output 2 pin meet integrated circuit U5B, the output 4 pin output of integrated circuit U5B.The model of integrated circuit U5B is 74HCl4.
The present invention adopts phase-locked loop circuit that the frequency and the phase place of the low-frequency time-code carrier signal received are carried out from motion tracking, and the signal extraction that will mix in noise through loop filtering goes out.According to the rule that the low-frequency time-code carrier phase is changed, the time period of optimum reception lf time-code signal is proposed, choose for the time user, the user can obtain correct time information better.The present invention has that antijamming capability is strong, highly sensitive, in light weight, energy consumption is low, memory capacity is big, the data measured of record and locator data, advantage such as easy and simple to handle automatically, to the user of the research lf time-code signal propagation characteristic measuring equipment that is absolutely necessary.
Description of drawings
Fig. 1 is an electrical principle block diagram of the present invention.
Fig. 2 is an electronic circuit schematic diagram of the present invention.
Embodiment
The present invention is described in more detail below in conjunction with drawings and Examples, but the invention is not restricted to these embodiment.
Fig. 1 is an electrical principle block diagram of the present invention, referring to Fig. 1.In Fig. 1, the present invention is connected and composed by time code signal amplifying circuit, active filter circuit, the optional amplifying circuit of gain, phase-locked loop circuit, voltage comparator circuit, shaping pulse drive circuit.
The output of time code signal amplifying circuit is connected to the source filter circuit, the output termination of the active filter circuit optional amplifying circuit that gains, the output termination phase-locked loop circuit of optional amplifying circuit gains, the output termination voltage comparator circuit of phase-locked loop circuit, the output termination shaping pulse drive circuit of voltage comparator circuit.
In Fig. 2, the time code signal amplifying circuit of present embodiment is connected and composed by operational amplifier A 1, operational amplifier A 2, resistance R 1～resistance R 5, capacitor C 1, reception antenna L1.The model of operational amplifier A 1 and operational amplifier A 2 is OP27EP.The end, inverting input 2 pin that in-phase input end 3 pin of operational amplifier A 1 connect reception antenna L1 and capacitor C 1 by resistance R 2 connect output and by resistance R 1 ground connection, positive power source terminal 7 pin connect the 12V positive source, negative power end 4 pin connect 12V power cathode, output connect operational amplifier A 2 by resistance R 3 in-phase input end 3 pin, the other end ground connection of reception antenna L1 and capacitor C 1, reception antenna L1 is the low frequency loop receiving antenna, capacitor C 1 is a tuning capacity, and reception antenna L1 and capacitor C 1 connect and compose low-frequency time-code analog signal receiving circuit.Inverting input 2 pin of operational amplifier A 2 connect output by resistance R 5 and connect by resistance R 4 ground connection, positive power source terminal 7 pin that 12V positive source, negative power end 4 pin connect the 12V power cathode, output 6 pin are connected to the source filter circuit.Reception antenna L1 will receive the in-phase input end 3 pin input of faint low-frequency time-code analog signal via operational amplifier A 1, and the output after operational amplifier A 1, operational amplifier A 2 are amplified of low-frequency time-code analog signal has the noise signal of noise.
The active filter circuit of present embodiment is connected and composed by integrated circuit U1, resistance R 6～resistance R 9.The model of integrated circuit U1 is UAF42.Input 3 pin of integrated circuit U1 connect output 6 pin of operational amplifier A 2 and connect 13 pin, 12 pin by resistance R 6 ground connection, 8 pin by resistance R 9 and connect by resistance R 8 that 13 pin, 10 pin connect the 12V positive source, 9 pin connect 12V power cathode, 2 pin and 11 pin ground connection, 7 pin and connect 14 pin by resistance R 7 and connect the optional amplifying circuit of gain.Amplify back output by operational amplifier A 2 and have the input 3 pin input of the noise signal of noise from integrated circuit U1, integrated circuit U1 filters out clutter, and makes the low-frequency time-code carrier signal of 68.5KHz obtain amplifying.
The optional amplifying circuit of the gain of present embodiment is connected and composed by integrated circuit U2, resistance R 10, resistance R 11, potentiometer P1, potentiometer P2, potentiometer P3, and the model of integrated circuit U2 is AD625.1 pin of integrated circuit U2 connects 7 pin of integrated circuit U1,3 pin connect the end of potentiometer P1,4 pin connect the other end of potentiometer P1,9 pin connect adjustable end and the 12V positive source of potentiometer P1, the end of 5 pin connecting resistance R10, the other end of 2 pin connecting resistance R10 and the end of potentiometer P3,15 pin connect the other end of potentiometer P3 and adjustable end and connect 12 pin by resistance R 11,13 pin connect the end of potentiometer P2,14 pin connect the other end of potentiometer P2,8 pin connect adjustable end and the 12V power cathode of potentiometer P2,16 pin and 7 pin ground connection, 10 pin and 11 pin connect phase-locked loop circuit.The low-frequency time-code carrier signal is from the 1 pin input of integrated circuit U2, and integrated circuit U2 further amplifies back output to the low-frequency time-code carrier signal of input.
The phase-locked loop circuit of present embodiment is connected and composed by integrated circuit U3, resistance R 12～resistance R 17, capacitor C 2～capacitor C 8, potentiometer P4, potentiometer P5, and the model of integrated circuit U3 is NE564.10 pin of one termination integrated circuit U2 of capacitor C 7,6 pin of another termination integrated circuit U3 also connect an end of capacitor C 8 by resistance R 16,2 pin of integrated circuit U3 connect the adjustable end of potentiometer P5 by resistance R 17,1 pin and 10 pin connect the end of potentiometer P5 and the end of 5V positive source and potentiometer P4,16 pin connect the end of potentiometer P4 by resistance R 13,15 pin connect the other end and the adjustable end of potentiometer P4 by resistance R 12,14 pin connect an end of capacitor C 6,13 pin and 12 pin connect the two ends of capacitor C 4 and capacitor C 5 respectively, 4 pin connect an end of capacitor C 3,5 pin connect an end of capacitor C 2,8 pin connect the other end and the ground of capacitor C 2 and capacitor C 3,7 pin connect an end of capacitor C 8 and an end of resistance R 15, the other end of 3 pin and 9 pin connecting resistance R15 also connects voltage comparator circuit, the other end ground connection of capacitor C 8 and capacitor C 6 and potentiometer P5 by resistance R 14.Low-frequency time-code carrier signal through amplifying is from the 6 pin input of integrated circuit U3, and integrated circuit U3 also locks from the carrier frequency signaling of 9 pin output 68.5KHz from motion tracking the frequency and the phase place of the signal of input.
The voltage comparator circuit of present embodiment is connected and composed by integrated circuit U4, resistance R 18～resistance R 20, capacitor C 9, potentiometer P6, and the model of integrated circuit U4 is LM311.In-phase input end 2 pin of integrated circuit U4 meet integrated circuit U3 by resistance R 14 9 pin, inverting input 3 pin connect the adjustable end of potentiometer P6, a end that positive power source terminal 8 pin meet potentiometer P6 and 5V positive source and connect the other end and the shaping pulse drive circuit that output, output 7 pin connect the other end ground connection of an end, 1 pin and 4 pin of capacitor C 9 and potentiometer P6 and connect capacitor C 9 by resistance R 19 by resistance R 18 by resistance R 20.68.5KHz carrier frequency signaling is from the in-phase input end 2 pin input of integrated circuit U4, integrated circuit U4 picks out the very noisy in the input signal, and signal to noise ratio will further improve and output signal and Transistor-Transistor Logic level compatibility.
The shaping pulse drive circuit of present embodiment is connected and composed by integrated circuit U5A, integrated circuit U5B, and the model of integrated circuit U5A and integrated circuit U5B is 74HCl4.Input 1 pin of integrated circuit U5A connects the other end of capacitor C 9, input 3 pin that output 2 pin meet integrated circuit U5B, the output 4 pin output of integrated circuit U5B.The signal that integrated circuit U4 exports is from the input 1 pin input of integrated circuit U5A, and after integrated circuit U5A, integrated circuit U5B shaping, output and analog input signal are with the square-wave signal of the 68.5KHz of frequency homophase.
Claims (4)
1. low-frequency time-code lock phase receiver is characterized in that it comprises:
The time code signal amplifying circuit that the low-frequency time-code analog signal that is received is amplified;
Active filter circuit, the input termination time code signal amplifying circuit of this circuit;
The optional amplifying circuit that gains, the input of this circuit is connected to the source filter circuit;
Phase-locked loop circuit, the input termination of this circuit optional amplifying circuit that gains;
Voltage comparator circuit, the input termination phase-locked loop circuit of this circuit;
It also comprises the shaping pulse drive circuit, the input termination voltage comparator circuit of this circuit.
2. according to the described low-frequency time-code lock phase receiver of claim 1, it is characterized in that said phase-locked loop circuit is: 10 pin of a termination integrated circuit (U2) of electric capacity (C7), 6 pin of another termination integrated circuit (U3) also connect an end of electric capacity (C8) by resistance (R16), 2 pin of integrated circuit (U3) connect the adjustable end of potentiometer (P5) by resistance (R17), 1 pin and 10 pin connect an end of potentiometer (P5) and an end of 5V positive source and potentiometer (P4), 16 pin connect an end of potentiometer (P4) by resistance (R13), 15 pin connect the other end and the adjustable end of potentiometer (P4) by resistance (R12), 14 pin connect an end of electric capacity (C6), 13 pin and 12 pin connect the two ends of electric capacity (C4) and electric capacity (C5) respectively, 4 pin connect an end of electric capacity (C3), 5 pin connect an end of electric capacity (C2), 8 pin connect the other end and the ground of electric capacity (C2) and electric capacity (C3), 7 pin connect an end of electric capacity (C8) and an end of resistance (R15), the other end of 3 pin and 9 pin connecting resistances (R15) also connects in-phase input end 2 pin of the integrated circuit (U4) of voltage comparator circuit, the other end ground connection of electric capacity (C8) and electric capacity (C6) and potentiometer (P5) by resistance (R14); The model of integrated circuit (U2) is AD625; The model of integrated circuit (U3) is NE564.
3. according to the described low-frequency time-code lock phase receiver of claim 1, it is characterized in that said voltage comparator circuit is: in-phase input end 2 pin of integrated circuit (U4) connect 9 pin of integrated circuit (U3) by resistance (R14), inverting input 3 pin connect the adjustable end of potentiometer (P6) by resistance (R20), positive power source terminal 8 pin connect an end and the 5V positive source of potentiometer (P6) and connect output by resistance (R18), output 7 pin connect an end of electric capacity (C9), the other end ground connection of 1 pin and 4 pin and potentiometer (P6) also connects input 1 pin of the integrated circuit (U5A) of the other end of electric capacity (C9) and shaping pulse drive circuit by resistance (R19); The model of integrated circuit (U4) is LM311; The model of integrated circuit (U5A) is 74HC14.
4. according to the described low-frequency time-code lock phase receiver of claim 1, it is characterized in that said shaping pulse drive circuit is: input 1 pin of integrated circuit (U5A) connects the other end of electric capacity (C9), input 3 pin that output 2 pin connect integrated circuit (U5B), the output 4 pin output of integrated circuit (U5B); The model of integrated circuit (U5B) is 74HC14.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910218988 CN101719772B (en) | 2009-11-16 | 2009-11-16 | Low-frequency time-code lock phase receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910218988 CN101719772B (en) | 2009-11-16 | 2009-11-16 | Low-frequency time-code lock phase receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101719772A true CN101719772A (en) | 2010-06-02 |
| CN101719772B CN101719772B (en) | 2013-09-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910218988 Expired - Fee Related CN101719772B (en) | 2009-11-16 | 2009-11-16 | Low-frequency time-code lock phase receiver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107954177A (en) * | 2017-11-07 | 2018-04-24 | 陕西未来能源化工有限公司 | The monitoring device and its monitoring method of chain scrapper conveyor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4525685A (en) * | 1983-05-31 | 1985-06-25 | Spectracom Corp. | Disciplined oscillator system with frequency control and accumulated time control |
| JP2001042073A (en) * | 1999-07-27 | 2001-02-16 | Technol Seven Co Ltd | Standard wave synchronous clock device |
| CN1852288B (en) * | 2005-09-19 | 2010-05-12 | 华为技术有限公司 | Time transmitting method |
| CN201039093Y (en) * | 2007-05-30 | 2008-03-19 | 中国科学院国家授时中心 | Low-frequency time code front amplifier |
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2009
- 2009-11-16 CN CN 200910218988 patent/CN101719772B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107954177A (en) * | 2017-11-07 | 2018-04-24 | 陕西未来能源化工有限公司 | The monitoring device and its monitoring method of chain scrapper conveyor |
| CN107954177B (en) * | 2017-11-07 | 2023-11-17 | 陕西未来能源化工有限公司 | Monitoring device and monitoring method for double-chain scraper |
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| Publication number | Publication date |
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| CN101719772B (en) | 2013-09-18 |
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Granted publication date: 20130918 Termination date: 20151116 |