CN101705872A - FPGA-based distributed aeroengine electronic controller in chip and control method - Google Patents

Abstract

The invention provides an FPGA-based on-chip distributed aeroengine electronic controller and a control method, belonging to the technical field of engine control. The present invention comprises an input signal interface circuit (2), an FPGA chip (1), and an output signal interface circuit (3). The FPGA chip includes a synchronous serial bus DB, a synchronous clock line CLK, a synchronous control line SC and interconnected by these three lines. n processor modules with independent data space RAM and program space ROM, a synchronous control logic module used to control the synchronous work of each module inside the FPGA, an over-rotation protection logic module used for engine speed monitoring, and a logic module used to convert the FPGA internal Bus protocol conversion logic module for synchronous serial bus and external bus protocol. The invention uses n processors and multiple logic modules inside the FPGA to jointly control the aeroengine, and solves the problems of highly customized electronic controller software based on traditional processors, poor reusability, and difficult development of parallel real-time tasks.

Description

On-chip distributed aeroengine electronic controller and control method based on FPGA

technical field

The invention relates to an embedded electronic controller, in particular to an FPGA-based on-chip distributed aeroengine electronic controller and a control method.

Background technique

With the progress of science and technology, especially the rapid development of electronic technology and the improvement of modern control theory, the control system of aero-engine has also undergone fundamental changes, from the traditional mechanical hydraulic control system to the partial electronic control system to the current full-scale control system. Authority Digital Electronic Control (FADEC). The benefits brought by the use of FADEC are obvious, such as: larger control range, higher control accuracy, complex control laws, improved system reliability, and reduced volume and weight of the control system. At present, the FADEC system of aero-engine generally uses a centralized dual-channel redundant architecture, which is characterized by: highly customized system software and hardware, sensor signal acquisition, processing, redundancy management, control algorithm, control signal output, fault diagnosis, isolation And other tasks are completed by a single CPU, the disadvantages of this centralized control system are as follows:

(1) All tasks such as data acquisition, processing, and control algorithms are completed by a single CPU. The calculation tasks of this CPU are quite heavy, the complexity of the software increases sharply, and the reliability verification of the software system becomes very difficult.

(2) Software programs such as data acquisition, processing, redundancy management, control algorithms, and fault diagnosis running in a single CPU are highly correlated. After the design is finalized, any partial software modification may cause a large part of the system to Software re-verification, which makes the later upgrade and maintenance costs of the system increase sharply.

(3) All software programs are customized for specific engines, and the reusability is poor. When designing a new engine control system, all program modules must be rewritten and verified, which reduces development efficiency and increases development costs .

At present, aero-engine control is developing in the direction of multivariable, self-adaptive, intelligent, comprehensive, distributed, and high reliability. In order to reduce development costs and improve development efficiency, software and hardware are required to be highly modular and reusable. Distributed control systems are proposed to meet this demand. For example: Bhal Tulpule et al. at the 43rd AIAA/ The paper "Vision for Next Generation Modular Adaptive Generic Integrated Controls (MAGIC) For Military/Commercial Turbine Engines" on ASME/SAE/ASEE Joint Propulsion Conference&Exhibit and Jin Quan et al. The dissertation "Structure Analysis of Distributed Control System of Aero-Engine" provides the realization scheme of distributed control system of aero-engine. Compared with the centralized control system, the software and hardware of the distributed control system are highly modular and reusable, which will greatly improve the development efficiency and reduce the development and maintenance costs. However, the aeroengine distributed control system proposed by Bhal Tulpule and Huang Jinquan is limited to the development level of key technologies such as high-temperature electronic components and high-reliability buses, and is not yet ready for implementation.

SOPC (System On Programmable Chip) based on Field Programmable Gate Array (Field Programmable Gate Array), or a single-chip system based on large-scale FPGA represents the development direction of contemporary embedded systems. The design of SOPC Technology is a highly developed product of modern computer-aided design technology, EDA technology and large-scale integrated circuit technology. The goal of SOPC technology is to try to integrate as large and complete electronic systems as possible, including embedded processor systems, interface systems, hardware co-processing Accelerator or accelerator system, DSP system, digital communication system, storage circuit, and general digital system, etc., can be implemented in a single FPGA, so that the designed circuit system can improve the scale, reliability, volume, power consumption, function, performance index, and time to market. , development costs, product maintenance and hardware upgrades, etc. are optimized. Therefore, FPGA-based SOPC technology provides an efficient and high-performance solution for the design of aeroengine electronic controllers.

Contents of the invention

Purpose of the invention:

The purpose of the present invention is to solve the problems of highly customized software, high complexity, poor reusability, difficulty in developing parallel real-time tasks, and low development efficiency in the design of centralized aeroengine electronic controllers, and to provide an FPGA-based on-chip distributed Aeroengine electronic controller and control method.

Technical solutions:

The present invention adopts the following technical solutions for realizing the above-mentioned purpose of the invention:

The on-chip distributed aeroengine electronic controller based on FPGA of the present invention is composed of an input signal interface circuit, an FPGA chip, and an output signal interface circuit connected in sequence, and the inside of the FPGA chip includes a synchronous serial bus DB, a synchronous clock line CLK, The synchronous control line SC and the n processor modules interconnected through these three lines, the over-rotation protection logic module for real-time measurement of the speed of the aeroengine, the synchronous control logic module for controlling the synchronous work of each module inside the FPGA, and the conversion of the FPGA Bus protocol conversion logic module of internal synchronous serial bus and external bus protocol, where n represents the number of engine sensors and actuators, n is a natural number, 3<n<20.

In the FPGA-based on-chip distributed aeroengine electronic controller of the present invention, the n processors embedded in the FPGA operate independently, and each processor has a separate program space ROM and data space RAM. These n processors independently execute throttle lever command acquisition and processing, temperature signal acquisition and processing, pressure signal acquisition and processing, core control algorithm, main fuel volume small closed-loop control, afterburner fuel volume small closed-loop control, tail nozzle area Small closed-loop control and other tasks.

In the FPGA-based on-chip distributed aero-engine electronic controller of the present invention, the over-rotation protection logic module is used to measure the speed of the aero-engine in real time, and when the speed exceeds a safety limit, control the speed of the engine to stay away from the safety boundary according to a predetermined safety mode.

In the FPGA-based on-chip distributed aeroengine electronic controller of the present invention, the synchronous control logic module inside the FPGA chip is a configurable high-precision customizer, which controls n processors inside the FPGA chip through the synchronous control line SC The module, the overrun protection logic module, and the bus protocol conversion logic module operate synchronously according to the predetermined time interval T1, that is, the control step of the main loop.

In the FPGA-based on-chip distributed aeroengine electronic controller of the present invention, the bus protocol conversion logic module inside the FPGA chip is used for protocol conversion between the FPGA chip internal synchronous serial bus and the external bus, and the external bus is used for Communicate with engine redundant controller channel, flight control system.

In the FPGA-based on-chip distributed aeroengine electronic controller of the present invention, the n processors are used for processing the tasks of small closed-loop control of main fuel volume, small closed-loop control of afterburning fuel volume, and small closed-loop control of tail nozzle area The device also contains a high-precision customizer, whose timing interval T2 is 1/4 of the timing interval T1 of the synchronous control logic module.

In addition, the present invention also provides a control method based on an FPGA-based on-chip distributed aeroengine electronic controller. Whenever the synchronous control signal SC is valid, the n processor modules, the overrunning protection logic module, the The synchronous control logic module and the bus protocol conversion logic module complete the task of controlling the aeroengine according to the following steps, including the following steps:

a) The synchronous control logic repeatedly generates an effective synchronous control signal SC according to the preset time interval T1;

b) After detecting an effective synchronous control signal SC, each processor completes the acquisition and processing of the throttle lever signal;

c) After detecting the effective synchronous control signal SC, each processor completes the tasks of temperature and pressure signal acquisition, linearization, dimension conversion, fault diagnosis and isolation, etc.;

d) After detecting an effective synchronous control signal SC, the over-rotation protection logic module measures the current engine speed;

e) After detecting an effective synchronous control signal SC, the bus protocol conversion logic obtains atmospheric data information from the flight control system;

f) The throttle lever, pressure, temperature, rotational speed, and air data information collected above are sequentially sent to the core processing in charge of the core control algorithm through the synchronous serial bus DB.

g) The core processor calculates the output control quantities of the engine such as the main fuel quantity, afterburner fuel quantity and tail nozzle area according to the current engine speed, temperature, pressure, atmospheric data information and reference command of the throttle lever according to the predetermined control mode, And send these output control quantities to the synchronous serial bus DB;

h) Each processor used for small closed-loop control receives the control quantity output by the core processor through the synchronous serial bus DB, and completes the small closed-loop control of the main fuel flow, afterburner fuel flow, and tail nozzle area respectively according to the predetermined control mode control tasks.

Beneficial effect:

(1), complex tasks such as data acquisition, control algorithm, and small closed-loop control completed by a single processor in the centralized controller are jointly completed by a plurality of processors after adopting the present invention, which will reduce the complexity of the control software, Simplifies the development of parallel real-time software tasks and makes software verification relatively easy.

(2), the present invention decomposes the system control software according to functions such as data acquisition, control algorithm, small closed-loop control, is completed by independent processor respectively, and these several parts are relatively independent software modules, the development of these software modules It can be carried out by multiple software developers at the same time, which improves the development efficiency.

(3), the present invention decomposes the system control software according to functions such as data acquisition, control algorithm, small closed-loop control, respectively by independent processors, the modification of any software module does not affect other software modules, which will Reduce software maintenance and upgrade costs during use.

(4), software modules such as data collection of the present invention, small closed-loop control run on independent processors, and have little correlation with engine. When designing a new engine control system, these originally designed and verified software modules can be reused, which improves the development efficiency of the new system and reduces the development cost.

Description of drawings

Accompanying drawing 1 is the structure schematic diagram of on-chip distributed aeroengine electronic controller based on FPGA.

Accompanying drawing 2 is the schematic diagram of the numerical control system of twin-shaft turbojet engine based on the present invention.

Accompanying drawing 3 is a structural block diagram of a synchronous serial bus terminal.

Accompanying drawing 4 is the data frame structural diagram of synchronous serial bus.

Accompanying drawing 5 is a logical structural block diagram of bus protocol conversion.

Accompanying drawing 6 is the control flowchart of the on-chip distributed aeroengine electronic controller based on FPGA.

Detailed ways

The technical scheme of the present invention is described in detail below in conjunction with accompanying drawing:

Contrast the structure block diagram of the present invention shown in accompanying drawing 1, comprise input interface circuit 2, a slice FPGA1 and output interface circuit 3, wherein the design method of input signal interface circuit 2 and output number interface circuit 3 is the technical field well known to control system technicians , this embodiment only provides the design process of the distributed processing structure inside the FPGA and the control method of the controller, and the implementation steps of the present invention are given below.

A distributed aero-engine electronic controller in a chip based on FPGA, its completion comprises the following steps:

(1), Embed n independently running processors inside a FPGA, and customize the program storage space ROM and program running space RAM for each processor inside the FPGA, each processor has and synchronous serial bus DB , Synchronous clock CLK interface, can add PWM output, timer, general-purpose I/O and other peripherals to the processor according to requirements.

(2), adopt C language in processor 1 to realize functions such as signal acquisition, linearization, dimension conversion, fault diagnosis and isolation of engine inlet temperature; Adopt C language in processor 2 to realize the acquisition of low-pressure turbine outlet temperature signal , linearization, dimension conversion, fault diagnosis and isolation and other functions; use C language in processor 3 to realize the collection, linearization, dimension conversion, fault diagnosis and isolation and other functions of high pressure turbine outlet pressure signal; in processor 4 The reference signal of the throttle lever is converted into the reference state of the engine by programming in C language; the core control algorithm and some simple switch input and output functions are realized by C language in processor 5; the main control algorithm is realized by C language in processor 6 Closed-loop control of small fuel volume; use C language in processor 7 to realize small closed-loop control of afterburner fuel volume; use C language in processor 8 to realize small closed-loop control of tail nozzle area; above-mentioned processors 6, 7, 8 all A built-in high-precision customizer with a timing interval of T2 (small closed-loop control step size). Different types of engines and control modes have different requirements for sensors and actuators, and the number of processor cores that need to be customized is also different, which needs to be determined according to the actual situation.

(3) The synchronous serial bus is composed of a bidirectional data line DB and a synchronous clock line CLK, wherein the CLK signal is generated by the bus protocol conversion logic, and the period T3 can be configured by the user. When the bus is idle, the default state of DB is high level "1". Before any module sends data, first pull the DB line to low level "0", and last for T4 (T4>=10*T3) as the bus request signal, and at the same time Inform other modules that the bus is about to transfer data. The synchronous serial bus can only accept the data sending request of one module at any time, while other modules that have not sent data can receive the data on the bus, and the order of sending data of each module on the bus needs to be set in advance.

(4) The hardware description language VHDL/Verilog is adopted to implement the over-rotation protection logic inside the FPGA. The logic monitors the high-pressure compressor speed of the engine in real time. When the speed exceeds the safety limit, the logic module controls the engine to stay away from the safe speed limit according to the preset safety protection mode.

(5) Using the hardware description language VHDL/Verilog, the synchronous control logic is implemented inside the FPGA. This logic is a configurable high-precision customizer, which controls n processors inside the FPGA and overrun protection through the synchronous control signal line SC Logic, the bus protocol conversion logic operates synchronously according to the predetermined time interval T1 (main loop control step).

(6), using the hardware description language VHDL/Verilog to implement the bus protocol conversion logic inside the FPGA, this logic mainly realizes the protocol conversion between the serial synchronous bus DB inside the FPGA and the external bus, the external bus and the redundant control channel of the engine, the flight Control system communication.

(7), interconnect the above-mentioned customized n processor modules, synchronous control logic module, overrun protection logic module and bus protocol conversion logic module through synchronous serial bus DB and synchronous clock CLK in FPGA, and provide each module Assign a unique bus address.

Embodiment one:

This embodiment takes a certain type of turbojet engine digital control system as an example. Accompanying drawing 2 is a system block diagram, including a sensor, an FPGA-based on-chip distributed aeroengine electronic controller, an actuator, a fuel supply device, an oil pump and a controlled engine. The object of the twin-spool turbojet engine. The input parameters of the engine digital control system include: compressor inlet temperature T2, pressure P2, low pressure compressor speed N1, low pressure compressor outlet pressure P2.5, high pressure compressor speed Nh, high pressure compressor outlet pressure P3, low pressure turbine outlet Temperature T5, pressure P5, tail nozzle hydraulic cylinder displacement Lp1, position signal Lp2 reflecting main fuel flow, position signal Lp3 reflecting afterburner fuel flow, throttle lever position input. Output parameters include: main fuel quantity control signal qmf, afterburner fuel quantity control signal qm, faf, tail nozzle area control signal A8.

The detailed structure of the on-chip distributed aeroengine electronic controller based on FPGA in accompanying drawing 2 is as shown in accompanying drawing 1, comprises input signal interface circuit 2, a piece of FPGA based on SRAM architecture and supporting peripheral circuit, input signal interface circuit 3 . Wherein the design method of the input signal interface circuit 2, the output signal interface circuit 3, and the control mode of the engine, software programming etc. are all technical fields well-known to the control system technicians, and the present embodiment only provides the distributed processing structure inside the FPGA Design process and control method of this controller.

A kind of on-chip distributed aeroengine electronic controller based on FPGA, its implementation comprises the following steps:

(1) Embed n processors inside the FPGA.

The FPGA selected in this embodiment is the EP2C35F672C6 of the Cyclone II series based on the SRAM architecture of Altera Corporation. Based on the company's FPGA development software Quartus II and SOPC development platform SOPCBulider, according to the requirements of the control system of the biaxial turbojet engine of this embodiment, 11 NIOS II processors are embedded in EP2C35F672C6. NIOS II is an embedded soft-core processor, which is divided into fast type, economical type and standard type. The fast type pursues the highest performance, the economical type has the lowest resource usage, and the standard type balances performance and resource usage. In this embodiment, one fast NIOS II is used as the core processor to run the core control algorithm, three standard NIOS IIs are used for small closed-loop control, and seven economical NIOS IIs are used for throttle lever, pressure, and temperature signals. Collection and processing. The functions of these processors are:

Economical processor 1: This processor performs tasks such as signal acquisition, linearization, fault diagnosis, isolation, and dimension conversion of the compressor inlet temperature T2, and sends the collected effective data to the operating core through the synchronous serial bus DB Core processor 8 for control algorithm.

Economical processor 2: This processor performs tasks such as signal acquisition, linearization, fault diagnosis, isolation, and dimension conversion of the compressor inlet pressure P2, and sends the collected effective data to the operating core through the synchronous serial bus DB Core processor 8 for control algorithm.

Economical processor 3: This processor performs tasks such as signal acquisition, linearization, fault diagnosis, isolation, and dimension conversion of the outlet pressure P2.5 of the low-pressure compressor, and sends the collected effective data through the synchronous serial bus DB to the core processor 8 that runs the core control algorithm.

Economical processor 4: This processor performs tasks such as signal acquisition, linearization, fault diagnosis, isolation, and dimension conversion of the outlet pressure P3 of the high-pressure compressor, and sends the collected effective data to the operating system through the synchronous serial bus DB Core processor 8 for core control algorithm.

Economical processor 5: This processor performs tasks such as signal acquisition, linearization, fault diagnosis, isolation, and dimension conversion of the low-pressure turbine outlet temperature T5, and sends the collected effective data to the operating core through the synchronous serial bus DB Core processor 8 for control algorithm.

Economical processor 6: This processor performs tasks such as signal acquisition, linearization, fault diagnosis, isolation, and dimension conversion of the low-pressure turbine outlet pressure P5, and sends the collected effective data to the operating core through the synchronous serial bus DB The core processor of the control algorithm 8.

Economical processor 7: This processor performs tasks such as throttle lever signal acquisition and conversion, and sends the collected effective data to the core processor 8 that runs the core control algorithm through the synchronous serial bus DB.

Core processor 8: core processor 8 is a fast type NIOS II processor, and this processor receives engine temperature, pressure, rotating speed signal (measured by the overrunning protection logic in accompanying drawing 1) and by synchronous serial bus DB Throttle lever command, calculate and output main fuel quantity q _{m, f} , afterburner fuel quantity q _{m, faf} , tail nozzle area A ₈ according to the predetermined control mode (PID control algorithm, control step length is 20ms), and send these data to the synchronous serial bus DB.

Standard processor 9: This processor receives the main fuel flow command q _{m, f} issued by the core processor 8 on the synchronous serial bus DB as a reference input, and collects the displacement Lp2 representing the flow of the main fuel pump to form a local closed-loop control (PID control algorithm, control step size is 5ms), improve system stability and dynamic quality.

Standard processor 10: This processor receives the afterburner fuel flow command q _{m and faf} issued by the core processor 8 on the synchronous serial bus DB as a reference input, and collects the displacement Lp3 representing the flow rate of the afterburner fuel pump to form a local Closed-loop control (PID control algorithm, control step size is 5ms), improving system stability and dynamic quality.

Standard type processor 11: this processor receives on the synchronous serial bus DB the tail nozzle area control instruction A ₈ that is sent by the core processor 8 as a reference input, and adopts the displacement Lp1 representing the tail nozzle area to form a local closed-loop control ( PID control algorithm, control step length is 5ms), improve system stability and dynamic quality.

(2), customized synchronous serial bus interface

The synchronous serial bus interface block diagram shown in Figure 3 includes a bus terminal controller, a receiving FIFO, and a sending FIFO. The width of the two FIFOs is 16 bits, and the depth is 8. The frame format of the sent data is shown in Figure 4, and the data check adopts a simple sum check. When sending data, the bus terminal controller reads the data buffered in the sending FIFO, performs parallel/serial conversion, clock signal edge detection, and sends the data to the bus DB on the falling edge of the clock signal CLK. The bus terminal controller detects the edge of the clock signal CLK when receiving data, and reads the data on the data bus DB at the rising edge of CLK, performs serial/parallel conversion and puts it into the receiving buffer FIFO. This module is designed using the hardware description language Verilog. The design process is a technical field well-known to embedded system technicians, and will not be introduced in detail here.

(3), customized over-rotation protection logic

The over-rotation protection logic is used to monitor the low-pressure rotor, high-pressure rotor speed Nl and Nh of the engine. The principle is to use the system high-frequency clock (50Mhz) to detect the edge of the speed pulse signal sent by the speed sensor, and measure the difference between the two same edges. The time interval between, and then get the engine speed. When the module finds that the high-pressure rotor speed Nh exceeds the preset safety limit, it controls the engine to stay away from the speed safety boundary according to a predetermined safety mode. This module is designed using the hardware description language Verilog. The design process is a technical field well-known to embedded system technicians, and will not be introduced in detail here.

(4), customized synchronous control logic

The synchronous control logic is a high-precision timer that can be configured through the synchronous serial bus (DB). This logic divides the frequency of the system clock (50Mhz) to obtain a control step of 20ms for the control system. Every 20ms, the synchronous control logic sends a synchronous pulse signal to the 11 processor modules, the overrun protection logic module, and the bus protocol conversion logic module through the synchronous control signal line SC to control the synchronous work of each module. This module is designed using the hardware description language Verilog. The design process is a technical field well-known to embedded system technicians, and will not be introduced in detail here.

(5), custom bus conversion logic

The structural block diagram of the bus protocol conversion logic module as shown in accompanying drawing 5, this module realizes the protocol conversion from the internal serial synchronous bus to the external bus UART. This module adopts the hardware description language Verilog design, and the design process is familiar to embedded system technicians technical field, which will not be described in detail here.

(6), on-chip system interconnection

Finally, interconnect the above-mentioned 11 customized processor modules, overrun protection logic modules, synchronous control logic modules, and bus protocol conversion logic modules through the synchronous serial bus DB and the synchronous clock CLK, and assign a unique bus address to each module , to determine the order in which each module sends data on the bus, in order: processor 1, 2, 3, 4, 5, 6, 7, overrun protection logic sends speed information, bus protocol conversion logic sends atmospheric data information, processor 8 Send control volume.

A control method based on FPGA-based distributed aero-engine electronic controller on-chip, with reference to accompanying drawing 6, its implementation comprises the following steps:

(1) The synchronous control logic repeatedly generates an effective synchronous control signal SC according to a preset time interval of 20 ms;

(2) After detecting an effective synchronous control signal SC, the economical processor 7 completes the task of collecting and processing the throttle lever signal;

(3) After detecting the effective synchronous control signal SC, the economical processors 1, 2, 3, 4, 5, and 6 respectively complete the collection, linearization, dimension conversion, fault diagnosis and tasks such as isolation;

(4) After detecting an effective synchronous control signal SC, the over-rotation protection logic module measures the current engine speed;

(5) After detecting the effective synchronous control signal SC, the bus protocol conversion logic obtains the air data signal from the flight control system;

(6) The throttle lever, pressure, temperature, rotational speed, and air data information collected above are sent to the core processor 8 responsible for the core control algorithm through the synchronous serial bus DB in a preset order.

(7) The core processor 8 calculates the output of the engine's main fuel volume, afterburner fuel volume, and tail nozzle area according to the predetermined control mode according to the current engine speed, temperature, pressure, atmospheric data information and reference instructions of the throttle lever control quantity, and send these output control quantities to the synchronous serial bus DB;

(8) The standard processors 9, 10, and 11 used for small closed-loop control receive the control quantity output by the core processor 8 through the synchronous serial bus DB, and respectively complete the control of the main fuel flow and the afterburner fuel flow according to the predetermined control mode , The small closed-loop control task of the tail nozzle area.

The above 1, 2, 3, 4, 5, 6, 7, and 8 are control steps for a complete control step. Whenever the synchronous control signal SC is valid, the controller will follow the steps of 1, 2, 3, 4, 5, The steps described in 6, 7, and 8 complete the control task.

Claims (7)

1. a kind of in-chip distributed aviation engine electronic controller based on FPGA, is connected and formed by input signal interface circuit (2), FPGA chip (1), output signal interface circuit (3) successively, it is characterized in that: described FPGA The chip includes a synchronous serial bus (DB), a synchronous clock line (CLK), a synchronous control line (SC), and n processor modules interconnected through these three lines, and an over-rotation protection logic module for real-time measurement of the speed of the aeroengine 1. A synchronous control logic module for controlling the synchronous work of each module inside the FPGA, and a bus protocol conversion logic module for converting the synchronous serial bus inside the FPGA and the external bus protocol; wherein, n is a natural number, 3<n<20. 2. the on-chip distributed aeroengine electronic controller based on FPGA according to claim 1, is characterized in that: the n processors embedded in the FPGA operate independently, and each processor has a separate program space ROM and data space RAM; the n processors independently execute throttle lever command acquisition and processing, temperature signal acquisition and processing, pressure signal acquisition and processing, core control algorithm, main fuel volume small closed-loop control, afterburning fuel volume small closed-loop Control, tail nozzle area small closed-loop control and other tasks. 3. The on-chip distributed aero-engine electronic controller based on FPGA according to claim 1, characterized in that: the over-rotation protection logic module is used for real-time measurement of the aero-engine speed, and when the speed exceeds a safety limit, the predetermined The safe mode controls engine speed away from safe boundaries. 4. the on-chip distributed aeroengine electronic controller based on FPGA according to claim 1, is characterized in that: the synchronous control logic module inside the FPGA chip is a configurable high-precision customizer, through the synchronous control line (SC) controls the n processor modules, the overrun protection logic module, and the bus protocol conversion logic module inside the FPGA chip to run synchronously according to the predetermined time interval T1, that is, the main loop control step. 5. the on-chip distributed aeroengine electronic controller based on FPGA according to claim 1, is characterized in that: the bus protocol conversion logic module inside the FPGA chip is used for synchronous serial bus and external bus in the FPGA chip Between the protocol conversion, the external bus is used to communicate with the engine redundant controller channel and the flight control system. 6. the distributed aero-engine electronic controller based on FPGA according to claim 2, is characterized in that: the small closed-loop control of main fuel quantity, the small closed-loop control of afterburner fuel quantity, The processor of the closed-loop control task with small tail nozzle area also includes a high-precision customizer, and its timing interval T2 is 1/4 of the timing interval T1 of the synchronous control logic module. 7. A control method based on the FPGA-based on-chip distributed aero-engine electronic controller according to any one of claims 1 to 6, wherein: whenever the synchronous control signal SC is valid, the FPGA internal The n processor modules, the overrunning protection logic module, the synchronous control logic module and the bus protocol conversion logic module complete the control task of the aeroengine according to the following steps: a) The synchronous control logic repeatedly generates an effective synchronous control signal SC according to the preset time interval T1; b) After detecting an effective synchronous control signal SC, each processor completes the acquisition and processing of the throttle lever signal; c) After detecting the effective synchronous control signal SC, each processor completes the tasks of temperature and pressure signal acquisition, linearization, dimension conversion, fault diagnosis and isolation, etc.; d) After detecting an effective synchronous control signal SC, the over-rotation protection logic module measures the current engine speed; e) After detecting an effective synchronous control signal SC, the bus protocol conversion logic obtains atmospheric data information from the flight control system; f) The throttle lever signal, pressure signal, temperature signal, engine speed, and air data information collected above are sent to the processor responsible for the core control algorithm through the synchronous serial bus DB in sequence; g) The core processor calculates the output control quantities of the engine such as the main fuel quantity, afterburner fuel quantity and tail nozzle area according to the current engine speed, temperature, pressure, atmospheric data information and reference command of the throttle lever according to the predetermined control mode, And send these output control quantities to the synchronous serial bus DB; h) Each processor used for small closed-loop control receives the control quantity output by the core processor through the synchronous serial bus DB, and completes the small closed-loop control of the main fuel flow, afterburner fuel flow, and tail nozzle area respectively according to the predetermined control mode control tasks.

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