CN201526375U - On-chip distributed aircraft engine electronic controller based on FPGA - Google Patents
On-chip distributed aircraft engine electronic controller based on FPGA Download PDFInfo
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Abstract
The utility model provides an on-chip distributed aircraft engine electronic controller based on FPGA, belonging to the technical field of engine control. The on-chip distributed aircraft engine electronic controller based on FPGA comprises an input signal interface circuit (2), an FGPA chip (1) and an output signal interface circuit (3), the inside of the FPGA chip comprises a synchronous serial bus DB, a synchronous clock line CLK, a synchronous control line SC, n processor modules, a synchronous control logic module, an overturn protection logic module and a bus protocol conversion logic module, wherein the n processor modules are connected mutually via the synchronous serial bus DB, the synchronous clock line CLK and the synchronous control line SC, each processor module is provided with an independent data space RAM and a program space ROM, the synchronous control logic module is used for controlling synchronous work of all the modules in the FPGA, the overturn protection logic module is used for monitoring rotation speed of engines, and the bus protocol conversion logic module is used for realizing conversion between the synchronous serial bus inside the FPGA and an external bus protocol. By utilizing the n processors and the logic modules inside the FPGA to complete controlling aircraft engines together, the on-chip distributed aircraft engine electronic controller based on FPGA resolves the problems that the electronic controller software based on the conventional processors requires high degree of custom-made, and is poor in reusability and difficult to develop parallel real-time task.
Description
Technical field
The utility model relates to a kind of embedded electronic controller, a kind of specifically distributed aeroengine electronic controller in chip based on FPGA.
Background technique
Along with progress of science and technology, especially developing rapidly of electronic technology and being gradually improved of modern control theory, the control system of aeroengine has also produced basic change, develops into the portions of electronics control system up to present full powers limit digital and electronic formula controls (FADEC) from traditional machinery hydraulic pressure control system.The benefit that adopts FADEC to bring is significantly, and for example: control range becomes big, control accuracy improves, can realize complicated control law, improved the reliability of system, simultaneously the volume of control system reduce, weight saving.What the FADEC system of current aeroengine generally used is centralized Twin channel redundancy structure, be characterized in: system is soft, the customization of hardware height, tasks such as collecting sensor signal, processing, Redundancy Management, control algorithm, control signal output, fault diagnosis, isolation are all finished by single CPU, and the shortcoming of this Centralized Control System is as follows:
(1), all tasks such as data capture, processing, control algorithm all have single CPU to finish, the calculation task of this CPU is quite heavy, software complexity sharply increases, the reliability demonstration of the software systems very difficulty that becomes.
Be highly related between the software programs such as the data capture that (2), in single CPU, moves, processing, Redundancy Management, control algorithm, fault diagnosis, behind the design typification, local arbitrarily software modification all may cause the checking again of systems soft ware greatly, and this makes the upgrading in system's later stage, maintenance cost sharply increase.
(3), all software programs all are that reusability is poor at the customization of specific motor, when the new engine control system of design, all program modules must write again, verify that this has reduced development efficiency, have increased development cost.
At present aeroengine control just develops towards directions such as multivariable, self adaption, intellectuality, synthesization, distributed, high reliability.In order to reduce development cost, to improve development efficiency, require soft, hardware to have the modularization and the reusability of height, distributed control system proposes in order to satisfy this demand just, and for example: people such as Bhal Tulpule are at the 43rd AIAA/ASME/SAE/ASEE Joint Propulsion Conference ﹠amp; The paper " aeroengine distributed control system structural analysis " of people such as paper on the Exhibit " Vision for Next Generation Modular Adaptive Generic Integrated Controls (MAGIC) For Military/Commercial Turbine Engines " and gold spring on " aviation power journal " the 18th the 5th phase of volume all provided the implementation of aeroengine distributed control system.With respect to Centralized Control System, soft, the hardware of distributed control system has the modularization and the reusability of height, and this will improve development efficiency greatly, reduces exploitation, maintenance cost.But the boat motor distributed control system that Bhal Tulpule and gold spring provide is limited to the development level of key technologies such as high-temperature electronic components and parts, highly reliable bus, does not also possess the condition of enforcement at present.
Based on the programmable system on chip SOPC (System On Programmable Chip) of on-site programmable gate array FPGA (Field Programmable Gate Array), represented the developing direction of contemporary embedded system in other words conj.or perhaps based on the monolithic system of large-scale F PGA.The designing technique of SOPC is the product of modern computer aided design techniques, EDA technology and the development of large-scale integrated circuit (LSI) technology height.The target of SOPC technology is exactly the electronics of attempting big and complete as far as possible, comprise embedded processor system, interface system, hardware co-processor or accelerator system, dsp system, digital communications, memory circuit and ordinary numbers system etc., in single FPGA, realize, make designed circuitry in many-sided optimization that realizes such as scale, reliability, volume, power consumption, function, performance index, listing cycle, development cost, product maintenance and HardwareUpgring thereof.Therefore, provide a kind of efficient, high performance solution based on the SOPC technology of FPGA for the design of aeroengine electronic controller.
The model utility content
The model utility purpose:
The purpose of this utility model is the software height customization when solving centralized aeroengine electronic controller design, problem such as complexity is big, reusability is poor, parallel real-time task exploitation difficulty, development efficiency are low, and a kind of distributed aeroengine electronic controller in chip based on FPGA is provided.
Technological scheme:
The utility model is for realizing above-mentioned model utility purpose by the following technical solutions:
Distributed aeroengine electronic controller in chip based on FPGA of the present utility model; by input signal interface circuits; fpga chip; interface circuit of output signal connects to form successively; described fpga chip inside comprises synchronous serial bus DB; synchronised clock line CLK; train line SC reaches by n interconnected processor module of these three lines; be used for measuring in real time the excess revolutions protection logic module of aeroengine rotating speed; be used to control the synchronization control logic module of inner each module synchronous working of FPGA; be used to change the bus protocol conversion logic of inner synchronous serial bus of FPGA and external bus protocol; wherein n represents the quantity of engine sensor and actuator; n is a natural number, 3＜n＜20.。
Distributed aeroengine electronic controller in chip based on FPGA of the present utility model, inner n the processor that embeds of FPGA is independent operating, each processor all has independent program space ROM and data space RAM.This n processor independently carried out tasks such as throttle lever instruction acquisition and processing, temperature signal collection and processing, pressure signal collection and processing, core control algorithm, the little closed loop control of main fuel amount, the little closed loop control of afterburning amount of fuel, the little closed loop control of jet pipe area respectively.
Distributed aeroengine electronic controller in chip based on FPGA of the present utility model; described excess revolutions protection logic module is used for measuring in real time the aeroengine rotating speed; when rotating speed surpasses security limitations, control engine speed away from secure border according to the predetermined safe pattern.
Distributed aeroengine electronic controller in chip based on FPGA of the present utility model; the synchronization control logic module of described fpga chip inside is a highi degree of accuracy customization device that can dispose; n processor module, excess revolutions by train line SC control fpga chip inside protect logic module, bus protocol conversion logic according to preset time interval T 1, i.e. the synchronous operation of major loop control step-length.
Distributed aeroengine electronic controller in chip based on FPGA of the present utility model, the bus protocol conversion logic of described fpga chip inside is used for the protocol conversion between inner synchronous serial bus of fpga chip and the external bus, and external bus is used for communicating with motor redundant manipulator passage, flight control system.
Distributed aeroengine electronic controller in chip based on FPGA of the present utility model, be used for the little closed loop control of main fuel amount, the little closed loop control of afterburning amount of fuel, the little closed loop control task handling of jet pipe area device inside in the described n processor and also comprise a highi degree of accuracy customization device, its fixed time interval T2 is 1/4 of synchronization control logic module fixed time interval T1.
Beneficial effect:
(1), complex tasks such as the data capture of in centralized controller, finishing, control algorithm, little closed loop control by single processor, finish jointly by a plurality of processors after adopting the utility model, this will reduce control software complexity, simplified the exploitation of parallel real-time software task, and make software verification become relatively easy.
(2), the utility model decomposes according to functions such as data capture, control algorithm, little closed loop controls system controlling software, finish by separate processor respectively, and these several parts are relatively independent software modules, the exploitation of these software modules can be carried out simultaneously by a plurality of software developers, has improved development efficiency.
(3), the utility model decomposes according to functions such as data capture, control algorithm, little closed loop controls system controlling software, carry out by separate processor respectively, modification to any one software module does not influence other software modules, and this will reduce software maintenance, upgrade cost in the using process.
(4), software modules such as data capture of the present utility model, little closed loop control move on separate processor, and and the motor coherence little.When the new engine control system of design, these original designs, can reuse through software modules of checking, improved new system development efficiency, reduced development cost.
Description of drawings
Accompanying drawing 1 is based on the distributed aeroengine electronic controller in chip structural representation of FPGA.
Accompanying drawing 2 is based on twin shaft turbojet engine numerical control system schematic diagram of the present utility model.
Accompanying drawing 3 is synchronous serial bus terminal structure block diagrams.
Accompanying drawing 4 is data frame structure figure of synchronous serial bus.
Accompanying drawing 5 is bus protocol conversion logic structured flowcharts.
Accompanying drawing 6 is based on the control flow chart of the distributed aeroengine electronic controller in chip of FPGA.
Embodiment
Below in conjunction with accompanying drawing the technical solution of the utility model is elaborated:
The utility model structured flowchart shown in the contrast accompanying drawing 1, comprise input interface circuit 2, a slice FPGA1 and output interface circuit 3, wherein the design method of input signal interface circuits 2 and output interface circuit 3 is technical fields that the control system technician knows, present embodiment only provides the design process of distributed processing structure of FPGA inside and the controlling method of this controller, provides performing step of the present utility model below.
A kind of distributed aeroengine electronic controller in chip based on FPGA, it is finished is may further comprise the steps:
(1), at the inner processor that embeds n independent operating of a slice FPGA, and distinguish custom program storage space ROM and program running space RAM for each processor in that FPGA is inner, each processor all has the interface with synchronous serial bus DB, synchronised clock CLK, can add peripheral hardwares such as PWM output, timer, general purpose I/O according to demand for processor.
(2), in processor 1, adopt the C language to realize the functions such as signals collecting, linearization, dimension conversion, fault diagnosis and isolation of engine intake temperature; In processor 2, adopt the C language to realize the functions such as collection, linearization, dimension conversion, fault diagnosis and isolation of low-pressure turbine outlet temperature signal; In processor 3, adopt the C language to realize the functions such as collection, linearization, dimension conversion, fault diagnosis and isolation of high-pressure turbine outlet pressure signal; In processor 4, adopt the C Programming with Pascal Language throttle lever reference signal to be converted to the reference state of motor; In processor 5, adopt the C language to realize the simple switching value input of core control algorithm and some, output function; In processor 6, adopt the C language to realize the little closed loop control of main fuel amount; In processor 7, adopt the C language to realize the little closed loop control of afterburning amount of fuel; In processor 8, adopt the C language to realize the little closed loop control of jet pipe area; An all built-in fixed time interval is the highi degree of accuracy customization device of T2 (the control step-length of little closed loop) in the above-mentioned processor 6,7,8.Dissimilar motors and control mode have nothing in common with each other to the requirement of sensor, actuator, need the number of the processor core of customization also just to have nothing in common with each other, and need to determine according to actual conditions.
(3), synchronous serial bus is made up of bidirectional data line DB and synchronised clock line CLK, wherein the CLK signal is produced by the bus protocol conversion logic, the cycle is that T3 can be disposed by the user.The DB default conditions were high level " 1 " when bus was idle, at first the DB line is drawn before any module transmission data to be low level " 0 ", and duration T 4 (T4＞=10*T3) as bus request signal, inform that simultaneously other module bus will transmit data.Synchronous serial bus can only be accepted the data sending request of a module at any time, and other module that does not send data can receive the data on the bus, and the order of each module transmission data need preestablish on the bus.
(4), adopt Hardware Description Language VHDL/Verilog, in the inner excess revolutions protection logic that realizes of FPGA.This logic is monitored the high-pressure compressor rotating speed of motor in real time, and when rotating speed surpassed security limitations, this logic module was controlled motor away from the safe speed of rotation border according to default safety protection pattern.
(5), adopt Hardware Description Language VHDL/Verilog; in the inner synchronization control logic that realizes of FPGA; this logic is a highi degree of accuracy customization device that can dispose; by n processor, the excess revolutions protection logic of synchronous control signal line SC control FPGA inside, the bus protocol conversion logic is according to preset time interval T 1 (major loop control step-length) synchronous operation.
(6), adopt Hardware Description Language VHDL/Verilog at FPGA, the inner bus protocol conversion logic of realizing, this logic mainly realizes the serial synchronous bus DB of FPGA inside and the protocol conversion of external bus, and external bus is communicated by letter with motor Redundant Control passage, flight control system.
(7), in FPGA inside that n processor module of above-mentioned customization, synchronization control logic module, excess revolutions protection logic module and bus protocol conversion logic is interconnected by synchronous serial bus DB and synchronised clock CLK, and be the unique bus address of each module assignment.
Embodiment one:
Present embodiment is an example with certain type turbojet engine numerical control system, accompanying drawing 2 is a system block diagram, comprises sensor, the distributed aeroengine electronic controller in chip based on FPGA, actuator, oil supplying device, oil pump and as the double-compound turbo jet of controlled device.The input parameter of this motor numerical control system comprises: compressor inlet temperature T 2, pressure P 2, low pressure compressor rotational speed N l, low pressure compressor outlet pressure P2.5, high-pressure compressor rotational speed N h, high-pressure compressor outlet pressure P3, low-pressure turbine outlet temperature T5, pressure P 5, jet pipe hydraulic actuator displacement Lp1, the position signal Lp2 of reflection main fuel flow reflects the position signal Lp3 of afterburning fuel flow, the input of throttle lever position.Output parameter comprises: main fuel amount control signal qmf, afterburning amount of fuel control signal qm, faf, jet nozzle area control signal A8.
In the accompanying drawing 2 based on the detailed structure of the distributed aeroengine electronic controller in chip of FPGA as shown in Figure 1, comprise that input signal interface circuits 2, a slice are based on the FPGA of SRAM framework and supporting peripheral circuit, input signal interface circuits 3.The design method of input signal interface circuits 2, interface circuit of output signal 3 wherein, and the control mode of motor, software programming etc. all are the technical fields that the control system technician knows, and present embodiment only provides the design process of distributed processing structure of FPGA inside and the controlling method of this controller.
A kind of distributed aeroengine electronic controller in chip based on FPGA, its enforcement is may further comprise the steps:
(1), at n processor of the inner embedding of FPGA.
The FPGA that present embodiment is selected for use is the EP2C35F672C6 based on the Cyclone II series of SRAM framework of altera corp.Based on develop software Quartus II and the SOPC development platform SOPCBulider of the FPGA of the said firm, the control system demand according to the double-compound turbo jet of present embodiment has embedded 11 NIOS II processors in EP2C35F672C6.NIOS II is a kind of embedded soft-core processor, is divided into quick type, Economy and standard type.Type is pursued the highest performance fast, and economical have minimum resource occupation, and standard type has been done a balance between performance and resource occupation.Present embodiment selects for use 1 rakish NIOS II as core processor operation core control algorithm, and the NIOS II of 3 standard types is used for little closed loop control, and 7 Eco-power NIOS II are used for throttle lever, pressure, selection of temperature signal and processing.The function of these processors is respectively:
Economical processor 1: this processor is carried out tasks such as the signals collecting, linearization, fault diagnosis, isolation, dimension conversion of compressor inlet temperature T 2, and the valid data that collect is sent to the core processor 8 of operation core control algorithm by synchronous serial bus DB.
Economical processor 2: this processor is carried out tasks such as the signals collecting, linearization, fault diagnosis, isolation, dimension conversion of compressor intake pressure P2, and the valid data that collect is sent to the core processor 8 of operation core control algorithm by synchronous serial bus DB.
Economical processor 3: this processor is carried out tasks such as the signals collecting, linearization, fault diagnosis, isolation, dimension conversion of low pressure compressor outlet pressure P2.5, and the valid data that collect is sent to the core processor 8 of operation core control algorithm by synchronous serial bus DB.
Economical processor 4: this processor is carried out tasks such as the signals collecting, linearization, fault diagnosis, isolation, dimension conversion of high-pressure compressor outlet pressure P3, and the valid data that collect is sent to the core processor 8 of operation core control algorithm by synchronous serial bus DB.
Economical processor 5: this processor is carried out tasks such as the signals collecting, linearization, fault diagnosis, isolation, dimension conversion of low-pressure turbine outlet temperature T5, and the valid data that collect is sent to the core processor 8 of operation core control algorithm by synchronous serial bus DB.
Economical processor 6: this processor is carried out tasks such as the signals collecting, linearization, fault diagnosis, isolation, dimension conversion of low-pressure turbine outlet pressure P5, and the valid data that collect is sent to the core processor 8 of operation core control algorithm by synchronous serial bus DB.
Economical processor 7: this processor is carried out tasks such as throttle lever signals collecting and conversion, and the valid data that collect is sent to the core processor 8 of operation core control algorithm by synchronous serial bus DB.
Core processor 8: core processor 8 is rakish NIOS II processors; this processor receives engine temperature, pressure, tach signal (being measured by the protection of the excess revolutions in the accompanying drawing 1 logic) and throttle lever instruction by synchronous serial bus DB, calculates output main fuel amount q according to expectant control pattern (pid control algorithm, control step-length are 20ms)
M, f, afterburning amount of fuel q
M, faf, the jet nozzle area A
8, and these data are sent on the synchronous serial bus DB.
Standard type processor 9: this processor receives the main fuel flow instruction q that is sent by core processor 8 on synchronous serial bus DB
M, fAs the reference input, and the displacement Lp2 of collection sign main fuel pump flow forms local closed loop control (pid control algorithm, the control step-length is 5ms), the raising stability of a system and dynamic quality.
Standard type processor 10: this processor receives the afterburning fuel flow instruction q that is sent by core processor 8 on synchronous serial bus DB
M, fafAs the reference input, and the displacement Lp3 of the afterburning fuel pump flow of collection sign forms local closed loop control (pid control algorithm, the control step-length is 5ms), the raising stability of a system and dynamic quality.
Standard type processor 11: this processor receives the jet nozzle area control command A that is sent by core processor 8 on synchronous serial bus DB
8As with reference to input, and adopt the displacement amount Lp1 that characterizes the jet nozzle area and form local closed loop control (pid control algorithm, control step-length is 5ms), the raising stability of a system and dynamic quality.
(2), customization synchronous serial bus interface
Synchronous serial bus interface block diagram as shown in Figure 3 comprises the bus termination controller, receives FIFO, sends FIFO, and the width of two FIFO is 16, and the degree of depth is 8.Shown in the frame format accompanying drawing 4 of transmission data, data check adopts simple sum check.The bus termination controller reads when sending data and sends the FIFO data in buffer, and carry out parallel/serial conversion, clock edges detects, at the trailing edge of clock signal clk data are sent on the bus DB.The bus termination controller detects the edge of clock signal clk when receiving data, and the data on the rising edge readout data bus DB of CLK, carries out putting into reception buffer memory FIFO after the serial/parallel conversion.This module adopts hardware description language Verilog design, and design process is the technical field that the embedded system technology personnel know, and is not described in detail here.
(3), customization excess revolutions protection logic
Excess revolutions protection logic is used to monitor low pressure rotor, high pressure rotor rotational speed N l and the Nh of motor; its principle is that the rotational speed pulse signal that adopts system high-frequency clock (50Mhz) that speed probe is sent carries out the edge detection; and measure two same edge edges between the time lag, and then obtain engine speed.When this module finds that high pressure rotor rotational speed N h surpasses default security limitations, control motor away from the rotating speed secure border according to the predetermined safe pattern.This module adopts hardware description language Verilog design, and design process is the technical field that the embedded system technology personnel know, and is not described in detail here.
(4), customization synchronization control logic
The synchronization control logic is a high-resolution timer that can pass through synchronous serial bus (DB) configuration, and this logic is carried out frequency division to system clock (50Mhz), the control step-length 20ms of controlled system.Send synchronous working that a synchronization pulse control each module by synchronous control signal line SC to 11 processor modules, excess revolutions protection logic module, bus protocol conversion logic every 20ms synchronization control logic.This module adopts hardware description language Verilog design, and design process is the technical field that the embedded system technology personnel know, and is not described in detail here.
(5), customization bus conversion logic
The structured flowchart of bus protocol conversion logic as shown in Figure 5, this module are realized the protocol conversion of inner serial synchronous bus to external bus UART.This module adopts hardware description language Verilog design, and design process is the technical field that the embedded system technology personnel know, and is not described in detail here.
(6), system interconnection in the sheet
At last, 11 processor modules, excess revolutions protection logic module, synchronization control logic module, the bus protocol conversion logic of above-mentioned customization is interconnected by synchronous serial bus DB and synchronised clock CLK, and be the unique bus address of each module assignment; determine that each module sends the order of data on bus, be: processor 1,2 successively; 3; 4,5,6; 7; excess revolutions protection logic sends rotary speed information, and the bus protocol conversion logic sends atmosphere data information, and processor 8 sends controlled quentity controlled variable.
As shown in Figure 6, the job step of electronic controller of the present utility model is as follows:
(1) the synchronization control logic repeats to produce efficient synchronization control signal SC according to default time lag 20ms;
(2) detect efficient synchronization control signal SC after, economical processor 7 is finished the collection and the Processing tasks of throttle lever signal;
(3) detect efficient synchronization control signal SC after, economical processor 1,2,3,4,5,6 is finished the tasks such as collection, linearization, dimension conversion, fault diagnosis and isolation of each section temperature of motor, pressure signal respectively;
(4) detect efficient synchronization control signal SC after, excess revolutions protection logic module is measured the present engine rotating speed;
(5) detect efficient synchronization control signal SC after, the bus protocol conversion logic obtains the atmosphere data letter from flight control system;
(6) the above-mentioned throttle lever that collects, pressure, temperature, rotating speed, atmosphere data information send to the core processor 8 of being responsible for the core control algorithm according to default order by synchronous serial bus DB.
(7) core type processor 8 is according to rotating speed, temperature, pressure, atmosphere data information and the throttle lever reference instruction of present engine, assess the output controlled quentity controlled variables such as main fuel amount, afterburning amount of fuel and jet nozzle area of calculating motor according to the expectant control pattern, and these output controlled quentity controlled variables are sent on the synchronous serial bus DB;
(8) the standard type processor 9,10,11 that is used for little closed loop control receives the controlled quentity controlled variable of core processor 8 outputs by synchronous serial bus DB, finishes little closed loop control task to main fuel flow, afterburning fuel flow, jet pipe area respectively according to the expectant control pattern.
Above-mentioned 1,2,3,4,5,6,7,8 is control step of a complete control step-length, and when synchronous control signal SC was effective, controller was all finished control task according to 1,2,3,4,5,6,7,8 steps of describing.
Claims (6)
1. distributed aeroengine electronic controller in chip based on FPGA, by input signal interface circuits (2), fpga chip (1), interface circuit of output signal (3) connects to form successively, it is characterized in that: described fpga chip inside comprises synchronous serial bus (DB), synchronised clock line (CLK), train line (SC) reaches by n interconnected processor module of these three lines, be used for measuring in real time the excess revolutions protection logic module of aeroengine rotating speed, be used to control the synchronization control logic module of inner each module synchronous working of FPGA, be used to change the bus protocol conversion logic of inner synchronous serial bus of FPGA and external bus protocol; Wherein, n is a natural number, 3＜n＜20.
2. the distributed aeroengine electronic controller in chip based on FPGA according to claim 1 is characterized in that: inner n the processor that embeds of FPGA is independent operating, and each processor all has independent program space ROM and data space RAM; Described n processor independently carried out tasks such as throttle lever instruction acquisition and processing, temperature signal collection and processing, pressure signal collection and processing, core control algorithm, the little closed loop control of main fuel amount, the little closed loop control of afterburning amount of fuel, the little closed loop control of jet pipe area respectively.
3. the distributed aeroengine electronic controller in chip based on FPGA according to claim 1; it is characterized in that: described excess revolutions protection logic module is used for measuring in real time the aeroengine rotating speed; when rotating speed surpasses security limitations, control engine speed away from secure border according to the predetermined safe pattern.
4. the distributed aeroengine electronic controller in chip based on FPGA according to claim 1; it is characterized in that: the synchronization control logic module of described fpga chip inside is a highi degree of accuracy customization device that can dispose; n processor module, excess revolutions by train line (SC) control fpga chip inside protect logic module, bus protocol conversion logic according to preset time interval T 1, i.e. the synchronous operation of major loop control step-length.
5. the distributed aeroengine electronic controller in chip based on FPGA according to claim 1, it is characterized in that: the bus protocol conversion logic of described fpga chip inside is used for the protocol conversion between inner synchronous serial bus of fpga chip and the external bus, and external bus is used for communicating with motor redundant manipulator passage, flight control system.
6. the distributed aeroengine electronic controller in chip based on FPGA according to claim 2, it is characterized in that: be used for the little closed loop control of main fuel amount, the little closed loop control of afterburning amount of fuel, the little closed loop control task handling of jet pipe area device inside in the described n processor and also comprise a highi degree of accuracy customization device, its fixed time interval T2 is 1/4 of synchronization control logic module fixed time interval T1.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101705872B (en) * | 2009-11-10 | 2011-11-30 | 南京航空航天大学 | FPGA-based distributed aeroengine electronic controller in chip and control method |
| CN103946822A (en) * | 2011-09-30 | 2014-07-23 | 英特尔公司 | Mechanism for facilitating customization of multipurpose interconnect agents at computing devices |
| CN108603444A (en) * | 2016-01-29 | 2018-09-28 | 赛峰动力设备公司 | The electronic control system of partial redundance |
| US10248430B2 (en) | 2016-12-16 | 2019-04-02 | Hamilton Sundstrand Corporation | Runtime reconfigurable dissimilar processing platform |
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- 2009-11-10 CN CN2009202568979U patent/CN201526375U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101705872B (en) * | 2009-11-10 | 2011-11-30 | 南京航空航天大学 | FPGA-based distributed aeroengine electronic controller in chip and control method |
| CN103946822A (en) * | 2011-09-30 | 2014-07-23 | 英特尔公司 | Mechanism for facilitating customization of multipurpose interconnect agents at computing devices |
| US9361257B2 (en) | 2011-09-30 | 2016-06-07 | Intel Corporation | Mechanism for facilitating customization of multipurpose interconnect agents at computing devices |
| CN103946822B (en) * | 2011-09-30 | 2016-11-09 | 英特尔公司 | For promoting the mechanism of multipurpose interconnection agency at computing device for the customization |
| CN108603444A (en) * | 2016-01-29 | 2018-09-28 | 赛峰动力设备公司 | The electronic control system of partial redundance |
| CN108603444B (en) * | 2016-01-29 | 2020-10-30 | 赛峰动力设备公司 | Partially redundant electronic control system |
| US10248430B2 (en) | 2016-12-16 | 2019-04-02 | Hamilton Sundstrand Corporation | Runtime reconfigurable dissimilar processing platform |
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