CN101702328A - 3d memory and operation method thereof - Google Patents
3d memory and operation method thereof Download PDFInfo
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- CN101702328A CN101702328A CN200910206679A CN200910206679A CN101702328A CN 101702328 A CN101702328 A CN 101702328A CN 200910206679 A CN200910206679 A CN 200910206679A CN 200910206679 A CN200910206679 A CN 200910206679A CN 101702328 A CN101702328 A CN 101702328A
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Abstract
A 3D memory constituted by multiple layer memories. Each layer of memory includes m word lines, n bit lines and a plurality of initial switch layers, where m, n are natural numbers. The initial switch layer consists of Chalcogenide material. Two initial switches C[i, j +1] and C[i +1, j] are provided in a region surrounded by the word line i, the word line i +1 and the bit line j, the bit line j +1; and no initial switch is provided in a region surrounded by the word line i +1, the word line i +2 and the bit line j, and the bit line j +1, wherein i is odd and 1<=i<=m-1; j is a natural number and j is in a range from 1 to n-1, the initial switch layer C[i, j +1] denotes an initial switch connecting the word line i and the bit line j +1, and the initial switch layer C[i +1, j] denotes an initial switch connecting the word line i +1 and the bit line j. Each initial switch constitutes a memory core along with the connected word line and the connected bit line.
Description
The present invention is an original applying number 200510105365.1, and the applying date is on September 23rd, 2005, and denomination of invention is divided an application for " chalcogenide memory "
Technical field
The invention relates to a kind of storage unit, and particularly relevant for a kind of 3 d memory and method of operating thereof that does not need access transistor (access transistor).
Background technology
Typical storage element comprises a director element (steering element), and it for example is one or more transistors (transistor is electric crystal, below all be called transistor), is used for each storage element of access (access).This access transistor also can be diode (diode is diode, below all be called diode), and it provides the word line (word line) of the bit line (bit line) of access storage element.Especially in order to read and write the data of storage element, this access transistor can serve as and be used for word line to the logical lock (pass gate) of the access of bit line.For example, dynamic randon access reservoir (DRAM), fast flash memory (flash memory), static random-access reservoir (SRAM), traditional chalcogenide (chalcogenide) reservoir, European memory body (ovonic unifiedmemory, OUM) or the phase-change random access reservoir (phase-change random accessmemory PCRAM) needs transistor or PN diode as director element or addressed elements (addressing element).In DRAM, this director element is that transistor and data are to be stored in the capacitor.Similar ground then needs six transistors in SRAM.But making transistor needs high-quality silicon, and when making transistor on Silicon Wafer, can produce some problems.Therefore, on Silicon Wafer, make and have transistorized three-dimensional (three dimensional, 3D) reservoir is inconvenient.
Feasible solution is to use polysilicon p-n to engage (p-n junction) with the reservoir as director element.Yet this method has certain defective.For example, the type of these reservoirs mostly is confined to disposable programmable reservoir (one time programmable memory, and this method needs high programming voltage (programming voltage) and high process temperatures (process temperature) OTP).This high process temperatures will hinder the use of aluminium (Al) and copper (Cu) metal wire.For example, the highest process temperatures of aluminium is 500 ℃, and the process temperatures scope of copper is about 400～500 ℃.Because aluminium and copper are the interlayer distribution metals of using always, will make the interlayer distribution become difficult more so get rid of these two kinds of metals.In addition, when making three-dimensional reservoir by encapsulation technology, it is very difficult that the combination calibration (bonding alignment) of interlayer will become.Based on aforementioned viewpoint, so need a kind of storage element structure that can select access kernel storage element without access transistor.
Summary of the invention
The present invention is by using initialize switch material (threshold-switching material), its function of carrying out director element able to programme, and needn't can be used as the access transistor of the director element of access one reservoir kernel unit.
The present invention provides a kind of three-dimensional reservoir (3D memory) to be made of the multilayer reservoir again.Each layer reservoir comprises m bar word line, n bit lines and most initialize switch layer.M wherein, n is a natural number.The initialize switch layer is made of chalcogenide material.In the zone that word line i, word line i+1 and bit line j, bit line j+1 are enclosed, two initialize switch layer C are arranged
I, j+1And C
I+1, j, and in the zone that word line i+1, word line i+2 and bit line j, bit line j+1 are enclosed no initialize switch layer.Wherein, i is odd number and 1≤i≤m-1; J is natural number and j=1～n-1; Above-mentioned initialize switch layer C
I, j+1Expression connects the initialize switch layer of word line i and bit line j+1; And above-mentioned initialize switch layer C
I+1, jExpression connects the initialize switch layer of word line i+1 and bit line j.Each initialize switch layer constitutes a reservoir kernel with word line that is connected and the bit line that is connected.Each reservoir kernel has first starting potential of a low voltage value and second starting potential of a high-voltage value, this first starting potential is corresponding to one first storing state of this initialize switch layer, and this second starting potential is corresponding to one second storing state of this reservoir.When the magnitude of voltage between this word line and this bit line is this first starting potential, this initialize switch layer is by gating and be in this first storing state, when the magnitude of voltage between this word line and this bit line is this second starting potential, this initialize switch layer is by gating and be in this second storing state, when this word line and bit line were floated, this initialize switch layer was in non-strobe state.
The present invention provide in addition a kind of in above-mentioned three-dimensional reservoir the method for access reservoir kernel, and this method comprises following several steps.At first, decision is used for wherein one starting potential of the above-mentioned reservoir kernel of access.Then, an initial switching material of this reservoir kernel of programming is so that can be at access reservoir kernel under the starting potential.Next, on the word line that is communicated with (communication) with the reservoir kernel, apply a voltage, if when this voltage equals this starting potential at least, can access reservoir kernel.
The present invention provides a kind of method that reads above-mentioned three-dimensional reservoir (3D chalcogenide memory) element again, comprises following several steps.At first, apply one and read voltage in a word line.This reads voltage can be in order to the reservoir kernel of the corresponding selected word line of direct access.Then, with the word line corresponding bit line on apply a zero-bias.Next, read the numerical value that is stored in the reservoir kernel.
Anyly know skill person of the present invention and can know clearly that all the present invention can be applied to many reservoir/solid state devices (solid state device).An advantage that is showing of this reservoir kernel is to be that it needn't access transistor, and wherein this access transistor can be used as the director element that sends a signal to the reservoir kernel.In addition, the present invention can reduce the needed program voltage of reservoir kernel, also can reduce its process temperatures.The present invention can promote the manufacturing of three-dimensional reservoir, and wherein this reservoir can be non-volatile and reservoir fast.
Above-mentioned summary of the invention and following disclosed embodiment are only in order to explain the example of embodiments of the present invention, and so it is not in order to limit the present invention.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A illustrates the synoptic diagram into a kind of reservoir kernel of one embodiment of the invention.
Figure 1B illustrates the synoptic diagram into a kind of reservoir kernel of one embodiment of the invention.
Fig. 2 A and 2B illustrate the synoptic diagram for reservoir kernel formed a kind of three-dimensional reservoir after piling up.
Fig. 2 C illustrate for the reservoir kernel through piling up the diagrammatic cross-section of the three-dimensional reservoir of making.
Fig. 3 A illustrates the array synoptic diagram into the reservoir kernel that forms one deck.
Fig. 3 B illustrates and is the bit line that connects the selection circuit and the reservoir kernel array synoptic diagram of word line.
Fig. 3 C illustrates the synoptic diagram into the three-dimensional reservoir of multilayer.
Fig. 3 D illustrates to forming the reservoir kernel array of multilayer, and it is the some of three-dimensional reservoir.
Fig. 4 A to 4D illustrates the synoptic diagram for the programming technique that can put on the chalcogenide memory element.
Fig. 5 A to 5C illustrates the method that reads an element for three embodiment of the present invention.
102,108: top electrodes
104,110: the initialize switch layer
106,112: bottom electrode
114: select circuit
202,210,214,222: word line
204,212,216,220: the initialize switch layer
206,208,218: bit line
304,310,318: word line
306,314,320: the initialize switch layer
302,312,316: bit line
308: select element
311: the reservoir array layer
317: the reservoir kernel
408s, 408r: storage element
408a to 408n: storage element
Vthl: low starting potential
Vthh: high starting potential
Vp, Vpl, Vph: bias voltage
Embodiment
The present invention is by an initialize switch being incorporated in the storage element and needn't access transistor.In one embodiment, this initialize switch material is chalcogenide (chalcogenide) material.Further the Vth adjustment data about the material that can change starting potential Vth is to disclose in No. the 10/465th, 120, United States Patent (USP).
In one embodiment, can utilize the initialize switch material similar transistor characteristic and needn't director element to simplify the storage element structure, it for example is access transistor or P-N diode.Apparently, concerning the skill person who knows the present technique field, can on the chalcogenide storage element, implant logical circuit with form the single-chip system (a system on a chip, SoC).And then for chalcogenide, in case during this non-volatile speciality of programming, can carry out read-write operation relatively apace.It should be noted that and only read reservoir than quickflashing by relevant with the initialize switch material (for example being chalcogenide material) program voltage (read only memory, program voltage ROM) is much lower.For example, the program voltage of chalcogenide storage element approximately is 5 volts (V), and quickflashing only to read the program voltage of reservoir approximately be 10 volts.
The chalcogenide storage element has the dual-use function of director element and storage unit.Therefore, it is more easy more than transistor and chalcogenide storage element are combined only to make a chalcogenide memory.In addition, when this storage element during as director element, have under the identical storage volume situation, its wafer volume will be less than having the director element separately and the reservoir of storage element.Relatively, have under the long-pending situation of same stored body, compare with having the director element that separates and the reservoir of storage element, difunctional (dual functioning) chalcogenide memory can provide higher storage volume.Compare with access transistor, a undersized chalcogenide memory element can pass through higher electric current.In this embodiment, use chalcogenide material only to be one and give an example, be not limited to chalcogenide material as the initialize switch material.Any material with this chalcogenide material character for example has stable and adjustable starting potential (Vth) characteristic, may be used to non-volatile difunctional storage element.
Figure 1A and Figure 1B illustrate the synoptic diagram into a kind of reservoir kernel of one embodiment of the invention.Reservoir kernel unit shown in Figure 1A comprise a top electrodes 102 and a bottom electrode 106 and be arranged at top electrodes 102 and bottom electrode 106 between an initial switching layer (threshold-switching layer) 104.Top electrodes 106 can be initial (threshold) characteristic material that metal, metalloid (metalloid), semiconductor or silicide (silicide) or other have stable and adjustable-voltage.
Same, Figure 1B is another embodiment of reservoir kernel.In this embodiment, this reservoir kernel comprise a top electrodes 108 and a bottom electrode 112 and be arranged at top electrodes 108 and first end of bottom electrode 112 between an initial switching layer 110.First end of bottom electrode 112 links to each other with initialize switch layer 110 and second end of bottom electrode 112 links to each other with selecting circuit 114.This selection circuit 114 can be selected and storage element corresponding bit line and word line.
Fig. 2 A and 2B illustrate the synoptic diagram for as shown in Figure 1A and 1B reservoir kernel formed a kind of storage unit after piling up.Fig. 2 A comprises a word line 202 and a bit line 206.Certainly, in certain embodiments, on behalf of word line and 202,206 can represent bit line.Fig. 2 A further comprises an initial switching layer 204 that is arranged at 206 of word line 202 and bit lines.This word line 202 and bit line 206 can be the electrodes that is similar among Figure 1A and the 1B.Each reservoir kernel can be deposited on another reservoir kernel to form a magazine member.
Fig. 2 B and Fig. 2 category-A seemingly, difference is to constitute the independent stratum (individual layers) of reservoir kernel.In the present embodiment, the reservoir kernel comprises a bit line 208 and a word line 210.Certainly, in certain embodiments, on behalf of word line and 210,208 can represent bit line.Initialize switch layer 212 is positioned under the word line 210.Therefore, each layer that piles up comprises a bit line 208, a word line 210 and an initial switching layer 212.
Fig. 2 C illustrate for the reservoir kernel shown in Fig. 2 A and 2B through piling up the diagrammatic cross-section of the three-dimensional reservoir of making.Fig. 2 C comprises a word line 214 and a bit line 218.Fig. 2 C further comprises an initial switching layer 216 that is arranged between word line 214 and the bit line 218.Similarly, another initial switching layer 220 is arranged between bit line 218 and the word line 222.
Pile up by the array of above-mentioned reservoir kernel and can produce three-dimensional reservoir.Fig. 3 A illustrates the array synoptic diagram into the reservoir kernel of Fig. 2 A and 2B.This reservoir array can pile up and form three-dimensional reservoir.Each reservoir kernel in the reservoir kernel array comprise a bit line 302, a word line 304 and be arranged at word line 304 and bit line 302 between an initial switching layer 306.
Fig. 3 B illustrates to being similar to the described reservoir kernel of Fig. 3 A array synoptic diagram.In an embodiment of the present invention, the selection element 308 of word line 304 and bit line 302 is connected in the outer rim of reservoir kernel array.Although the selection element 308 shown in Fig. 3 B is transistors, this selection element also can be P-N diode, Schottky diode (Schottky diodes) or wear tunnel diode (tunnelingdiode).Fig. 3 C illustrates the synoptic diagram into the three-dimensional reservoir of multilayer.Fig. 3 C comprises a plurality of reservoir array layers 311.Each reservoir array layer 311 comprises many word lines 310, bit line 312 and initialize switch layer 314.
Fig. 3 D is that the reservoir kernel array that illustrates according to one embodiment of the invention is through piling up the synoptic diagram of the three-dimensional reservoir of making.Each layer reservoir 317 comprise multiple bit lines 316, many word lines 318 and be arranged at bit line 316 and word line 318 between initialize switch layer 320.
In more detail, three-dimensional reservoir (3D memory) is made of the multilayer reservoir.Each layer reservoir comprises m bar word line WL
1, WL
2... WL
m, n bit lines BL
1, BL
2... BL
nAnd most initialize switch layers 320.M wherein, n is a natural number.This three-dimensional reservoir only has two initialize switch layer C in the zone that word line i, word line i+1 and bit line j, bit line j+1 are enclosed
I, j+1And C
I+1, jWherein, i is odd number and 1≤i≤m-1; J is natural number and j=1～n-1; Above-mentioned initialize switch layer C
I, j+1Expression connects the initialize switch layer of word line i and bit line j+1; Above-mentioned initialize switch layer C
I+1, jExpression connects the initialize switch layer of word line i+1 and bit line j.
Initialize switch layer (C
I, j+1And C
I+1, j) 320 constitute by chalcogenide material.Each initialize switch layer constitutes a reservoir kernel with word line that is connected and the bit line that is connected.With initialize switch layer C
I, j+1, the reservoir kernel that constituted of word line i and word line i+1, it has first starting potential of a low voltage value and second starting potential of a high-voltage value, first starting potential is corresponding to initialize switch layer C
I, j+1First storing state, second starting potential is corresponding to this initialize switch layer C
I, j+1Second storing state.As word line WL
iWith bit line BL
J+1Between magnitude of voltage when being first starting potential, initialize switch layer C
I, j+1By gating and be in first storing state, as word line WL
iWith bit line BL
J+1Between magnitude of voltage when being second starting potential, initialize switch layer C
I, j+1By gating and be in second storing state, as word line WL
iWith bit line BL
J+1When floating, initialize switch layer C
I, j+1Be in non-strobe state.
In the present invention, be again storage element because the reservoir kernel is a director element, therefore needn't use transistor as director element.As mentioned above, having omitted transistor as director element in fact is the demand of having exempted when making reservoir for high-quality silicon.Simultaneously, also relatively reduced the temperature of making reservoir.So promptly can make the multilayer reservoir and not need to carry out any interlayer correction by traditional photoengraving (photo/etching) or damascene (damascene) technology.
Because this initialize switch material can be used as director element, so exempted the demand for extra director element.Therefore, can be combined into a three-dimensional reservoir at an easy rate by making reservoir kernel array layer by layer.In addition, will help to improve reservoir density by merging most layers.
Fig. 4 A to 4D illustrates the synoptic diagram for the programming technique that can put on the chalcogenide memory element.What Fig. 4 A represented is programming (floating programming) technology of floating.At this, suppose that the chalcogenide memory element comprises two starting potentials, for example be a low starting potential (Vthl) and a high starting potential (Vthh) as state 0 as state 1.What Fig. 4 A described is the bias voltage that puts on the storage element.Unselected storage element be apply-Vp is to the bias voltage the between+Vp, and the unit of selecting is to apply forward+Vp bias voltage.Storage element 408s is the unit that representative is selected, and remaining unit 408a to 408n representative is unselected unit.Table 1 has been concluded the programmed method of formula 1 and formula 0.
Table 1
| Formula 1 | |
|
| The bit line of selecting | ??0 | ??0 |
| Other bit line | Float | Float |
| The word line of selecting | ??Vpl | ??Vph |
| Other word line | Float | Float |
Bias voltage as shown in table 1, the bit line of selection are zero, and the word line of selecting is to be Vpl or Vph according to formula or selected state.
What Fig. 4 B represented is a bias voltage programming technique.The bias voltage that diagrammatic representation applied of Fig. 4 B.At this, can on unselected word line and bit line, apply a voltage (bias voltage).On the unit 408s that selects is to apply forward+Vp bias voltage.Can suppose that the chalcogenide memory element comprises two starting potentials, for example be a low starting potential (Vthl) and the high starting potential (Vthh) as state 0 as state 1.Following table 2 has been listed the programmed method of formula 1 and formula 0.
Table 2
| Formula 1 | |
|
| The bit line of selecting | ??0 | ??0 |
| Other bit line | ??0≤V≤Vpl | ??0≤V≤Vph |
| The word line of selecting | ??Vpl | ??Vph |
| Other word line | ??0≤V≤Vpl | ??0≤V≤Vph |
Bias voltage as shown in table 2, the bit line of selection are zero, and the word line of selecting is Vpl or Vph according to the state of formula or selection.It should be noted that respectively and as shown in Fig. 4 C and 4D, can adopt the embodiment of two bias voltage programmed methods, just V/2 method and V/3 method.Certainly, other bias voltage programmed method can also be as programmed method of the present invention, so method described herein is only as an embodiment but be not to be limited to this embodiment.
Fig. 4 C illustrates the synoptic diagram into the V/2 method.What Fig. 4 C described is the bias voltage that puts on the storage element.Be to apply forward+Vp bias voltage on the storage element 408s of this selection, remaining other unselected storage elements then apply forward+Vp/2 bias voltage.Can suppose that this chalcogenide memory element comprises two starting potentials, just as a low starting potential (Vthl) of state 1 with as a high starting potential (Vthh) of state 0.The programmed method of state 1 and state 0 is that tabular is in following table 3.
Table 3
| Formula 1 | |
|
| The bit line of selecting | ??0 | ??0 |
| Other bit line | ??Vpl/2 | ??Vph/2 |
| The word line of selecting | ??Vpl | ??Vph |
| Other word line | ??Vpl/2 | ??Vph/2 |
Bias voltage as shown in table 3, the bit line of selection are zero, and the word line of selecting is Vpl or Vph according to formula or selected state then.
Fig. 4 D illustrates the synoptic diagram into the V/3 method.What Fig. 4 D described is the bias voltage that puts on the storage element.The storage element 408s of this selection applies forward+Vp bias voltage, remaining other unselected storage elements then have one of them of following two specific characters, just some unselected storage elements are to apply forward bias+Vp/3, and some unselected storage elements then apply reverse biased-Vp/3.Storage element 408f applies forward bias+Vp/3, and storage element 408r then applies reverse biased-Vp/3.Can suppose that the chalcogenide memory element comprises two starting potentials, just a low starting potential (Vthl) and a high starting potential (Vthh) as state 0 as state 1.As for the programmed method of state 1 and state 0 then tabular in following table 4.
Table 4
| Formula 1 | |
|
| The bit line of selecting | ??0 | ??0 |
| Other bit line | ??2Vpl/3 | ??2Vph/3 |
| The word line of selecting | ??Vpl | ??Vph |
| Other word line | ??Vpl/3 | ??Vph/3 |
Bias voltage as shown in table 4, the bit line of selection are zero, and the word line of selecting is Vpl or Vph according to the state of formula or selection then.Limited field that it should be noted that program voltage can be: " Vthh＜Vp＜3Vthl ".
Read method comprises the method for floating and a bias method.The bias voltage Vr that this method of floating relates to Vthl and the bias voltage between the Vthh on the word line (perhaps bit line) that puts on selection and is applied to the zero-bias on the word line (perhaps bit line) of selection, and other word line and bit line are floated.The bias voltage Vr that this bias method relates to Vthl and the bias voltage between the Vthh on the word line (perhaps bit line) that puts on selection and is applied to the zero-bias on the word line (perhaps bit line) of selection, other word line and bit line then are the fixed-bias transistor circuits that is applied in 0＜V＜Vthl scope.In the present invention, be the bias method that two different embodiment are provided, also be exactly V/2 method and V/3 method.
Fig. 5 A illustrates the method that reads an element for one embodiment of the invention respectively to 5C.Fig. 5 A represents the bias voltage that puts on the storage element separately to 5C.Fig. 5 A represents a kind of method of floating, and wherein this bias voltage is to+Vr and selected cell 408s applies forward bias+Vr by-Vr.What Fig. 5 B represented is the read method of a kind of V/2, and wherein selected cell 408s then applies forward bias+Vr.Shown in Fig. 5 B, all the other unselected unit are to apply forward bias+Vr/2.What Fig. 5 C represented is the read method of a kind of V/3, and selected cell 408s applies forward bias+Vr.The unselected unit of among Fig. 5 C all the other then applies forward bias+Vr/3 or reverse biased-Vr/3.It should be noted that among Fig. 5 C unselected unit be formed one with the similar pattern of Fig. 4 D.
In sum, the invention provides a kind of reservoir kernel, it needn't use the access transistor that is used for access kernel storage element.In other words, when this kernel unit has added an initial switching material, for example be chalcogenide material, can come access kernel storage element by programming kernel storage element.In fact, also can be used as director element by programming initialize switch material.Anyly know skill person of the present invention and can know that all the decode logic signal that simplification can also be provided makes that in the mode of access transistor the present invention needn't access transistor.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (15)
1. a three-dimensional reservoir is made of the multilayer reservoir, it is characterized in that each layer reservoir comprises:
M bar word line, wherein m is a natural number;
The n bit lines, wherein n is a natural number;
Most initialize switch layers are made of chalcogenide material, wherein only in the zone that word line i, word line i+1 and bit line j, bit line j+1 are enclosed two initialize switch layer C are arranged
I, j+1And C
I+1, j,
Wherein
I is an odd number, 1≤i≤m-1;
J is a natural number, j=1～n-1;
Above-mentioned initialize switch layer C
I, j+1Expression connects the initialize switch layer of word line i and bit line j+1;
Above-mentioned initialize switch layer C
I+1, jExpression connects the initialize switch layer of word line i+1 and bit line j;
Each initialize switch layer constitutes a reservoir kernel with word line that is connected and the bit line that is connected, each reservoir kernel has first starting potential of a low voltage value and second starting potential of a high-voltage value, this first starting potential is corresponding to one first storing state of this initialize switch layer, and this second starting potential is corresponding to one second storing state of this reservoir;
When the magnitude of voltage between this word line and this bit line is this first starting potential, this initialize switch layer is by gating and be in this first storing state, when the magnitude of voltage between this word line electrode and this bit line is this second starting potential, this initialize switch layer is by gating and be in this second storing state, when this word line and bit line were floated, this initialize switch layer was in non-strobe state.
2. three-dimensional reservoir according to claim 1 is characterized in that wherein said word line comprises a metal material or a metalloid material.
3. three-dimensional reservoir according to claim 1 is characterized in that wherein said bit line comprises semiconductor material or silicide.
4. reservoir kernel according to claim 3 is characterized in that wherein said semiconductor material comprises silicon.
5. three-dimensional reservoir according to claim 1 is characterized in that wherein said initialize switch layer can be in order to be provided in a non-volatile storage.
6. three-dimensional reservoir according to claim 1 is characterized in that wherein said first storing state is expressed as state 1, and described second storing state is expressed as state 0.
7. the method for an access reservoir kernel in three-dimensional reservoir, this three-dimensional reservoir is made of the multilayer reservoir, and each layer reservoir comprises:
M bar word line, wherein m is a natural number;
The n bit lines, wherein n is a natural number;
Most initialize switch layers are made of chalcogenide material, wherein only in the zone that word line i, word line i+1 and bit line j, bit line j+1 are enclosed two initialize switch layer C are arranged
I, j+1And C
I+1, j,
Wherein
I is an odd number, 1≤i≤m-1;
J is a natural number, j=1～n-1;
Above-mentioned initialize switch layer C
I, j+1Expression connects the initialize switch layer of word line i and bit line j+1;
Above-mentioned initialize switch layer C
I+1, jExpression connects the initialize switch layer of word line i+1 and bit line j;
Each initialize switch layer constitutes a reservoir kernel with word line that is connected and the bit line that is connected, each reservoir kernel has first starting potential of a low voltage value and second starting potential of a high-voltage value, this first starting potential is corresponding to one first storing state of this initialize switch layer, and this second starting potential is corresponding to one second storing state of this reservoir;
When the magnitude of voltage between this word line and this bit line is this first starting potential, this initialize switch layer is by gating and be in this first storing state, when the magnitude of voltage between this word line electrode and this bit line is this second starting potential, this initialize switch layer is by gating and be in this second storing state, when this word line and bit line are floated, this initialize switch layer is in non-strobe state
It is characterized in that it comprises:
Decision is used for one of them an initial voltage of the above-mentioned reservoir kernel of access;
The programme initialize switch layer of this reservoir kernel is so that can this reservoir kernel of access under this starting potential;
Apply a voltage in a word line; And
When if this voltage equals this starting potential at least, can this reservoir kernel of access.
8. according to claim 7 in three-dimensional reservoir the method for access reservoir kernel, it is characterized in that wherein programming this initialize switch layer of this reservoir kernel is so that step that can this reservoir kernel of access under this starting potential comprises: adopt a livitation or a bias voltage technology.
9. according to claim 7 in three-dimensional reservoir the method for access reservoir kernel, it is characterized in that it more comprises: if this voltage during less than this starting potential, is then refused this reservoir kernel of access.
10. method that reads 3 d memory, this three-dimensional reservoir is made of the multilayer reservoir, and each layer reservoir comprises:
M bar word line, wherein m is a natural number;
The n bit lines, wherein n is a natural number;
Most initialize switch layers are made of chalcogenide material, wherein only in the zone that word line i, word line i+1 and bit line j, bit line j+1 are enclosed two initialize switch layer C are arranged
I, j+1And C
I+1, j,
Wherein
I is an odd number, 1≤i≤m-1;
J is a natural number, j=1～n-1;
Above-mentioned initialize switch layer C
I, j+1Expression connects the initialize switch layer of word line i and bit line j+1;
Above-mentioned initialize switch layer C
I+1, jExpression connects the initialize switch layer of word line i+1 and bit line j;
Each initialize switch layer constitutes a reservoir kernel with word line that is connected and the bit line that is connected, each reservoir kernel has first starting potential of a low voltage value and second starting potential of a high-voltage value, this first starting potential is corresponding to one first storing state of this initialize switch layer, and this second starting potential is corresponding to one second storing state of this reservoir;
When the magnitude of voltage between this word line and this bit line is this first starting potential, this initialize switch layer is by gating and be in this first storing state, when the magnitude of voltage between this word line electrode and this bit line is this second starting potential, this initialize switch layer is by gating and be in this second storing state, when this word line and bit line are floated, this initialize switch layer is in non-strobe state
It is characterized in that it comprises:
Apply one and read voltage in a word line of selecting, and this read voltage can be in order to this reservoir kernel of the corresponding selected word line of direct access;
Apply a zero-bias in a bit line, and this bit line is the word line corresponding to this selection; And
Read a numerical value that is stored in this reservoir kernel.
11. the method that reads 3 d memory according to claim 10 is characterized in that it more comprises: keep unselected word line and unselected bit line in a floating state.
12. the method that reads 3 d memory according to claim 10 is characterized in that it more comprises:
Apply a bias voltage in unselected word line and unselected bit line.
13. the method that reads 3 d memory according to claim 12 is characterized in that wherein said bias voltage is less than an initial voltage, and the scope of this bias voltage is between about 20V between 0.1V.
14. the method that reads 3 d memory according to claim 12 is characterized in that wherein said bias voltage approximately is that this reads voltage half.
15. the method that reads 3 d memory according to claim 12, it is characterized in that wherein said bias voltage approximately be on the unselected word line read voltage 1/3rd and approximately be to read 2/3rds of voltage on the unselected bit line.
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| US10/948,891 US20050041467A1 (en) | 2003-06-18 | 2004-09-24 | Chalcogenide memory |
| US10/948,891 | 2004-09-24 |
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| CN 200510105365 Division CN1770494B (en) | 2004-09-24 | 2005-09-23 | Chalcogenide memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800361A (en) * | 2011-05-24 | 2012-11-28 | 爱思开海力士有限公司 | 3-dimensional non-volatile memory device and method of manufacturing the same |
| CN107924699A (en) * | 2015-04-24 | 2018-04-17 | 李武开 | Part/complete array/block erasing for 2D/3D hierarchy types NAND |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10134470B2 (en) | 2015-11-04 | 2018-11-20 | Micron Technology, Inc. | Apparatuses and methods including memory and operation of same |
| US9978810B2 (en) * | 2015-11-04 | 2018-05-22 | Micron Technology, Inc. | Three-dimensional memory apparatuses and methods of use |
| KR102410947B1 (en) * | 2015-11-20 | 2022-06-22 | 에스케이하이닉스 주식회사 | Threshold switching device and electronic device including the same |
| CN105788632B (en) * | 2016-02-26 | 2019-04-02 | 江苏时代全芯存储科技有限公司 | Memory circuit |
| US10446226B2 (en) | 2016-08-08 | 2019-10-15 | Micron Technology, Inc. | Apparatuses including multi-level memory cells and methods of operation of same |
| CN106898371B (en) * | 2017-02-24 | 2020-08-28 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional memory reading circuit and word line and bit line voltage configuration method thereof |
| CN107644664A (en) * | 2017-09-27 | 2018-01-30 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional perpendicular type memory circuitry and bit line and word line voltage collocation method |
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| US5761115A (en) * | 1996-05-30 | 1998-06-02 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102800361A (en) * | 2011-05-24 | 2012-11-28 | 爱思开海力士有限公司 | 3-dimensional non-volatile memory device and method of manufacturing the same |
| US9508836B2 (en) | 2011-05-24 | 2016-11-29 | SK Hynix Inc. | 3-dimensional non-volatile memory device and method of manufacturing the same |
| CN107924699A (en) * | 2015-04-24 | 2018-04-17 | 李武开 | Part/complete array/block erasing for 2D/3D hierarchy types NAND |
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| TW200611270A (en) | 2006-04-01 |
| CN101702328B (en) | 2013-03-06 |
| TWI313863B (en) | 2009-08-21 |
| CN1770494A (en) | 2006-05-10 |
| CN1770494B (en) | 2010-05-05 |
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