CN101697479B - Adjustable grain low noise amplifier - Google Patents
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- CN101697479B CN101697479B CN2009102090514A CN200910209051A CN101697479B CN 101697479 B CN101697479 B CN 101697479B CN 2009102090514 A CN2009102090514 A CN 2009102090514A CN 200910209051 A CN200910209051 A CN 200910209051A CN 101697479 B CN101697479 B CN 101697479B
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Abstract
The invention discloses an adjustable grain low noise amplifier which is a cascode. The adjustable grain low noise amplifier comprises a grain adjusting control circuit, a load circuit, a current guiding circuit and an input circuit, wherein the grain adjusting control circuit is used for receiving a grain adjusting voltage and further generating a resistance value adjusting signal and a current guiding control signal; the load circuit comprises a plurality of variable resistors and is used for adjusting the resistance values of the plurality of the variable resistors according to the resistance values; the current guiding circuit is connected to the load circuit through a plurality of current paths and is used for adjusting the current ratios among the plurality of current paths according to the current guiding control signal and the current guiding circuit is provided with a differential signal output end; and the input circuit is connected to the current guiding circuit, wherein the input circuit is provided with a differential signal input end. The amplifier can provide low noise index during low grain and provide wider grain adjusting range, and further achieve lower power loss, smaller layout area, lower linearity requirement and other effects.
Description
Technical field
The present invention relates to a kind of adjustable grain low noise amplifier, refer to a kind of adjustable grain low noise amplifier of high linearity especially, it can be used in TV tuner or other wideband communication system, and low noise figure can be provided when low gain.
Background technology
In wideband communication system (broadband communication system); For example TV tuner (TV tuner) all must use high linearity adjustable grain low noise amplifier (high linearvariable-gain low noise amplifier) and place frequency mixer (Mixer) before.In addition, general high linearity adjustable grain low noise amplifier generally all is to utilize electric current bootstrapping architecture (currentsteering topology) to accomplish.
Please with reference to Figure 1A, it is depicted as known high linearity variable gain amplifier.It is disclosed in 1991 " IEEE J.Solid-State Circuit " periodical vol.26, no.11, pp.1673-1680.It is one differential to (differential pair) that the first transistor Q1 and transistor seconds Q2 are connected to form; Wherein, the base stage (base) of the first transistor Q1 and transistor seconds Q2 can receive an input signal (vi) for the differential wave input of amplifier (differential signal input terminals); First end of two emitter resistances (Re) is connected to the first transistor Q1 and transistor seconds Q2 emitter (Emitter) respectively; Second end of two emitter resistances (Re) is connected in node a.Current source Is is connected between node a and the earth terminal (Gnd).
In addition; The base stage of the 3rd transistor Q3 and the 4th transistor Q4 is that Amplifier Gain control input end (gain control terminals) can receive electric current guiding control signal (current steeringcontrol signal; Vctrl); The 3rd transistor Q3 collector electrode (collector) is connected to voltage source (Vcc), and emitter is connected to the first transistor Q1 collector electrode; Be connected one first collector resistance (Rc1) between the 4th transistor Q4 collector electrode and the voltage source (Vcc), emitter is connected to the first transistor Q1 collector electrode.The 5th transistor Q5 base stage is connected to the 4th transistor Q4 base stage; The 6th transistor Q6 base stage is connected to the 3rd transistor Q3 base stage; The 6th transistor Q6 collector electrode is connected to voltage source (Vcc), and emitter is connected to transistor seconds Q2 collector electrode; Be connected one second collector resistance (Rc2) between the 5th transistor Q5 collector electrode and the voltage source (Vcc), emitter is connected to transistor seconds Q2 collector electrode.The 4th transistor Q4 collector electrode and the 5th transistor Q5 collector electrode become differential wave output (differentialsignal output terminals) can produce an output signal (vo).
Wherein, current source Is can provide the Dc bias (DC bias) of all crystals pipe on the amplifier, and two emitter resistances (Re) can provide amplifier to obtain the preferable linearity.In addition, the resistance value of first collector resistance (Rc1) and second collector resistance (Rc2) is identical.
When electric current guiding control signal (Vctrl) changed, the bias current (bias currents) of the 3rd transistor Q3 that flows through, the 4th transistor Q4, the 5th transistor Q5, the 6th transistor Q6 can change, so the may command Amplifier Gain.In addition, above-mentioned amplifier can be realized big gain adjustment interval (high gain control range).
Yet (noise figure, NF) variation with gain is relevant for the noise figure of known high linearity variable gain amplifier.Please with reference to Figure 1B and Fig. 1 C, it is depicted as the gain (Gain) and noise figure (NF) sketch map of known high linearity variable gain amplifier.Can know that by Figure 1B and Fig. 1 C when Amplifier Gain was very big, noise figure was very little; Otherwise when Amplifier Gain was very little, noise figure was very big.That is to say that utilize electric current guiding control signal (Vctrl) when adjusting Amplifier Gain, noise figure (NF) is understood the minimizing along with gain, and then causes the rising that almost waits ratio.
In system considered, (when vi) very little, Amplifier Gain can transfer to the highest, so the noise figure of circuit (NF) can't be very big when input signal.So the output signal (vo) of amplifier still can provide enough signal to noise ratio (snr)s.(when vi) big, Amplifier Gain needs to reduce, and this moment, the noise figure of amplifier will rise, but because signal also increases simultaneously, so its output signal (vo) still can provide enough signal to noise ratio (snr)s when input signal.But in the application in broadband; When interference noise (interference) is much larger than useful signal sometimes; The electronic building brick in the amplifier got into the saturation region and can Amplifier Gain be reduced this moment; Therefore too many if the noise figure (NF) of this circuit rises, its output signal (vo) can't provide enough signal to noise ratio (snr)s, and cause baseband circuit can't signal effectively be restored.Therefore amplifier is when low gain, and low noise figure (NF) also is considerable index.
Please with reference to Fig. 2, it is depicted as another kind of known high linearity adjustable grain low noise amplifier.It is disclosed in United States Patent (USP) " US 6,100,761 ".It is one differential to (differential pair) that the first transistor 1Q1 and transistor seconds 1Q2 are connected to form.Wherein, Be connected one first base resistance (1Rb1) and one second base resistance (1Rb2) respectively between the base stage of the first transistor 1Q1 and transistor seconds 1Q2 and the base voltage (Vb); And the base stage of the first transistor 1Q1 and transistor seconds 1Q2 is the differential wave input (differential signal input terminals, IN+ and IN-) of amplifier.
First end of two emitter adjustable resistances (1Re) 40 is connected to the emitter of the first transistor 1Q1 and transistor seconds 1Q2; Second end of two emitter adjustable resistances (1Re) 40 is connected in earth terminal (Gnd).Moreover first end of two collector electrode adjustable resistances (1Rc) 30 is connected to the collector electrode of the first transistor 1Q1 and transistor seconds 1Q2; Second end of two collector electrode adjustable resistances (1Rc) 30 is connected in collector voltage (Vc).In addition, the current collection of the first transistor 1Q1 and transistor seconds 1Q2 very the differential wave output of amplifier (differential signal output terminals ,-OUT+).
Amplifier shown in Figure 2 is that the resistance value of control emitter adjustable resistance (1Re) 40 and collector electrode adjustable resistance (1Rc) 30 is adjusted Amplifier Gain.Yet adjustment emitter adjustable resistance (1Re) 40 can make the linearity variation of amplifier.
Summary of the invention
The objective of the invention is to propose a kind of high linearity adjustable grain low noise amplifier, lower noise figure can be provided when low gain.
The present invention proposes a kind of adjustable grain low noise cascode amplifier, comprising: a gain adjustment control circuit, and adjust voltage in order to receive a gain, and then produce resistance value adjustment signal and this electric current guiding control signal; Wherein this gain adjustment control circuit comprises: a control unit, resistance value adjustment circuit and electric current guiding control circuit; Wherein, When voltage is adjusted in this gain in this high-gain adjustment region; This control unit is controlled this resistance value adjustment circuit and is changed this resistance value adjustment signal, and when voltage was adjusted in this gain in this low gain adjustment region, this electric current guiding control circuit of this control unit control changed this electric current guiding control signal; One load circuit comprises a plurality of variable resistors, in order to adjust said a plurality of variable-resistance resistance value according to this resistance value adjustment signal; One current guiding circuit utilizes a plurality of current paths to be connected to this load circuit, and in order to adjust the current ratio between said a plurality of current path according to this electric current guiding control signal, wherein this current guiding circuit has the differential wave output; And an input circuit, be connected to this current guiding circuit, wherein this input circuit has the differential wave input.
Therefore, the present invention proposes a kind of adjustable grain low noise cascode amplifier, comprising: first bipolar junction transistor; Second bipolar junction transistor, the base stage of this first bipolar junction transistor and this second bipolar junction transistor are a differential wave input; Two emitter resistances, first end of said emitter resistance is connected to the emitter of this first bipolar junction transistor and this second bipolar junction transistor respectively, and second end of said emitter resistance is connected to a first node; One first current source is connected between this first node and the earth terminal; One first variable resistor; One the one n type field-effect transistor, its grid receives a grid voltage, its source electrode is connected to the collector electrode of this first bipolar junction transistor, and, its drain electrode with a supply voltage between be connected this first variable resistor; One the 2nd n type field-effect transistor, its grid receive electric current guiding control signal, and its source electrode is connected to the collector electrode of this first bipolar junction transistor, and its drain electrode is connected to this supply voltage; One the second adjustable resistance; One the 3rd n type field-effect transistor, its grid receive this electric current guiding control signal, and source electrode is connected to the collector electrode of this second bipolar junction transistor, and its drain electrode is connected to this supply voltage; One the 4th n type field-effect transistor, its grid receives this grid voltage, and its source electrode is connected to the collector electrode of this second bipolar junction transistor, and, be connected this second adjustable resistance between its drain electrode and this supply voltage; And a gain adjustment control circuit, in order to receiving a gain adjustment voltage, and then produce this electric current guiding control signal, and resistance value adjustment signal is in order to adjust this first variable resistor and this second adjustable resistance; This gain adjustment control circuit is when voltage is adjusted in this gain in a high-gain adjustment region; Adjust this resistance value adjustment signal and fixing this electric current guiding control signal; When voltage is adjusted in this gain in a low gain adjustment region, adjust this electric current guiding control signal and fixing this resistance value adjustment signal; This gain adjustment control circuit comprises: a control unit, resistance value adjustment circuit and electric current guiding control circuit; When voltage is adjusted in this gain in this high-gain adjustment region; This resistance value adjustment circuit of this control unit control changes this resistance value adjustment signal; And when voltage was adjusted in this gain in this low gain adjustment region, this electric current guiding control circuit of this control unit control changed this electric current guiding control signal; Wherein, the drain electrode of a n type field-effect transistor and the 4th n type field-effect transistor becomes a differential wave output.
Advantage of the present invention is the adjustable grain low noise amplifier that proposes a kind of high linearity; In the time of in the high-gain adjustment region; Utilize the variable-resistance resistance value of change to change Amplifier Gain, in the time of in the low gain adjustment region, change the transduction parameter and change gain.Therefore, utilize amplifier of the present invention that low noise figure can be provided when low gain.And, compared to the known high linearity known variable gain amplifier, the noise figure of the same, it can provide a larger range of gain adjustment, thus achieving lower power are consumed, a small layout area and low linearity requirements and other effects.
In order further to understand characteristic of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet appended diagram only provides reference and explanation, is not to be used for the present invention is limited.
Description of drawings
Figure 1A is depicted as known high linearity variable gain amplifier.
Figure 1B and Fig. 1 C are depicted as the gain (Gain) and noise figure (NF) sketch map of known high linearity variable gain amplifier.
Shown in Figure 2 is another kind of known high linearity adjustable grain low noise amplifier.
Fig. 3 A is depicted as high linearity adjustable grain low noise amplifier block schematic diagram of the present invention.
Fig. 3 B is depicted as first embodiment of high linearity adjustable grain low noise amplifier circuit diagram of the present invention.
Fig. 3 C is depicted as second embodiment of high linearity adjustable grain low noise amplifier circuit diagram of the present invention.
Fig. 4 A and Fig. 4 B are depicted as Amplifier Gain of the present invention and noise figure (NF) sketch map.
Fig. 5 A to Fig. 5 C is depicted as the various embodiment of variable resistor (RL).
Fig. 6 A is depicted as the present invention's adjustment control circuit that gains.
Fig. 6 B is depicted as gain adjustment control circuit at the interval adjustment sketch map of high-gain adjustment.
Fig. 6 C is depicted as gain adjustment control circuit at the interval adjustment sketch map of low gain adjustment.
The primary clustering symbol description is following:
30 collector electrode adjustable resistances, 40 emitter adjustable resistances
100 gain adjustment control circuits, 110 load circuits
115 current paths, 120 current guiding circuit
130 input circuits, 200 control units
Embodiment
Please with reference to Fig. 3 A, it is depicted as high linearity adjustable grain low noise amplifier block schematic diagram of the present invention.This amplifier comprises gain adjustment control circuit (gain control circuit) 100, load circuit (load circuit) 110, current guiding circuit (current steering circuit) 120, input circuit (input circuit) 130.Wherein load circuit 110, current guiding circuit 120, be connected to form cascode amplifier (cascode amplifier) with input circuit 130.
Gain adjustment control circuit 100 receive a gain adjustment voltage (gain adjusting voltage, VAGC), and then produce resistance value adjustment signal (resistance adjusting signal, Vp) and electric current guiding control signal (Vctrl).Load circuit 110 is adjusted the variable-resistance resistance value in the load circuit 110 according to resistance value adjustment signal (Vp).Current guiding circuit 120; Utilize a plurality of current paths (current paths) 115 to be connected to load circuit 110; But its received current guiding control signal (Vctrl); And adjust the current ratio (current ratio) between a plurality of current paths 115 according to this, and has differential wave output (differential signal output terminals, OUT+, OUT-).Input circuit 130 is connected to current guiding circuit 120, and it has differential wave input (differential signal input terminals, IN+, IN-).
According to embodiments of the invention, the present invention divides into two zones with Amplifier Gain adjusting range (gain controlrange), and first zone is the high-gain adjustment region, and second zone is the low gain adjustment region.Wherein, when the high-gain adjustment region, change resistance value adjustment signal (Vp) and change variable-resistance resistance value, and, when the low gain adjustment region, change the current ratio that electric current guiding control signal (Vctrl) changes current path.
Please refer to Fig. 3 B, it is depicted as circuit diagram first embodiment of high linearity adjustable grain low noise amplifier of the present invention.Input circuit 130 comprise first bipolar junction transistor (Bipolar junctiontransistor, BJT) Q1A, the second bipolar junction transistor Q1B, two emitter resistances (Re), with the first current source Ic1.It is one differential to (differential pair) that the first bipolar junction transistor Q1A and the second bipolar junction transistor Q1B are connected to form; Wherein, the base stage (base) of the first bipolar junction transistor Q1A and the second bipolar junction transistor Q1B is the differential wave input IN+ and the IN-of amplifier; First end of two emitter resistances (Re) is connected to the emitter (Emitter) of the first bipolar junction transistor Q1A and the second bipolar junction transistor Q1B respectively; Second end of two emitter resistances (Re) is connected to node a.The first current source Ic1 is connected between node a and the earth terminal (Gnd).
The grid (gate) of the one n type field effect transistor M 2A receives a grid voltage (VB3), and its source electrode (source) is connected to the collector electrode of the first bipolar junction transistor Q1A, is connected variable resistor (RL) between drain electrode (drain) and the supply voltage (Vcc).The grid of the 2nd n type field effect transistor M 3A receives electric current guiding control signal (Vctrl), and source electrode is connected to the collector electrode of the first bipolar junction transistor Q1A, and drain electrode is connected to supply voltage (Vcc).
The grid received current guiding control signal (Vctrl) of the 3rd n type field effect transistor M 3B, source electrode is connected to the collector electrode of the second bipolar junction transistor Q1B, and drain electrode is connected to supply voltage (Vcc).The grid receiving grid pole tension (VB3) of the 4th n type field effect transistor M 2B, source electrode is connected to the collector electrode of the second bipolar junction transistor Q1B, the drain electrode with supply voltage (Vcc) between be connected variable resistor (RL).And the drain electrode of a n type field effect transistor M 2A and the 4th n type field effect transistor M 2B becomes differential wave output OUT-and OUT+.
In addition, gain adjustment control circuit 100, it can receive a gain adjustment voltage, and produces resistance value adjustment signal (Vp) and electric current guiding control signal (Vctrl), and wherein, resistance value adjustment signal (Vp) can be adjusted the resistance value of variable resistor (RL).
According to embodiments of the invention, the first bipolar junction transistor Q1A has identical layout area (layout area) with the second bipolar junction transistor Q1B; The one n type field effect transistor M 2A has identical size (size) with the 4th n type field effect transistor M 2B; The 2nd n type field effect transistor M 3A has identical size with the 3rd n type field effect transistor M 3B.In addition, the first current source Ic1 is the Dc bias (DC bias) that is used to provide all crystals pipe on the amplifier, makes amplifier operate in suitable working point (Quiescent point).
Please refer to Fig. 3 C, it is depicted as circuit diagram second embodiment of high linearity adjustable grain low noise amplifier of the present invention.And the difference of first embodiment is to provide in addition one second current source Ic2 to be connected between the supply voltage (Vcc) and the first bipolar junction transistor Q1A collector electrode; And one the 3rd current source Ic3 be connected between the supply voltage (Vcc) and the second bipolar junction transistor Q1B collector electrode.And the first current source Ic1, the second current source Ic2, the Dc bias (DC bias) of all crystals pipe on the amplifier can more effectively be provided with the 3rd current source Ic3, make amplifier operate in suitable working point (Quiescent point).And, the first current source Ic1, the second current source Ic2, can't change the small-signal model (small signal model) of amplifier with the 3rd current source Ic3.
In addition, can derive its voltage gain (voltage gain) Av by the amplifier of Fig. 3 B and Fig. 3 C is:
Wherein, Gm1 is the transduction parameter (trans-conductance) of the first bipolar junction transistor Q1A and the second bipolar junction transistor Q1B; Gm2 is the transduction parameter of a n type field effect transistor M 2A and the 4th n type field effect transistor M 2B, and gm3 is the transduction parameter of the 2nd n type field effect transistor M 3A and the 3rd n type field effect transistor M 3B.
According to embodiments of the invention, the present invention divides into two zones with Amplifier Gain adjusting range (gain controlrange), and wherein, first zone is the high-gain adjustment region, and second zone is the low gain adjustment region.Wherein, when the high-gain adjustment region, utilize adjustment variable resistor (RL) to realize; And when the gain adjustment region, utilize electric current bootstrapping architecture (current steering topology) to accomplish, also promptly change the transduction parameter (gm2 and gm3) that electric current guiding control signal (Vctrl) changes n type field-effect transistor.
In other words; In gain adjustment range, will gain and be adjusted in the process of minimum value by maximum; When voltage (VAGC) is adjusted in gain in the high-gain adjustment region; Gain adjustment control circuit 100 can change resistance values adjustment signals (Vp), makes the resistance value of variable resistor (RL) reduce and electric current guiding control signal (Vctrl) remains unchanged; In addition; When voltage (VAGC) is adjusted in gain in the low gain adjustment region; Gain adjustment control circuit 100 can the fixed resistance value be adjusted signal (Vp); And then make the resistance value of variable resistor (RL) no longer change, and change that electric current guiding control signal (Vctrl) makes that transduction parameter gm3 is increasing and transduction parameter gm2 is more and more littler.
Please with reference to Fig. 4 A and Fig. 4 B, it is depicted as Amplifier Gain of the present invention and noise figure (NF) sketch map.Can know by Fig. 4 A, when gain adjustment voltage (VAGC) increases to the process of Vs2 (high-gain adjustment region) by Vs1, the process that resistance value that also can power transformation resistance (RL) changes, noise figure (NF) can change hardly.Therefore, in the high-gain adjustment region, noise figure (NF) can and not increase along with gain decline.
In addition, adjust voltage (VAGC) by the process (low gain adjustment region) that Vs2 increases to Vs3, utilize electric current guiding control signal (Vctrl) to adjust gain, so noise figure (NF) just can descend and increase along with gaining when gain.
Can know by Fig. 4 B; Compared to known Amplifier Gain and noise figure relation curve (I); Amplifier Gain of the present invention is reduced to when minimum; Can know that by Amplifier Gain of the present invention and noise figure relation curve (II) noise figure of the present invention will be far below the known noise figure that amplifier produced.
Please with reference to Fig. 5 A to Fig. 5 C, it is depicted as the various embodiment of variable resistor (RL).Shown in Fig. 5 A, variable resistor (RL) is made up of a p type field effect transistor M p1.Wherein, a p type field effect transistor M p1 grid receives resistance value adjustment signal (Vp), and source electrode then is variable resistor (RL) two ends with drain electrode.
Shown in Fig. 5 B, variable resistor (RL) is made up of the 2nd p type field effect transistor M p2 and the 3rd p type field effect transistor M p3.Wherein, the 2nd p type field effect transistor M p2 grid receives resistance value adjustment signal (Vp), and source electrode then is variable resistor (RL) two ends with drain electrode; Moreover; The 3rd p type field effect transistor M p3 source electrode is connected to the 2nd p type field effect transistor M p2 source electrode; The 3rd p type field effect transistor M p3 drain electrode is connected to the 2nd p type field effect transistor M p2 drain electrode, and the 3rd p type field effect transistor M p3 drain electrode is interconnected to form diode with grid and is connected transistor (Diode-connected transistor).
Shown in Fig. 5 C, variable resistor (RL) is made up of the 4th p type field effect transistor M p4 and polysilicon (polysilicon) resistance (Rx).Wherein, the 4th p type field effect transistor M p4 grid receives resistance value adjustment signal (Vp), and source electrode then is variable resistor (RL) two ends with drain electrode; In addition, polysilicon resistance (Rx) two ends are connected to the 4th p type field effect transistor M p4 source electrode and drain electrode respectively.
Please with reference to Fig. 6 A, it is depicted as the present invention's adjustment control circuit that gains.Gain adjustment control circuit comprises control unit 200, resistance value adjustment circuit, guides control circuit with electric current.Wherein, variable resistor (RL) is to be example with the p type field effect transistor M p1 among Fig. 5 A.
Resistance value adjustment circuit comprises that a reference resistance (Rref) is connected between the first input end of supply voltage (Vcc) and operational amplifier (OP); One first adjustable current source (Ix1) is connected between the first input end and earth terminal (Gnd) of operational amplifier (OP); The source electrode of one the 5th p type field effect transistor M p5 is connected to supply voltage (Vcc), and grid is connected to the output of operational amplifier (OP), and drain electrode is connected to second input of operational amplifier (OP); One second adjustable current source (Ix2) is connected between second input and earth terminal (Gnd) of operational amplifier (OP).Wherein, the exportable resistance value adjustment of the output of operational amplifier (OP) signal (Vp); The 5th a p type field effect transistor M p5 and a p type field effect transistor M p1 have corresponding size.
Electric current guiding control circuit comprises: the 5th n type field effect transistor M 2C drain electrode is connected to supply voltage (Vcc), grid receiving grid pole tension (VB3), and source electrode is connected to node b; The 6th n type field effect transistor M 3C drain electrode is connected with grid and can produces electric current guiding control signal (Vctrl), and source electrode is connected to node b; The 3rd adjustable current source (Ix3) is connected between supply voltage (Vcc) and the 6th n type field effect transistor M 3C drain electrode; The 4th current source (Ic4) is connected between node b and the earth terminal (Gnd).Wherein, the 5th n type field effect transistor M 2C, a n type field effect transistor M 2A, the 4th n type field effect transistor M 2B have corresponding size; The 6th n type field effect transistor M 3C, the 2nd n type field effect transistor M 3A, the 3rd n type field effect transistor M 3B have corresponding size.
Moreover, but control unit 200 receiving gains adjustment voltage (VAGC) and control first adjustable current source (Ix1), second adjustable current source (Ix2), with the 3rd adjustable current source (Ix3).
When the normal operation of resistance value adjustment circuit, when the gain of operational amplifier (OP) enough greatly the time, the voltage of two inputs will equate.Therefore,
Also promptly, the resistance value adjustment signal (Vp) of operational amplifier (OP) output can make that the equivalent resistance of the 5th p type field effect transistor M p5 is Rmp5.Because resistance value adjustment signal (Vp) is also imported a p type field effect transistor M p1 grid simultaneously, therefore, the resistance value of variable resistor (RL) also equals Rmp5.That is to say that the current ratio (current ratio) of adjusting first adjustable current source (Ix1) and second adjustable current source (Ix2) can make resistance value adjustment signal (Vp) change, and then make the resistance value of variable resistor (RL) change.
Please with reference to Fig. 6 B, it is depicted as gain adjustment control circuit at the interval adjustment sketch map of high-gain adjustment.When gain is adjusted voltage (VAGC) when rising to Vs2 by Vs1; Gain adjustment control circuit can change the current ratio (currentratio) of first adjustable current source (Ix1) and second adjustable current source (Ix2); And the 3rd adjustable current source (Ix3) be 0, and then make that current ratio (Ix1/Ix2) is more and more littler.After gain adjustment voltage (VAGC) dropped to Vs2, current ratio (Ix1/Ix2) can drop to minimum value and no longer change.That is to say that the more and more littler meeting of current ratio (Ix1/Ix2) makes that variable resistor (RL) is more and more littler.
Please with reference to Fig. 6 C, it is depicted as gain adjustment control circuit at the interval adjustment sketch map of low gain adjustment.Adjust voltage (VAGC) when rising to Vs3 by Vs2 when gain, (Ix3) is cumulative for the 3rd adjustable current source.That is to say that the electric current (Ix3) of the 6th n type field effect transistor M 3C that flows through is cumulative, and the electric current of the 5th n type field effect transistor M 2C that flows through decrescence (Ic4-Ix3).At this moment, electric current guiding control signal (Vctrl) can be increasing, and then make that transduction parameter gm3 is increasing and transduction parameter gm2 is more and more littler.
From the above; The present invention will gain in gain adjustment range and will be adjusted in the process (Vs1 is changed to Vs3) of minimum value by maximum; When the high-gain adjustment region, be utilize to reduce the gain that the resistance value of variable resistor (RL) is come step-down amplifier, and; In the time of in the low gain adjustment region, be that utilization improves transduction parameter gm3 and reduces the gain that transduction parameter gm2 comes step-down amplifier.In like manner, will gain is adjusted in the peaked process (Vs3 is changed to Vs1) by minimum value, also is to utilize above-mentioned mode to control so repeat no more.
In addition; Though embodiments of the invention are to be connected to form differential rightly with the first bipolar junction transistor Q1A and the second bipolar junction transistor Q1B, also can utilize other transistors (for example field-effect transistor) to replace easily these those skilled in the art.
Advantage of the present invention is the adjustable grain low noise amplifier that proposes a kind of high linearity; In the time of in the high-gain adjustment region; Utilize the resistance value that changes variable resistor (RL) to change Amplifier Gain, in the time of in the low gain adjustment region, change transduction parameter gm3 and gm2 and change gain.Therefore, utilize amplifier of the present invention that low noise figure can be provided when low gain.And, compared to the well-known well-known high-linearity variable gain amplifier, the same noise index (NF), it can provide a larger gain adjustment range, thus achieving lower power are consumed, the smaller the layout area and longer Low linearity requirements and other effects.
In sum; Though the present invention discloses as above with preferred embodiment; Right its is not that any those of ordinary skills are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the scope that claims define.
Claims (14)
1. adjustable grain low noise cascode amplifier comprises:
One gain adjustment control circuit; In order to receive a gain adjustment voltage; And then produce resistance value adjustment signal and electric current guiding control signal, wherein when voltage is adjusted in this gain in a high-gain adjustment region, adjust this resistance value adjustment signal and fixing this electric current guiding control signal; When voltage is adjusted in this gain in a low gain adjustment region, adjust this electric current guiding control signal and fixing this resistance value adjustment signal;
Wherein this gain adjustment control circuit comprises: a control unit, resistance value adjustment circuit and electric current guiding control circuit; Wherein, When voltage is adjusted in this gain in this high-gain adjustment region; This control unit is controlled this resistance value adjustment circuit and is changed this resistance value adjustment signal, and when voltage was adjusted in this gain in this low gain adjustment region, this electric current guiding control circuit of this control unit control changed this electric current guiding control signal;
One load circuit comprises a plurality of variable resistors, in order to adjust said a plurality of variable-resistance resistance value according to this resistance value adjustment signal;
One current guiding circuit utilizes a plurality of current paths to be connected to this load circuit, and in order to adjust the current ratio between said a plurality of current path according to this electric current guiding control signal, wherein this current guiding circuit has the differential wave output; And
One input circuit is connected to this current guiding circuit, and wherein this input circuit has the differential wave input.
2. adjustable grain low noise cascode amplifier as claimed in claim 1; Wherein, When voltage is adjusted in this gain in this high-gain adjustment region; Reduce a plurality of variable-resistance resistance values described in this load circuit in order to utilize this resistance value to adjust signal, and then downgrade a yield value of this adjustable grain low noise cascode amplifier.
3. adjustable grain low noise cascode amplifier as claimed in claim 1; Wherein, When voltage is adjusted in this gain in this low gain adjustment region; In order to utilize this electric current guiding control signal to adjust the current ratio between said a plurality of current path, make that a plurality of transistorized transduction parameter generating change in this current guiding circuit, and then adjust this yield value of this adjustable grain low noise cascode amplifier.
4. adjustable grain low noise cascode amplifier comprises:
First bipolar junction transistor;
Second bipolar junction transistor, the base stage of this first bipolar junction transistor and this second bipolar junction transistor are a differential wave input;
Two emitter resistances, first end of said emitter resistance is connected to the emitter of this first bipolar junction transistor and this second bipolar junction transistor respectively, and second end of said emitter resistance is connected to a first node;
One first current source is connected between this first node and the earth terminal;
One first variable resistor;
One the one n type field-effect transistor, its grid receives a grid voltage, its source electrode is connected to the collector electrode of this first bipolar junction transistor, and, its drain electrode with a supply voltage between be connected this first variable resistor;
One the 2nd n type field-effect transistor, its grid receive electric current guiding control signal, and its source electrode is connected to the collector electrode of this first bipolar junction transistor, and its drain electrode is connected to this supply voltage;
One the second adjustable resistance;
One the 3rd n type field-effect transistor, its grid receive this electric current guiding control signal, and source electrode is connected to the collector electrode of this second bipolar junction transistor, and its drain electrode is connected to this supply voltage;
One the 4th n type field-effect transistor, its grid receives this grid voltage, and its source electrode is connected to the collector electrode of this second bipolar junction transistor, and, be connected this second adjustable resistance between its drain electrode and this supply voltage; And
One gain adjustment control circuit is adjusted voltage in order to receive a gain, and then produces this electric current guiding control signal, and resistance value adjustment signal is in order to adjust this first variable resistor and this second adjustable resistance; This gain adjustment control circuit is when voltage is adjusted in this gain in a high-gain adjustment region; Adjust this resistance value adjustment signal and fixing this electric current guiding control signal; When voltage is adjusted in this gain in a low gain adjustment region, adjust this electric current guiding control signal and fixing this resistance value adjustment signal; This gain adjustment control circuit comprises: a control unit, resistance value adjustment circuit and electric current guiding control circuit; When voltage is adjusted in this gain in this high-gain adjustment region; This resistance value adjustment circuit of this control unit control changes this resistance value adjustment signal; And when voltage was adjusted in this gain in this low gain adjustment region, this electric current guiding control circuit of this control unit control changed this electric current guiding control signal;
Wherein, the drain electrode of a n type field-effect transistor and the 4th n type field-effect transistor becomes a differential wave output.
5. adjustable grain low noise cascode amplifier as claimed in claim 4; Comprise also that wherein one second current source is connected between this supply voltage and this first bipolar junction transistor collector electrode; And one the 3rd current source is connected between this supply voltage and this second bipolar junction transistor collector electrode.
6. adjustable grain low noise cascode amplifier as claimed in claim 4, wherein this first variable resistor is one the one p type field-effect transistor, and its grid is in order to receive this resistance value adjustment signal, and its source electrode is these first variable-resistance two ends with drain electrode.
7. adjustable grain low noise cascode amplifier as claimed in claim 4, wherein this first variable resistor comprises:
One the 2nd p type field-effect transistor, its grid is in order to receive this resistance value adjustment signal, and its source electrode is these first variable-resistance two ends with drain electrode; And
One the 3rd p type field-effect transistor, its source electrode are connected to the 2nd p type field-effect transistor source electrode, and its drain electrode and grid are connected to the drain electrode of the 2nd p type field-effect transistor.
8. adjustable grain low noise cascode amplifier as claimed in claim 4, wherein this first variable resistor comprises:
One the 4th p type field-effect transistor, its grid receive this resistance value adjustment signal, and its source electrode is these first variable-resistance two ends with drain electrode; And
One polysilicon resistance, its two ends are connected to the source electrode and the drain electrode of the 4th p type field-effect transistor respectively.
9. adjustable grain low noise cascode amplifier as claimed in claim 4; Wherein when voltage is adjusted in this gain in this high-gain adjustment region; Reduce the resistance value of this first variable resistor and this second adjustable resistance with this resistance value adjustment signal, and then downgrade this adjustable grain low noise cascode Amplifier Gain value.
10. adjustable grain low noise cascode amplifier as claimed in claim 4; Wherein, When voltage is adjusted in this gain in this low gain adjustment region; In order to utilizing this electric current guiding control signal to reduce the transduction parameter of a n type field-effect transistor and the 4th n type field-effect transistor, and increase the transduction parameter of the 2nd n type field-effect transistor and the 3rd n type field-effect transistor, and then downgrade this yield value of this adjustable grain low noise cascode amplifier.
11. adjustable grain low noise cascode amplifier as claimed in claim 4, wherein this resistance value adjustment circuit comprises:
One operational amplifier;
One reference resistance is connected between the first input end of this supply voltage and this operational amplifier;
One first adjustable current source is connected between the first input end and this earth terminal of this operational amplifier;
One the 5th p type field-effect transistor, its source electrode is connected to this supply voltage, and its grid is connected to the output of this operational amplifier and adjusts signal in order to receive this resistance value, and its drain electrode is connected to second input of this operational amplifier; And
One second adjustable current source is connected between second input and this earth terminal of this operational amplifier.
12. adjustable grain low noise cascode amplifier as claimed in claim 11, wherein this electric current guiding control circuit comprises:
One the 5th n type field-effect transistor, its drain electrode is connected to this supply voltage, and its grid receives this grid voltage, and its source electrode is connected to a Section Point;
One the 6th n type field-effect transistor, its drain electrode is connected with grid, and produces this electric current guiding control signal, and its source electrode is connected to this Section Point;
One the 3rd adjustable current source is connected between the drain electrode of this supply voltage and the 6th n type field-effect transistor; And
One the 4th current source is connected between this Section Point and this earth terminal.
13. adjustable grain low noise cascode amplifier as claimed in claim 12; Wherein when voltage is adjusted in this gain in this high-gain adjustment region; This control unit is in order to adjust a current ratio of this first adjustable current source and this second adjustable current source; And, when voltage is adjusted in this gain in this low gain adjustment region, this control unit adjustment the 3rd adjustable current source.
14. adjustable grain low noise cascode amplifier as claimed in claim 4, this adjustable grain low noise cascode amplifier is applied to a TV tuner.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009102090514A CN101697479B (en) | 2009-10-30 | 2009-10-30 | Adjustable grain low noise amplifier |
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| CN2009102090514A CN101697479B (en) | 2009-10-30 | 2009-10-30 | Adjustable grain low noise amplifier |
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| CN101697479A CN101697479A (en) | 2010-04-21 |
| CN101697479B true CN101697479B (en) | 2012-02-08 |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2474778A (en) * | 2009-10-23 | 2011-04-27 | Sunplus Technology Co Ltd | Highly linear variable-gain low noise cascode amplifier |
| TWI378640B (en) | 2009-10-23 | 2012-12-01 | Sunplus Technology Co Ltd | Variable-gain low noise amplifier |
| CN102780456A (en) * | 2011-05-11 | 2012-11-14 | 上海华虹集成电路有限责任公司 | Low noise amplifier |
| CN104065355A (en) * | 2013-03-19 | 2014-09-24 | 上海华虹宏力半导体制造有限公司 | Fully-differential low-noise amplifier |
| US9263998B2 (en) * | 2013-12-16 | 2016-02-16 | Mstar Semiconductor, Inc. | Broadband single-ended input to differential output low-noise amplifier |
| CN103973249B (en) * | 2014-05-09 | 2017-01-25 | 华为技术有限公司 | Variable gain amplifier |
| US9899961B2 (en) * | 2015-02-15 | 2018-02-20 | Skyworks Solutions, Inc. | Enhanced amplifier efficiency through cascode current steering |
| CN110572533B (en) * | 2019-09-19 | 2024-02-27 | 江西创新科技有限公司 | Electrodeless adjustable band display time-consuming DTV digital television amplifier |
| CN110995170B (en) * | 2019-12-25 | 2023-04-21 | 武汉邮电科学研究院有限公司 | High dynamic range transimpedance amplifier |
| CN113839633B (en) * | 2021-09-03 | 2024-01-23 | 厦门优迅高速芯片有限公司 | Gain-adjustable amplifier |
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| CN1661910A (en) * | 2004-02-24 | 2005-08-31 | 络达科技股份有限公司 | Gain control circuit and relevant amplifier |
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| CN1661910A (en) * | 2004-02-24 | 2005-08-31 | 络达科技股份有限公司 | Gain control circuit and relevant amplifier |
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