CN101694513A - Method and device for testing electronic micro-mirror device - Google Patents
Method and device for testing electronic micro-mirror device Download PDFInfo
- Publication number
- CN101694513A CN101694513A CN200910197505A CN200910197505A CN101694513A CN 101694513 A CN101694513 A CN 101694513A CN 200910197505 A CN200910197505 A CN 200910197505A CN 200910197505 A CN200910197505 A CN 200910197505A CN 101694513 A CN101694513 A CN 101694513A
- Authority
- CN
- China
- Prior art keywords
- data frame
- core logic
- logic functions
- signal generator
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a method and a device for testing an electronic micro-mirror device, wherein the test device comprises: a core logic function verification circuit, a high-speed data memory, a control signal generator, a test signal generator and a test signal detector; the test method comprises the following steps: after receiving an instruction, the core logic function verification circuit generates and stores original data frames which are then converted into bit data frames by being computed by the core logic function verification circuit, and signals sent to a tested device are the serialization of the bit data frames; after the tested device receives the serialized bit data frames, units corresponding to the tested device generate setting or resetting; the test signal detector detects the setting or resetting one by one and stores the setting and resetting in the data memory, thus obtaining bit effect data frames so as to judge whether the tested device functions are normal and judge the position of fault points. According to the invention, an effective detection and verification tool that is not possessed by the current commercial IC test equipment is provided for the batch production of the electronic micro-mirror device.
Description
Technical field
The present invention relates to technical field of measurement and test, the test of particularly a kind of electronics micro mirror integrated circuit (IC) chip (being called for short the AMD chip) is apparatus and method.
Background technology
Digital Micromirror Device is a kind of microelectronics manufacturing that relates to, microelectron-mechanical, integrated circuit (IC) design, Flame Image Process, a kind of hi-tech element that precision optics and high speed data transfer and high-speed data receive and handle; Its application comprises: (the 3D location of precision optical machinery), military (satellite imagery night vision device, the fighter plane helmet show), health care (endoscope etc.) are made in communication system (as optical fiber backbone network switch core devices), consumer electronics (televisor, projector, stereo display and following 3G mobile TV display unit), industry; But Digital Micromirror Device also has its weak point, is exactly its interface driving circuit frequency of operation very high (750Mhz), and the test of integrated circuit is difficulty very, and the test of batch process is more difficult; There is not special equipment can supply to select for use on the market.
DMD is the abbreviation of (digital micro-mirror device) digital micro-mirror semiconductor devices, is the patented technology of U.S. De Kesasi instrument company; Utilize the DMD technology to carry out digital light and handle, be i.e. (Digital Light Processing
TM) (be called for short DLP
TM), in the new method of having started a demonstration aspect information projection and the demonstration, be characterized in reflectivity, seamless image, digitizing, littler/lighter, brighter; The AMD chip then is the patented technology of U.S. Silicon quest company, and it also is a kind of digital micro-mirror semiconductor devices, but design technology is different with DMD with chip structure; DMD is similar SRAM structure, and AMD then is similar DRAM structure; In the middle of each micro mirror of DMD aperture is arranged, AMD does not then have; AMD is lower than DMD cost, the AMD chip is before giving user's use, need carry out the DCO of function and performance, because AMD chip periphery interface rate height (750Mhz), hyperchannel LVDS (134 pairs of differential signals), general universal integrated circuit testing tool all can't directly be tested, and is having a strong impact on the widespread use of AMD chip.
Summary of the invention
A kind of method of testing and the device that provide at the difficult problem of test in the AMD chip development process is provided, this device has not only solved the function and the performance test problem of AMD chip, also diagnose a kind of effective means are provided, and then improved production efficiency for fault AMD chip.
The object of the present invention is achieved like this:
A kind of proving installation of electronics micro mirror element, this device comprises:
One core logic functions proof scheme is used for device control and calculates core;
One high-speed data storer is connected to the core logic functions proof scheme, is used to store raw data Frame, bit data Frame and position effect data Frame;
One control signal generator is connected to the core logic functions proof scheme, produces the message exchange signal according to outside input trigger pip;
One measuring signal generator is connected to the core logic functions proof scheme, and sends test massage to tested electronics micro mirror element; Wherein comprise raw data Frame and bit data Frame in the test signal, and bit data Frame carries out the computing gained by raw data Frame;
And a test signal detecting device, be connected to the core logic functions proof scheme, and receive tested electronics micro mirror element return signal;
Described core logic functions proof scheme, high-speed data storer, control signal generator, measuring signal generator and test signal detecting device are loaded among a slice programming device (FPGA).
Described control signal generator connects a low-speed serial interface.
Be connected with 256 super wide data buss between described core logic functions proof scheme and control signal generator, the test signal detecting device.
A kind of method of testing of electronics micro mirror element, this method comprises the steps:
A) selected tested electronics micro mirror element, and be connected to measuring signal generator and test signal detecting device;
B) the external command signal is transported to the core logic functions proof scheme by the control signal generator, produces raw data Frame and stores the high-speed data storer into;
C) raw data Frame is converted to bit data Frame by the computing of core logic functions proof scheme;
D) bit data Frame after tested signal generator deliver to tested electronics micro mirror element, the signal that tested electronics micro mirror element receives is the serialization of bit data Frame; After tested electronics micro mirror element received serialized bit data Frame, its units corresponding produced set or resets;
E) the test signal detecting device is by detecting the set produced or resetting and it is stored in the high-speed data storer, and effect data Frame must put in place;
F) carry out logical relation by core logic functions proof scheme contraposition effect data Frame and bit data Frame and judge, and provide corresponding indicating signals.
The described external command signal of step b is obtained by the low-speed serial interface.
The present invention produces in batches for the electronics micro mirror element a kind of effective detection and verification tool is provided, and is that other commercial IC test equipment is not available at present.
Description of drawings
Fig. 1 is a proving installation structural representation of the present invention
Fig. 2 is a proving installation user mode system chart of the present invention
Fig. 3 is a method of testing process flow diagram of the present invention
Embodiment
Consult Fig. 1, proving installation of the present invention is when specifically testing, and peripheral microcontroller MCU, test of digital signal source, FPGA configuring chip and the power circuit of connecting constitutes a test macro.
Microcontroller MCU, the effect in system is a bridge extraneous and proving installation, accepts to be distributed to proving installation (FPGA) after extraneous PC sees through test command that USB interface sends, decoding, and test result is turned back to PC.
The test of digital signal source is a DVI receiver, and the digital video signal (it meets the DVI1.0 standard) that the receiving video signals generator produces becomes CMOS (perhaps LVTTL) level signal to it, so that proving installation (FPGA) can receive processing; For the test of electronics micro mirror integrated circuit (IC) chip (AMD) provides a kind of variable dynamic test pattern; It is by R[0:9], G[0:9], B[0:9], clock, Blanking, VS, 34 signals such as HS are formed.
The FPGA configuring chip, hardware setting code (software) burning is loaded into after powering in the proving installation (FPGA) automatically in wherein.
Power circuit, its generation system surveys auxiliary power supply (0.9V, 1.2V, 1.8V, 2.5V, 3.3V and 5V) and tries the various power supplys that electronics micro mirror integrated circuit (IC) chip (AMD) needs, and comprises 1.8v power supply, 6V power supply, 12V power supply, 20VA and 20VB etc.
Consult Fig. 2, proving installation of the present invention is an example with FPGA EP2S180F1508, comprises control signal generator, measuring signal generator, test signal detecting device, core logic functions proof scheme and high-speed data storer;
The control signal generator sees through I2c and links to each other with microcontroller MCU, and reception is also delivered to the core logic functions proof scheme to one command signal, and the trigger pip of sending according to exterior PC produces a switching signal;
Measuring signal generator, its LVDS passage by 134 links to each other with measured device (digital and electronic micro mirror chip (AMD)), and test command and bit data Frame are delivered to AMD, is connected with the core logic functions proof scheme through 256 bus simultaneously; Utilize the hyperchannel LVDS high speed resource of FPGA, solved the problem that general purpose I C tester table cann't be solved;
Return signal detecting device, its return signal that detects tested AMD comprise serial code stream and 13 kinds of test mode indicator signals of one; Serial code stream is organized into an effect data Frame and is sent to the core logic functions proof scheme, and 13 kinds of test mode indicator signals are also encoded again delivers to the core logic functions proof scheme;
The core logic functions proof scheme, it is the maincenter of whole device, link to each other with the control signal generator by a bit-serial bus, accept the switching signal of its generation, a core logic functions circuit interpreted command and a data bitmap Frame (bitplane-t) who is stored in the data-carrier store take out, and deliver to the test signal generator in sequence; Accept return signal detecting device serial code stream simultaneously and be organized into an effect data Frame, and be stored in data-carrier store, one Frame is a position effect data Frame after (bitplane-r) receive completely, the logical relation that compares bitplane-t and bitplane-r by turn, if meet specific function, then send normally functioning information, otherwise send parafunctional information to the control signal generator to the control signal generator; If receive the order of the diagnosis that the control signal generator sends this moment, then calculate and the fault location point at once, send fault details to the control signal generator.
It is a DVI receiver that this test macro is provided with the test of digital signal source, (test pattern) can be input to the core logic functions proof scheme by the external testing signal, by its storage with the Installed System Memory reservoir in as raw data Frame, can support to test the test of different test signals.
Consult Fig. 3, method of testing flow process of the present invention: after system powers on, the automatic load module of FPGA configuring chip, and enter holding state S1; The USB of microcontroller (MCU) receives the order of exterior PC, and send to proving installation (FPGA), it may be that test data is loaded (raw data Frame renewal), it also can be the order of measured device (being called for short the AMD chip) being carried out certain functional test, the core logic functions proof scheme takes orders, and raw data Frame is loaded into data-carrier store, enter the S2 state; Then the core logic functions proof scheme is converted to raw data Frame bit data Frame and deposits in data-carrier store, enters the S3 state; The core logic functions proof scheme is changed to bit data Frame and reorganizes and to be the data layout of 256 bit wides and to deliver to measuring signal generator depositing in data-carrier store, enters the S4 state; The backspace signal of the tested AMD that the test signal detecting device received gets position effect data Frame and deposits in data-carrier store through computing, enters the S5 state; The logical relation between bit data Frame and the position effect data Frame is compared in the checking of core logic functions proof scheme, enters the S6 state; Whether function is normal to judge measured device (being called for short the AMD chip), and normally then the sending function normal signal enters the S71 state to MCU, and undesired then sending function abnormal signal enters the S72 state to MCU; Be used for diagnosis if receive diagnostic command then send record data, enter the S8 state; Finish, get back to holding state S1.
Claims (5)
1. the proving installation of an electronics micro mirror element is characterized in that this device comprises:
One core logic functions proof scheme is used for device control and calculates core;
One high-speed data storer is connected to the core logic functions proof scheme, is used to store raw data Frame, bit data Frame and position effect data Frame;
One control signal generator is connected to the core logic functions proof scheme, produces the message exchange signal according to outside input trigger pip;
One measuring signal generator is connected to the core logic functions proof scheme, and sends test massage to tested electronics micro mirror element; Wherein comprise raw data Frame and bit data Frame in the test signal, and bit data Frame carries out the computing gained by raw data Frame;
And a test signal detecting device, be connected to the core logic functions proof scheme, and receive tested electronics micro mirror element return signal;
Described core logic functions proof scheme, high-speed data storer, control signal generator, measuring signal generator and test signal detecting device are loaded among a slice programming device (FPGA).
2. proving installation according to claim 1 is characterized in that the control signal generator connects a low-speed serial interface.
3. proving installation according to claim 1 is characterized in that being connected with 256 super wide data buss between described core logic functions proof scheme and the measuring signal generator.
4. the method for testing of an electronics micro mirror element is characterized in that this method comprises the steps:
A) selected tested electronics micro mirror element, and be connected to measuring signal generator and test signal detecting device;
B) the external command signal is transported to the core logic functions proof scheme by the control signal generator, produces raw data Frame and stores the high-speed data storer into;
C) raw data Frame is converted to bit data Frame by the computing of core logic functions proof scheme;
D) bit data Frame after tested signal generator deliver to tested electronics micro mirror element, the signal that tested electronics micro mirror element receives is the serialization of bit data Frame; After tested electronics micro mirror element received serialized bit data Frame, its units corresponding produced set or resets;
E) the test signal detecting device detects the set that is produced by turn or resets and it is stored in the high-speed data storer, and effect data Frame must put in place;
F) carry out logical relation by core logic functions proof scheme contraposition effect data Frame and bit data Frame and judge, and provide corresponding indicating signals.
5. method of testing according to claim 4 is characterized in that the described external command signal of step b is obtained by the low-speed serial interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197505A CN101694513A (en) | 2009-10-21 | 2009-10-21 | Method and device for testing electronic micro-mirror device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197505A CN101694513A (en) | 2009-10-21 | 2009-10-21 | Method and device for testing electronic micro-mirror device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101694513A true CN101694513A (en) | 2010-04-14 |
Family
ID=42093495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910197505A Pending CN101694513A (en) | 2009-10-21 | 2009-10-21 | Method and device for testing electronic micro-mirror device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101694513A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103327358A (en) * | 2012-03-21 | 2013-09-25 | 安凯(广州)微电子技术有限公司 | Method and device for chip verification |
| CN105578179A (en) * | 2016-01-04 | 2016-05-11 | 厦门理工学院 | System and method for detecting display frame rate of DMD (Digital Micro-mirror Device) |
| CN109669117A (en) * | 2019-01-22 | 2019-04-23 | 华东师范大学 | A kind of adjustable difference LVDS test device of amplitude-frequency |
| CN113419159A (en) * | 2021-05-31 | 2021-09-21 | 歌尔光学科技有限公司 | Testing method, testing device and testing circuit of flexible circuit board |
-
2009
- 2009-10-21 CN CN200910197505A patent/CN101694513A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103327358A (en) * | 2012-03-21 | 2013-09-25 | 安凯(广州)微电子技术有限公司 | Method and device for chip verification |
| CN105578179A (en) * | 2016-01-04 | 2016-05-11 | 厦门理工学院 | System and method for detecting display frame rate of DMD (Digital Micro-mirror Device) |
| CN105578179B (en) * | 2016-01-04 | 2018-11-13 | 厦门理工学院 | The system and method for detecting DMD display frame rates |
| CN109669117A (en) * | 2019-01-22 | 2019-04-23 | 华东师范大学 | A kind of adjustable difference LVDS test device of amplitude-frequency |
| CN109669117B (en) * | 2019-01-22 | 2023-09-26 | 华东师范大学 | Amplitude frequency adjustable differential LVDS testing device |
| CN113419159A (en) * | 2021-05-31 | 2021-09-21 | 歌尔光学科技有限公司 | Testing method, testing device and testing circuit of flexible circuit board |
| CN113419159B (en) * | 2021-05-31 | 2022-10-18 | 歌尔光学科技有限公司 | Testing method, testing device and testing circuit of flexible circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6594972B2 (en) | Embedded universal serial bus (USB) debugging (EUD) for multi-interface debugging in electronic systems | |
| CN102004219B (en) | Infrared focal plane array detector simulation device and method | |
| KR20150055250A (en) | Timing controller, and display system including the same | |
| CN101482843A (en) | On-chip circuitry for bus validation | |
| CN101694513A (en) | Method and device for testing electronic micro-mirror device | |
| US9786233B2 (en) | Electronic label system | |
| CN106851183B (en) | Multi-channel video processing system and method based on FPGA | |
| US20180156868A1 (en) | Testing a board assembly using test cards | |
| US20130283066A1 (en) | Test system for reset and power on or off of computer | |
| JP2020524334A (en) | Device and method for diagnosing communication abnormality | |
| US20190197929A1 (en) | Driving apparatus of display panel and operation method thereof | |
| CN103376894A (en) | Laser indication sharing method and system | |
| CN113031695A (en) | Control circuit device, electronic apparatus, control method, and readable storage medium | |
| CN102868906B (en) | test architecture, method and system | |
| CN102004686B (en) | Current measuring device and computer system thereof | |
| WO2020019682A1 (en) | Laser projection module, depth acquisition apparatus and electronic device | |
| CN103365735A (en) | Transmission interface and method for determining transmission signal | |
| CN114563017A (en) | Navigation performance test system and method for strapdown inertial navigation device | |
| CN103761384B (en) | Device and method capable of generating camera data in various formats | |
| CN104753613A (en) | Serial port communication testing device and testing method | |
| US20120050612A1 (en) | Video output supervisor | |
| CN116991647B (en) | Mask star detector interface test equipment, method and device and storage medium | |
| WO2024112352A1 (en) | Flexible bus communication | |
| CN109256072A (en) | The lighting test system of display device | |
| JP2001237842A (en) | Fault diagnosis method for multiplex communication equipment and multiplex communication equipment adopting the method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20100414 |