CN101692647A - Tunnel forwarding system in which IPv4 packets are encapsulated by IPv6 head in router - Google Patents

Abstract

The invention provides a tunnel forwarding system in which IPv4 (Internet Protocol version 4) packets are encapsulated by an IPv6 (Internet Protocol version 6) head in a router and belongs to the technical field of IPv6 routers. The invention is characterized in that the tunnel forwarding system consists of an FPGA-based (Field Programmable Gate Array) tunnel processing circuit, two CAMs (Content Addressable Memories) in cascaded connection, two one-port SRAMs (Static Random Access Memories), a double-port SRAM and a CPU control unit with the supported capacity of a V6 routing table being 64k*288bits in the maximum and the guaranteed line rate of forwarding being 3.2Gbit/s when the clock frequency is 100MHz. A routing lookup table constructed by the CAM supports the dynamic allocation of the entry number and is responsible for the read-write and maintenance of the routing table at the same time. If IP data packets received by the tunnel forwarding system are V4 packets, the V4 packets are encapsulated with a V6 packet head to form V6 tunneling packets; if the IP data packets are V6 data packets, the V6 data packets dispense with the transformation; then, the lookup information of the packets are extracted, and the routing lookup is carried out; and the packets are processed according to the returned results: forwarding on a V4 or V6 basis, and turning over to the CPU to process or discard.

Description

A Tunnel Forwarding System Encapsulating IPv4 Packet with IPv6 Header in Router

technical field

The tunnel forwarding system adopting IPv6 header to encapsulate IPv4 packet in router belongs to the technical field of IPv6 high-performance core router of next generation Internet.

Background technique

The IPv6 protocol solves the problems of IPv4 protocol address exhaustion, insufficient security and poor mobility. The transition from IPv4 to IPv6 is a gradual and lengthy process, and the two will coexist for quite a long time. With the large-scale development of IPv6, a pure IPv6 backbone network appears, and a large number of services are introduced on IPv6. Due to the incompatibility between IPv6 and IPv4 protocols, existing network users will not be able to interconnect with the resource-rich IPv4 network after migrating to a pure IPv6 network. This makes the process of migrating the users and resources of the original IPv4 network to the IPv6 network very slow, resulting in a low utilization rate of the established pure IPv6 network. In order to promote the transition of the IPv4-IPv6 network, there is an urgent need for a tunneling technology or protocol conversion technology that can realize mutual access between IPv4 and IPv6 networks, and transmit IPv4 data packets through the IPv6 network.

At present, the tunneling technology using IPv4 protocol to encapsulate IPv6 packets is widely used and relatively mature, while the tunneling technology using IPv6 protocol to encapsulate IPv4 packets is not mature enough. At present, there is no unified international standard for tunneling technology using IPv6 header to encapsulate IPv4 packets , Most of the tunneling technologies on the market that use IPv6 headers to encapsulate IPv4 packets are implemented by software. The architectures of the encapsulation are different, and the speed is low, which cannot meet the actual application needs of high-speed networks.

The invention realizes the tunnel forwarding of the IPv4 packet encapsulated by the IPv6 header in the router, solves the problem that the IPv4 network realizes interconnection through the pure IPv6 backbone network, the method is simple and efficient, and the encapsulation and forwarding speed reaches 3.2Gbit/s.

FPGA (Field Programmable Gate Array) is a large-scale programmable digital integrated circuit device that began to be used in the late 1980s. It makes full use of computer-aided design technology for device development and application. With the help of computers, users can not only design ASIC chips by themselves, but also perform function simulation and real-time simulation on the computer to find problems in time, adjust circuits, and improve design solutions. In this way, the designer does not need to manually connect the circuit, debug and verify, and only needs to operate on the computer for a short time to design an ideal circuit that is almost the same as the actual system. Moreover, the FPGA device adopts a standardized structure, small size, high integration, low power consumption, fast speed, and can be programmed repeatedly indefinitely. Therefore, it has become the first choice for scientific research product development and miniaturization, and its application is extremely wide.

CAM (Content Addressable Memory) is a special kind of memory, it compares the input data with all the data items stored in CAM at the same time, quickly judges whether the input data matches the data items stored in CAM, and gives the data item correspondence Address and matching information. CAM is currently the most used device to achieve fast routing lookup. CAM can complete the exact matching search of keywords within a limited number of hardware clock cycles. A lookup result can be pipelined every hardware clock cycle.

TCAM (Ternary Content Addressable Memory) is also a kind of CAM, but each of its storage bits has three states: 0, 1 or X (don't care), and each entry contains a value bit string and a mask bit string, so it can Used to determine the longest prefix match.

Contents of the invention

The purpose of the present invention is to provide a tunnel forwarding system that adopts IPv6 header to encapsulate IPv4 packets in a router, and the specific realization adopts FPGA and CAM technology. The router of the invention can connect the IPv6 backbone network and the IPv4 isolated island, and realize the transparent transmission between the IPv4 isolated islands through the IPv6 backbone network.

Features of the present invention:

Contains: a tunnel processing circuit integrated on the FPGA chip, SRAM single-port memory, SRAM dual-port memory, CAM content addressable memory and CPU control unit, of which:

The tunnel processing circuit includes: IP packet input interface circuit, packet filtering circuit, packet input queue memory FIFO, IPv6 protocol encapsulation circuit, IPv6 packet queue memory FIFO, packet related information extraction circuit, retrieval instruction queue memory FIFO, CAM control Circuit, retrieval result queue memory FIFO, IPv6 data packet related information queue memory FIFO, IPv6 data packet memory RAM, packet sending circuit, CAM maintenance instruction queue memory FIFO, 0th handover packet queue memory FIFO, 1st handover packet Queue memory FIFO, handover packet sending circuit, and CPU interface circuit, wherein:

The IP packet input interface circuit, the input end receives the data ready signal and the data bus signal output by the upper physical and data link layer processing circuit, and outputs the read signal to the upper physical and data link layer processing circuit, and the IP packet input interface circuit data The output terminal is connected to the input terminal of the packet filtering circuit, counts the input and output IPv4 and IPv6 packet header signals and packet tail signals respectively, sends the packet header and packet tail count output signal to the CPU interface circuit, and receives the reset signal input by the CPU interface circuit and counter clear signal;

Packet filtering circuit, the input end is connected to the IP packet input interface circuit, and is also connected to the 0th handover packet queue memory FIFO and the packet input queue memory FIFO output almost full signal, and the output end is respectively connected to the 0th handover packet queue memory The input end of the FIFO and the input end of the packet input queue memory FIFO are connected, and the input and output packet header signals and packet tail signals are counted, and sent to the CPU interface circuit, and simultaneously receive the reset signal and the counter clearing signal input by the CPU interface circuit;

The packet input queue memory FIFO is a first-in-first-out queue memory with a data width of 36 bits. The input end is connected to the IP packet output end of the above-mentioned packet filter circuit, the read signal comes from the IPv6 protocol encapsulation circuit, and the reset signal comes from the CPU interface circuit;

The IPv6 protocol encapsulation circuit, the input end is connected with the packet input queue memory FIFO, the output end is connected with the IPv6 packet queue memory FIFO, in addition the input end also receives the nearly full signal output by the IPv6 packet queue memory FIFO, and the IPv6 protocol encapsulation circuit is to the input and output The packet header signal and packet tail signal are counted and sent to the CPU interface circuit, and at the same time receive the reset signal and counter clear signal input by the CPU interface circuit;

The IPv6 packet queue memory FIFO is a first-in-first-out queue memory with a data width of 40 bits. The data input end is connected to the above-mentioned IPv6 protocol encapsulation circuit, the read input signal is connected to the read output of the packet-related information extraction circuit, and the output end is related to the packet. The information extraction circuit is connected, and the reset signal comes from the CPU interface circuit;

Packet-related information extraction circuit, the input end is connected to the output end of the IPv6 packet queue memory, and the output end is respectively connected to the retrieval command queue storage FIFO, the IPv6 data packet memory RAM, and the IPv6 data packet related information queue memory FIFO, and the input and output packet header signals Count with the end-of-packet signal, send it to the CPU interface circuit, and receive the reset signal and counter clear signal input by the CPU interface circuit at the same time;

The retrieval instruction queue memory FIFO is a first-in-first-out queue memory with a data width of 100 bits. The data input terminal is connected to the above-mentioned package-related information extraction circuit, the read input signal is connected to the read output of the CAM control circuit, and the data output terminal is connected to the CAM control circuit. circuit connected;

CAM control circuit, the input terminal is connected to the FIFO output terminal of the retrieval command queue memory and the FIFO output terminal of the CAM maintenance command queue memory respectively, and the CAM memory read and write control command bus signal output by the CAM control circuit and the bidirectional data request bus REQDATA signal are connected to the CAM memory , the CAM control circuit is connected to the data bus of the SRAM single-port memory, the input terminal of the CAM control circuit is also connected to the read confirmation signal output by the CAM memory, the search matching signal, and the search output effective signal, and the retrieval information output terminal output by the CAM control circuit is connected to the retrieval information output terminal. The result queue memory FIFO is connected. In addition, the read signal of the CAM control circuit is connected with the read input end of the retrieval instruction queue memory FIFO and the read input end of the CAM maintenance instruction queue memory FIFO. The output end of the CAM control circuit is connected with the CPU interface circuit, and the routing table The saved table items are sent to the CPU interface circuit, and the CAM control circuit counts the number of IPv6 routing queries and the information of query hits, sends these information as query status information to the CPU interface circuit, and receives the reset signal and counter input from the CPU interface circuit clear signal;

The retrieval result queue memory FIFO is a first-in-first-out queue memory with a data width of 148 bits. The data input terminal is connected to the output of the CAM control circuit, the read input signal is connected to the read output of the packet transmission circuit, and the data output terminal is connected to the packet transmission circuit. The input terminal is connected;

The IPv6 data packet-related information queue memory FIFO is a first-in-first-out queue memory with a data width of 60 bits. The data input terminal is connected to the above-mentioned packet-related information extraction circuit, and the read input signal is connected to the read output of the packet transmission circuit. The data output terminal Connected to the packet sending circuit;

CAM maintenance instruction queue memory FIFO is a first-in-first-out queue memory with a data width of 90 bits. The data input terminal is connected to the CPU interface circuit, the read input signal is connected to the read signal output by the CAM control circuit, and the data output terminal is connected to the CAM control circuit. The data input terminal is connected;

The packet sending circuit sends a read signal to the retrieval result queue memory FIFO and the IPv6 packet-related information queue memory FIFO respectively, and is connected to the output end of the retrieval result queue memory FIFO and the IPv6 data packet-related information queue memory FIFO, and the packet sending circuit outputs The read signal and read address are connected to the IPv6 data packet memory RAM, the data output end of the IPv6 data packet memory RAM is connected to the packet sending circuit, and the output of the packet sending circuit is also connected to the first handover packet queue memory FIFO and the uplink outside the FPGA chip The FIFOs are connected, and the packet sending circuit counts the input and output IPv4, IPv6 packet header signals and packet tail signals respectively, and sends them to the CPU interface circuit, and simultaneously receives the reset signal and the counter clearing signal input by the CPU interface circuit;

The IPv6 data packet memory RAM is a dual-port FPGA on-chip read-write memory, with a data write port and a data output port, the data write port is connected with the IPv6 data output port of the packet-related information extraction circuit, and all read ports The signal is connected to the packet sending circuit, the data width of the IPv6 packet memory RAM is 36 bits, and the read and write ports have 14 address lines respectively;

The 0th handover packet queue memory FIFO is a first-in first-out queue memory with a data width of 36 bits. The data input terminal is connected to the above-mentioned packet filter circuit, and the read input signal is connected to the read output of the handover packet sending circuit, and the data output The terminal is connected to the handover packet sending circuit;

The first handover packet queue memory FIFO is a first-in-first-out queue memory with a data width of 36 bits. The data input terminal is connected to the packet sending circuit, the read input signal is connected to the read output of the handover packet sending circuit, and the data output terminal It is connected with the handover packet sending circuit;

The handover packet sending circuit, the input end is connected to the 0th handover packet queue memory FIFO and the first handover packet queue memory FIFO, the data output end is connected to the data input end of the SRAM dual-port memory, and the handover packet sending circuit sends The CPU interrupt signal, the start address and end address of the SRAM dual-port memory data, the length signal output of the data to be transmitted in the SRAM dual-port memory are connected to the CPU interface circuit, and the CPU interface circuit outputs the CPU response signal to the handover packet sending circuit The input terminal of the handover packet transmission circuit counts the input and output IPv4, IPv6 packet header signals and packet tail signals respectively, and sends them to the CPU interface circuit, and simultaneously receives the reset signal and the counter clear signal input by the CPU interface circuit;

The CPU interface circuit is connected to each circuit inside the tunnel processing circuit realized by FPGA, and receives the IPv4 and IPv6 input and output packet header signals and packet tail signal counts input by each circuit, as well as the query status count of the CAM control circuit. The CPU interface circuit and the FPGA chip The CPU address bus, data bus, and read-write control signal of the external CPU control unit are connected, the interrupt signal output is connected with the interrupt input of the CPU control unit, and the CPU interface circuit is also connected with the address bus, data bus, and The read and write control signals are connected, the CPU interface circuit receives the reset signal input by the CPU control unit, and transmits the reset signal to other circuits in the FPGA, and transmits the reset signal to the IP packet input interface circuit, packet filter circuit, and IPv6 protocol encapsulation circuit, packet-related information extraction circuit, CAM control circuit, handover packet sending circuit, packet sending circuit, and the CPU interface circuit is also connected to the data input end of the CAM maintenance instruction queue memory FIFO, and receives the routing table entry data output by the CAM control circuit , receiving the SRAM dual-port memory data start address and termination address output by the packet sending circuit, the length of the data to be transmitted in the SRAM dual-port memory, and the interrupt request information, and also sending the CPU interrupt response indication signal to the packet sending circuit;

The packet filtering circuit is a circuit assembly, wherein: the input IP packet data register is connected to the output end of the input interface circuit of the IP packet; the output end of the input IP packet data register is respectively connected to the IPv4 packet register and the IPv6 packet register connected; the output end of the IPv4 data packet register is connected with the input end of the IPv4 data packet delay register group, the IPv4 packet header checksum register, the time-to-live register, the packet type register, and the state control machine respectively, and also receives the output of the state control machine; The output end of the IPv4 packet delay register group is connected to the input end of the data selector A; the input end of the IPv4 packet header checksum generator is connected to the output of the IPv4 header checksum register and the output of the time-to-live update register respectively; the time-to-live register The output terminal of the subtractor A is connected to the input terminal of the state control machine, the output terminal of the subtractor A is connected to the input terminal of the time-to-live update register, and the output terminals of the time-to-live update register are respectively connected to the IPv4 data The packet header checksum generator is connected to the state control machine; the input end of the data selector A is respectively connected to the output end of the IPv4 packet delay register group, the output end of the IPv4 packet header checksum generator, and the output end of the state control machine Connected, the output end of data selector A is connected with the updated IPv4 packet register input end;

The output end of IPv6 data packet register is connected with the input end of IPv6 data packet delay register group, hop count register, next head register, IPv6 purpose address register, state control machine respectively, also receives the output of state control machine simultaneously; Hop count register The output end of the subtractor B is connected with the input end of the subtractor B and the state control machine, and the output end of the hop update register is also connected with the state control machine; the output end of the subtractor B is connected with the input end of the hop update register ; The input end of data selector B is connected with the output end of IPv6 data packet delay register group, hop update register, state control machine respectively, and the output end of data selector B is connected with the updated IPv6 data packet register input end; The input end of a header register is connected with the output end of the IPv6 packet register, and the output end is connected with the state control machine; the output end of the IPv6 destination address register is connected with the input end of the comparator, and the other input end of the comparator is connected with the IPv6 The output end of the address register is connected; the output end of the comparator is connected with the input end of the state control machine; the input end of the router IPv6 address register is connected with the output of the CPU interface circuit;

The input end of data selector C links to each other with the output end of the IPv4 data packet register after updating, the IPv6 data packet register after updating, the state control machine and the nearly full signal of packet input queue memory FIFO are connected, the output of data selector C Terminals are respectively connected to the 0th handover packet queue memory FIFO and packet input queue memory FIFO, and the output terminals of the packet header signal and packet tail signal of the data selector C are also connected to the input terminal of the counter; the counter receives the counter output by the CPU interface circuit Clear the signal, and transmit the count signal of the header and tail signal to the input end of the CPU interface circuit;

The IPv6 protocol encapsulation circuit is a circuit assembly, wherein: the packet input queue memory FIFO interface circuit, the data input end is connected with the data output end of the packet input queue memory FIFO, the output read signal and the read input signal of the packet input queue memory FIFO Connected, the control input and output ends are connected to the state control machine circuit; the IPv4 packet header data register, the input end is connected to the output end of the FIFO interface circuit of the packet input queue memory and the output end of the state control machine circuit, and one output end is connected to the IPv4 packet header to IPv6 tunnel packet header circuit Connected, the other output end is connected with the input end of the multiplex data selector circuit; the IPv4 load data register, the input end is connected with the output end of the packet input queue memory FIFO interface circuit, and the output end is connected with the input end of the multiplex data selector circuit; IPv6 The data register, the input end is connected with the output end of the FIFO interface circuit of the packet input queue memory, and the output end is connected with the input end of the multi-channel data selector circuit; the IPv6 tunnel header data register, the input end is connected with the IPv4 header transfer IPv6 tunnel header circuit and state control The machine circuit is connected, and the output end is connected with the multiplex data selector circuit; the output end of the multiplex data selector circuit is connected with the input end of the IPv6 packet queue memory FIFO; the packet input queue memory FIFO interface circuit will receive the data packet head signal and tail The signal is sent to the counter circuit, and the multi-channel data selector circuit also transmits the output data packet header and packet tail signal to the counter circuit, and the input and output packet header and tail signal counts output by the counter circuit are connected to the state counter value input terminal of the CPU interface circuit. Simultaneously receive the counter clearing signal input by the CPU interface circuit;

Described packet-related information extraction circuit is a circuit component, is made up of a series of circuits: IPv6 packet queue memory interface circuit, described data input end is connected with IPv6 packet queue memory FIFO, the read signal of output and IPv6 packet queue memory FIFO The read input signal is connected, the control input and output terminals are connected to the state control machine circuit, and the output terminal is connected to the packet handover identification register, packet priority register, packet source port number register, packet start address register, packet end address register, and packet serial number The register, the packet destination address register, the tunnel identification register and the packet writing RAM circuit are connected; the input end of the IPv6 packet information sending circuit is handed over to the identification register, the packet priority register, the packet starting address register, and the packet source port number The register, the packet termination address register, and the packet serial number register are connected, the control information comes from the state control machine, and the output terminal is connected to the IPv6 data packet related information queue memory FIFO; the input terminal of the retrieval instruction sending circuit is connected with the packet serial number register, and the packet destination address register , the tunnel identification register are connected, the output end is connected with the retrieval instruction queue memory FIFO, the control input end is connected with the state control machine; the output end of the packet writing RAM circuit is connected with the IPv6 data packet memory RAM, and its control input end is connected with the state control machine Connected; the input end of the counter is respectively connected with the input packet header signal and the input packet tail signal of the IPv6 packet queue memory FIFO interface circuit, and also connected with the packet header signal and packet tail signal output by the packet writing RAM circuit, and also connected with the CPU interface circuit input The counter clearing signal is connected, and the output packet header and tail signal count is connected to the CPU interface circuit;

Described CAM control circuit is a circuit component, is made up of a series of circuits: the data input end of retrieval instruction queue memory FIFO interface circuit is connected with retrieval instruction queue memory FIFO output end, the read signal of output and the read of retrieval instruction queue memory FIFO The signal is connected, and the output end is also interconnected with the state control machine to receive the control signal output by the state control machine; the input end of the CAM write data register and the retrieval instruction queue memory FIFO interface circuit, and the CAM maintenance instruction queue memory FIFO interface circuit The output end is connected, and the output end is connected with the CAM data bus read-write control circuit; the input end of the CAM operation instruction sending circuit is connected with the output end of the retrieval instruction queue memory FIFO interface circuit, and the output end of the CAM maintenance instruction queue memory FIFO interface circuit, and the output The terminal is directly connected to the command bus INST, LTIN, SEGSEL, GMASK, CRB of the CAM memory and the request strobe signal REQSTB; the input terminal of the SRAM write data register and the output terminal of the FIFO interface circuit of the CAM maintenance instruction queue memory, and the retrieval instruction queue memory The output end of the FIFO interface circuit is connected, and the output end is connected with the input end of the SRAM data bus read-write control circuit; the output end of the SRAM data bus read-write control circuit is connected with the SRAM read data register, the retrieval result register and the SRAM single-port memory, and the control The signal input terminal is connected to the output of the state machine; the input terminal of the CPU read data register is connected to the output terminal of the CAM read data register and the output terminal of the SRAM read data register, and the output terminal is connected to the CPU interface circuit; the input of the retrieval result register The end is connected with the output end of the data packet serial number register, and the output end is connected with the retrieval result queue memory FIFO; the input end of the data packet serial number register is connected with the output end of the retrieval instruction queue memory FIFO interface circuit and the output end of the state control machine; The input terminal of the counter is connected with the output terminal of the retrieval result register, and is also connected with the calculator clearing signal input by the CPU interface circuit, and the query state count output of it is connected with the CPU interface circuit;

Described packet sending circuit is a circuit component, is made up of a series of circuits: IPv6 data packet related information queue memory FIFO interface circuit, data input end is connected with the output end of IPv6 data packet related information queue memory FIFO, control input and output end It is connected with the state machine control circuit, the output read signal is connected with the FIFO read input terminal of the IPv6 data packet related information queue memory, and the output terminal is respectively connected with the packet storage start address register, packet storage end address register, packet length register, and packet priority register , the source port number register, and the input of the packet serial number register A are connected; the retrieval result queue storage FIFO interface circuit, the data input terminal is connected with the output of the retrieval result queue storage FIFO, the control input and output terminals are connected with the state machine control circuit, and the output The terminals are respectively connected to the input ends of the packet serial number register B, the destination port number register, the destination line card number register, the next-hop IPv6 address register, the next-hop IPv4 address register, and the tunnel IPv6 destination address register; the bit width is 36 bits The input terminals of the additional data register group are respectively connected with the packet priority register, the packet length register, the source port number register, the source line card number register, the destination port number register, the destination line card number register, the next hop IPv6 address register, the next hop The data output end of the IPv4 address register and the tunnel IPv6 destination address register are connected; the input of the source line card number register comes from the CPU interface circuit; the adder is increased by 10, the input end is connected with the output of the packet storage start address, and the output end is connected with the address register A connected; the input of the address register B is connected to the output of the packet storage start address; the output of the adder is connected to the output of the IPv6 packet memory read address register and the input of the address register C respectively; multiplex data selection Device A, the input end is connected with the address register A, address register B, address register C respectively, the control input end is connected with the output of the state machine control circuit, the output end is connected with the input end of the IPv6 data packet memory read address register; the data comparator A, the input end is connected to the output end of the packet storage termination address register and the output end of the IPv6 packet memory read address register, and the output end is connected to the input end of the state machine control circuit; the bit width is 36 bits of IP data register, the input end It is connected with the data output terminal of the IPv6 data packet memory RAM, and the output terminal is connected with the input terminal of the multiplexer B; the data input terminal of the multiplexer B is respectively connected with the output of the additional data register group whose bit width is 36 bits end, the output end of the IP data register with a bit width of 36 bits is connected, and the output end is connected with the input end of the handover data packet register and the IPv4 or IPv6 data packet register with additional data; the output end of the handover data packet register is connected with the first The input end of 1 handover packet queue memory FIFO is connected; the output end of the IPv4 or IPv6 packet register with additional data is sent to the upstream FIFO connected with FPGA; the IPv4 or IPv6 packet with additional data is sent to The register also transmits the sent data packet header signal and packet tail signal to the counter respectively, and the counter is also connected with the counter clearing signal input by the CPU interface circuit, and the packet header and packet tail signal count signal output by the counter is sent to the CPU interface circuit;

The CAM memory is the FPGA off-chip memory of the system. The read-write control command bus signal and the data request bus REQDATA signal are from the CAM control circuit. The write signal is connected, and the output read confirmation signal, search match signal, and search output valid signal are connected to the input end of the CAM control circuit;

Described SRAM single-port memory is the FPGA off-chip static SRAM memory of system, and read-write input signal and address signal are from the output of CAM memory, and data input and output end are connected with CAM control circuit;

The SRAM dual-port memory is a static dual-port SRAM memory outside the FPGA chip of the system, which is divided into a data write port and a data output port. The read and write signal lines and address bus of the data output port are connected to the output end of the handover packet sending circuit, the bidirectional data bus of the data output port is connected to the CPU interface circuit, the read and write signal line of the data output port, the address bus and the output end of the CPU interface circuit connected.

The tunnel forwarding system that adopts IPv6 header to encapsulate IPv4 packets in the router built by the above method is composed of one FPGA chip EP1S25F780, two IDT75k62100 (TCAM), two IDT71T75602 (SRAM), and one CY7C1300A (SRAM dual-port memory) chip. Work with the same clock as peripheral chips.

FPGA has only one main clock CLK. When the clock frequency is 100MHZ, the reset signals of all the above modules come from the CPU interface circuit, and the reset signals of the CPU interface circuit come from the CPU control unit. The clocks of all the above modules are CLK, but in the above In order to avoid repetition, it is not mentioned that the performance indicators achieved by the tunnel forwarding system that uses IPv6 headers to encapsulate IPv4 packets in routers are:

IDT75k62100 and FPGA share a main clock 100MHZ CLK, and the operating frequency of the two IDT71T75602 is 50MHZ. The 50MHZ and the main 100MHZ clock source are the same, and are obtained by dividing the 100MHZ CLK main clock by two;

By using the lookup table constructed by the CAM system, it supports the dynamic allocation of the number of entries and IPv6 routing lookup of IPv6 packets, and the system can guarantee to send and receive data packets at a line speed of 3.2Gbit/s.

Through the above method, the route finder built by using one EP1S25780 and cascading two IDT75k62100s can support IPv6 routing entries of 64K*288bits at most.

The tunnel transmission processing system can process IPv6 tunnel data packets, IPv4 data packets and IPv6 non-tunnel data packets, and can process data packets of up to 32k bytes. The system can guarantee 3.2Gbit/s wire speed to send and receive data packets. If it exceeds 3.2Gbit/s, packets will be lost, but the packets that are not lost can be transmitted correctly. If the packet rate returns to 3.2Gbit/s, there will still be no packet loss.

Support handing over the entire packet cache.

Control and maintain each circuit module and CAM system in FPGA through CPU.

Description of drawings

Figure 1 The position of the tunnel forwarding system in the router that uses the IPv6 header to encapsulate the IPv4 packet in the line card of the core router and the relationship with the surrounding devices

Figure 2 The connection relationship between chips in the tunnel forwarding system that uses IPv6 headers to encapsulate IPv4 packets in routers

Figure 3 The relationship between the various sub-circuits inside the FPGA of the tunnel forwarding system that uses the IPv6 header to encapsulate the IPv4 packet in the router

Figure 4 packet filtering circuit

Figure 5 IPv6 protocol encapsulation circuit

Figure 6 Package related information extraction circuit

Figure 7CAM control circuit

Figure 8 packet sending circuit

Table entry data structure stored in Figure 9CAM memory

Note: The destination IPv6 address is 128 bits (127~0), the tunnel ID occupies 1 bit, and the reserved bit is 0.

Figure 10 SRAM single-port memory storage entry data structure

Description: Identification (bit71~69): 000——IPv4 forwarding; 001—handover; 010—discard, 011—general IPv6 forwarding; 100——IPv6 tunnel forwarding;

Destination line card number: bit71~68; destination port number: bit67~64.

The IPv6 tunnel destination address has a total of 128 bits, which is composed of bit63~0 of the third and fourth entries of the SRAM single-port memory.

Reserved position 0.

Figure 11 The data structure of the PPP packet received by the IP packet input interface circuit and processed by the upper circuit

Figure 12 The data structure in the packet input queue memory FIFO

Explanation: (1) bit35~34 indicate the head and tail of the packet: 10—the beginning of the data packet, 00—the middle data of the data packet, 01—the end of the data packet, 11—the error of the data packet. bit33~32 is the MOD field, the last 32-bit valid byte indicates that it is meaningful only at the end of the packet: 00—the last four bytes are all valid, 01—three of the last four bytes are valid (bit31~8), 10—two bytes in the last four bytes are valid (bit31~16), 11—one byte in the last four bytes is valid (bit31~24); invalid bits are filled with 0 . bit31~31, the specific content of the data packet.

Figure 13 The data structure in the FIFO of the IPv6 data packet-related information queue memory

Figure 14 Retrieve the data structure in the instruction queue memory FIFO

Figure 15 CAM maintenance instruction queue memory FIFO data structure

Figure 16 The data structure in the retrieval result queue memory FIFO

Figure 17 The data structure sent to the upstream FIFO

Explanation: (1) bit35~34 indicate the head and tail of the packet: 10—the beginning of the data packet, 00—the middle data of the data packet, 01—the end of the data packet, 11—the error of the data packet. bit33~32 is the MOD field, the last 32-bit valid byte indicates that it is meaningful only at the end of the packet: 00—the last four bytes are all valid, 01—three of the last four bytes are valid (bit31~8), 10—two bytes in the last four bytes are valid (bit31~16), 11—one byte in the last four bytes is valid (bit31~24); invalid bits are filled with 0 . bit31~31, the specific content of the data packet.

(2) Source location number: bits 15-8, 8 bits in total, where bits 11-8 identify the source port number, and bits 15-12 identify the source line card number.

(3) Destination port number: bit19~8, 12 bits in total, but currently only bit11~8 are used, and other bits are 0, which are used to indicate the output port after the data packet arrives at the target line card.

Figure 18 hand in data structure

Note: bit35~34 are the head and tail instructions of the packet: 10—the start of the data packet, 00—the middle data of the data packet, 01—the end of the data packet, 11—the error of the data packet. bit33~32 is the MOD field, the last 32-bit valid byte indicates that it is meaningful only at the end of the packet: 00—the last four bytes are all valid, 01—three of the last four bytes are valid (bit31~8), 10—two bytes in the last four bytes are valid (bit31~16), 11—one byte in the last four bytes is valid (bit31~24); invalid bits are filled with 0 . bit31~31, the specific content of the data packet.

Figure 19 uses the IPv6 header to encapsulate the data structure of the tunnel data packet of the IPv4 message

Detailed ways

The tunnel forwarding system that uses IPv6 header to encapsulate IPv4 packets in routers is used on line interface cards to solve the problem of interconnection of IPv4 networks through pure IPv6 backbone networks, and the specific implementation uses FPGA technology. It is realized by a tunnel processing circuit, an external SRAM dual-port memory chip, an SRAM single-port memory chip, a CAM memory chip, and a CPU control unit, and the tunnel processing circuit is realized by an FPGA. The position of the system in the high-performance core router is shown in Figure 1, and the connection relationship between the chips constituting the system is shown in Figure 2.

It can be seen from the figure that the tunnel forwarding system in the router adopts the IPv6 header to encapsulate the IPv4 packet, and receives the data packet encapsulated according to the PPP protocol from the physical and data link layer processing circuits. The processing system extracts pure IPv6 data packets and IPv4 data packets therein according to the protocol domain identification. Encapsulate the IPv4 data packet and add the IPv6 data packet header to become an IPv6 tunnel data packet; check the destination address and hop count of the IPv6 data packet, and directly hand over the IPv6 data packet whose destination address is the router to the CPU control unit is processed. For the IPv6 data packet whose destination address is not the router, extract the route lookup information from it, and submit the lookup information to the CAM lookup system (CAM+SRAM) for lookup, the tunnel processing circuit composed of FPGA, according to the result returned by the lookup, decides Whether to perform normal IPv6 forwarding, IPv6 header-encapsulated tunnel forwarding of IPv4 packets, IPv4 forwarding, discarding, or handing over to the CPU for processing of IPv6 data packets. The forwarded packet is sent to the subsequent switch fabric coprocessor and switch fabric for processing through the uplink FIFO memory.

After the tunnel transmission processing system is powered on, the CPU control unit initializes the entire system through the CPU interface circuit, configures the CAM as a 288-bit search mode, and configures SRAM entries. After the initialization is completed, the system can work normally.

The storage bit width of a single CAM entry used by the system is 72 bits, so the supported entry length is an integer multiple of 72 bits. Since the destination address of an IPv6 packet is 128 bits, at least two CAM entries are required to store the IPv6 packet. Destination address. After the IPv4 packet enters the router and leaves the router, if the IPv6 header is used to encapsulate the tunnel forwarding of the IPv4 packet, the system needs to provide not only the IPv6 address of the tunnel end exit, but also the IPv6 address of the next-hop router that the tunnel packet passes through after leaving the current router. , such that the SRAM providing the lookup results requires at least 256 bits. The length of entries supported by the SRAM single-port memory used by the system is an integer multiple of 72 bits. In this way, the actual storage capacity provided by the SRAM is 288 bits, corresponding to 4 storage units of the SRAM. 288-bit SRAM must be paired with 288-bit CAM to match in timing, so the system uses 4 CAM entries with a total of 288 bits to represent a routing entry. The bits 71 to 69 of the first entry are set to 100, indicating that it is an IPv6 entry. If bit68 is set to 1, it means that the route of the IPv6-encapsulated tunnel packet is checked. If bit68 is set to 0, it means that the check is a normal IPv6 packet. For routing, bits 67~64 are reserved, and bits 63~0 correspond to the upper 64 bits of the IPv6 destination address. The bits 71~64 of the second entry are reserved, and bits 63~0 correspond to the lower 64 bits of the IPv6 destination address. There are two other table items reserved and set to 0, as shown in Figure 9.

The structure of each routing entry supported by the SRAM single-port memory used by the system is shown in Figure 10: bits 71 to 69 of the first entry form the identification bits of the routing search result, which are used to indicate the type of the search result: IPv4 forwarding, common IPv6 forwarding, IPv6 tunnel forwarding, discarding, and data delivery to the CPU control unit; the destination line card number is composed of bits 71 to 68 of the second table entry, a total of 4 bits, used to indicate the destination line that the data packet will reach through the switching structure card; the destination port number is composed of bit67~64, a total of 4 bits, used to indicate which port of the line card the forwarded data packet will be sent out after it reaches the destination line card through the switching structure; the first entry and the second The bit63~0 of the entry stores the destination address of the next hop. If it is normal IPv6 forwarding, the IP address of the next hop is 128 bits. If it is IPv4 forwarding, the IP address of the next hop is 32 bits. Only bits 31 to 0 of the second entry are valid; when the flag is equal to 000, the data packet is forwarded with IPv4; when it is equal to 001, the data packet is discarded; when it is equal to 010, the data packet is handed over to the CPU control unit, equal to When 011, the data packet is forwarded by ordinary IPv6; when it is equal to 100, the data packet is forwarded by IPv6 tunnel; the bits 63-0 of the third and fourth entries of the SRAM store IPv4 data packets by IPv6 tunnel mode, and the IPv6 tunnel 128-bit IPv6 destination address of the terminal egress router.

The workflow of the whole system is as follows:

1) The IP packet input interface circuit reads the processed PPP protocol data packet and data source port number from the physical and data link layer processing circuit. The processed PPP protocol data packet only contains the protocol field, the information field and the padding field. PPP The other parts of the data packet have already been discarded by the higher-level circuit. According to the 16-bit protocol number of the PPP packet, the pure IPv6 or IPv4 data packet is extracted, and the pure IPv6 message or IPv4 message with the PPP 16-bit protocol field and the filling field removed is sent to the packet filtering circuit.

2) Packet filter circuit receives IPv4 and IPv6 data packet, if what receive is unicast IPv4 data packet, then the time-to-live TTL field of IPv4 packet is checked, if its TTL is 0, then this IPv4 data packet is discarded; If TTL If it is greater than 1, subtract 1 from the TTL domain of the IPv4 data packet. If the TTL is equal to 0 after subtracting 1, the IPv4 data packet will be sent to the 0th handover packet queue memory FIFO; if the received IPv4 data packet is Multicast data is also sent to the 0th handover packet queue memory FIFO; if the TTL of the received unicast IPv4 packet is not 0, and the TTL obtained after the TTL is subtracted by 1 is also not 0, let the IPv4 packet complete TTL minus 1 operation, regenerate a new header checksum, let the packet pass, and send it to the next-level packet input queue memory FIFO.

There are three types of IPv6 data packets received by the packet filtering circuit: unicast, multicast, and anycast. In the subsequent processing, the processing of anycast in this system is the same as that of unicast, and all the processing methods for unicast are also applied to anycast, but will not be described again.

After the packet filter circuit receives the IPv6 packet, it first checks the hop limit of the packet, and if its hop limit is 0, the IPv6 packet is discarded; if its hop limit is greater than or equal to 1, then the hop limit is removed. Subtract 1 operation, if after subtracting 1, the hop count is 0, then send the IPv6 data packet to the 0th handover packet queue memory FIFO; if the hop count is still not 0 after the hop count is decremented by 1, the packet filtering circuit will The destination address of the IPv6 packet is checked; if it is a multicast packet, it is sent to the 0th handover packet queue memory FIFO.

If the destination address of the received IPv6 data packet is the router, there are two cases, the first is the case: the data packet is not an IPv6 tunnel packet, then it will be sent to the 0th handover packet queue memory FIFO; the second is the case : The data packet is a tunnel packet, then the packets smaller than 61 bytes are all discarded, and those not smaller than 61 bytes are sent to the next-level packet input queue memory FIFO.

If the destination address of the received IPv6 data packet is not the router, there are two cases: the first case is that the data packet is an IPv6 tunnel packet, then the packet smaller than 61 bytes will be discarded, and the packet not smaller than 61 bytes will be sent Input the queue storage FIFO to the next-level packet; the second case is that the data packet is not an IPv6 tunnel data packet, then the size of the data packet is not checked and directly sent to the next-level packet input queue storage FIFO.

3) The IPv6 protocol encapsulation circuit reads the data packet through the packet input queue memory FIFO interface circuit, and according to the version number of the IP data, the packet input queue memory FIFO interface circuit knows whether the data read in is an IPv4 data packet or an IPv6 data packet.

If it is IPv4 data, under the control of the state control machine circuit, the packet input queue memory FIFO interface circuit reads the IPv4 packet header data, and saves it in the IPv4 packet header data register, and the data in the IPv4 packet header data register is output to the IPv4 packet header Transfer to IPv6 tunnel header circuit. The IPv4 header-to-IPv6 tunnel header circuit corresponds to each IPv4 header and generates an IPv6 encapsulation header: the source address of the IPv6 header is the IPv6 address of the router, the highest 96 bits of the header destination address are set to 0, and the lowest 32 bits are currently processed The destination address of the IPv4 data packet, the next header field of the packet header is set to 101 in decimal, the hop limit is set to 64 in decimal, the traffic type of the packet is set to 0, and the flow label is set to 0. The generated IPv6 header is sent to the IPv6 tunnel header data register. The data in the IPv6 packet header stored in the IPv6 tunnel packet header data register and the data stored in the IPv4 packet header data register are sequentially selected and sent to the next-level IPv6 packet queue memory FIFO by the multiplexer, and at the same time, the packet is input into the queue memory The FIFO interface circuit continues to read the load part of the IPv4 data packet and save them in the IPv4 load data register. After sending the data in the IPv4 header data register, the multiplexer immediately selects the output of the IPv4 load data register , so that the IPv6 tunnel packet is continuously sent to the next-level IPv6 packet queue memory FIFO like a pipeline.

If it is an IPv6 tunnel packet, the packet input queue memory FIFO interface circuit reads the IPv6 header, and discards the IPv6 header, and then reads the IPv4 packet header data of the IPv6 tunnel packet, and stores it in the IPv4 packet header data register, and the IPv4 packet header data The data in the register is output to the IPv4 header-to-IPv6 tunnel header circuit. Under the control of the state control machine circuit, the IPv4 header-to-IPv6 tunnel header circuit corresponds to each IPv4 header, and generates an IPv6 encapsulation header: the source address of the IPv6 header is the IPv6 address of the router, and the destination address of the header is up to 96 bits bit127~32 Set to 0, the lowest 32 bits are the destination address of the currently processed IPv4 data packet, the next header field of the packet header is set to 101 in decimal, the hop limit is set to 2 in decimal, the traffic type of the packet is set to 0, and the flow label is set to 0. The generated IPv6 header is sent to the IPv6 tunnel header data register. The data in the IPv6 packet header stored in the IPv6 tunnel packet header data register and the data stored in the IPv4 packet header data register are sequentially selected and sent to the next-level IPv6 packet queue memory FIFO by the multiplexer, and at the same time, the packet is input into the queue memory The FIFO interface circuit continues to read the IPv4 data load part of the IPv6 tunnel packet and saves them in the IPv4 load data register. After sending the data in the IPv4 header data register, the multiplexer selects the IPv4 load data register immediately The output of the IPv6 tunnel packet that has been updated like this is continuously sent to the IPv6 packet queue memory FIFO of the next level like a pipeline.

If the IPv6 data packet read by the packet input queue memory FIFO interface circuit is not a tunnel packet, no processing is performed on the IPv6 data packet, it is only temporarily stored in the IPv6 data register, and it is directly transmitted to the next channel through the multiplex data selector. One-level IPv6 packet queue memory FIFO.

4) The packet-related information extraction circuit reads the IPv6 data packet from the IPv6 packet queue memory FIFO through the IPv6 packet queue memory FIFO interface circuit, and each beat reads 40 bits, wherein 8 bits are side information, and 32 bits are IP packets. The IPv6 packet queue memory FIFO interface circuit has a beat calculator and a packet calculator. The beat calculator records the number of beats of the received data packets. Each beat contains 32 bits of IP data. The packet calculator records the number of received packets. When the system is initialized, the beat counter and packet counter are cleared to 0. When the IPv6 packet queue memory FIFO interface circuit receives a data packet, the beat calculator value corresponding to the first beat data of the data packet is exactly the starting address of the IPv6 data packet stored in the IPv6 memory RAM, and the last beat data of the data packet corresponds to The calculator value of is the termination address of the data packet stored in the IPv6 memory RAM. After each beat data is received, the counter value is increased by 1. The start address and end address of the data packet are output and stored in the packet start address register and the packet end address register respectively. Correspondingly, when a data packet is received, the packet calculator value corresponding to the first beat data of the data packet is the serial number corresponding to the data packet, and the serial number is output to the packet serial number register for storage. Each time a data packet is received, the value of the packet counter is increased by 1, and the increment of the packet counter by 1 occurs after the last beat of the received data packet.

Under the action of the state control machine circuit, the IPv6 packet queue memory FIFO interface circuit writes the IPv6 packet into the RAM circuit through the packet, and sends the received IPv6 packet to the IPv6 packet memory RAM connected with the packet-related information extraction circuit, and the IPv6 packet memory RAM is A dual-port RAM memory that reads and writes synchronously with the clock, one port is dedicated to writing data, and one port is dedicated to reading data.

Under the action of the state control machine circuit, the IPv6 packet queue memory FIFO interface circuit extracts the source port number of the data packet, and sends the source port number to the source port number register. For the received IPv6 data packet, if its next header field is 0, set the handover flag, and output the handover flag to the packet handover flag register, and save it in the register.

Under the action of the state control machine circuit, the IPv6 packet queue memory FIFO interface circuit extracts the traffic category of the packet and saves it in the packet priority register. If the IPv6 packet is a tunnel packet, set the tunnel identification register to 1, otherwise set to 0.

The value of the packet handover identification register, packet priority register, packet source port number register, packet termination address register, packet start address register, and packet serial number register is output to the IPv6 packet information sending circuit, and the IPv6 information sending circuit is in the state control machine Under the control of the circuit, the data is sent to the IPv6 data packet-related information queue memory FIFO connected with the packet-related information extraction circuit.

The work of CAM is controlled by its command bus and request data bus. The retrieval instruction sending circuit generates CAM command bus control data: request strobe signal REQSTB, operation instruction type signal INST, search type signal LTIN, segment selection signal SEGSEL, mask register selection The signal GMASK, CAM command bus control data is sent to the retrieval instruction queue memory FIFO by the retrieval instruction sending circuit.

The packet serial number register, tunnel identification register and packet destination address register are sent to the retrieval instruction queue memory FIFO connected with the packet-related information extraction circuit through the retrieval instruction sending circuit, wherein the data stored in the tunnel identification register and the packet destination address register correspond to the CAM data bus The input 72-bit wide REQDATA data is used for CAM lookup.

5) The retrieval instruction queue memory FIFO interface circuit inside the CAM control circuit reads the retrieval instruction from the retrieval instruction queue memory FIFO, and writes the REQDATA data into the CAM write data register. The operation of the CAM memory is controlled by the command bus, so the read bus control commands REQSTB, INST, LTIN, SEGSEL, GMASK are written into the CAM operation instruction sending circuit. The FIFO interface circuit of the retrieval instruction queue memory also saves the data packet serial number corresponding to the retrieval instruction into the data packet serial number memory.

After the initialization of CAM entries and SRAM entries is completed, during the operation of CAM, the operating system must continuously delete and add operations to CAM entries and SRAM entries. These operations are maintenance instructions from the CPU to the CAM through the CPU interface circuit. The queue memory FIFO sends CAM maintenance instructions to complete. The CAM control circuit reads the CAM maintenance instruction of the CAM maintenance instruction queue memory FIFO through the CAM maintenance instruction queue memory FIFO interface circuit, and writes the REQDATA data into the CAM write data register, and reads the bus control commands REQSTB, INST, LTIN, SEGSEL , GMASK is written into the CAM operation instruction sending circuit. The CAM maintenance instruction queue memory FIFO interface circuit also saves the SRAM entries that need to be written in the SRAM write data register.

Under the action of the state control machine circuit, the CAM data bus read-write control circuit and the SRAM read-write data bus control circuit write the corresponding entries into the CAM and SRAM memory, or output the result of the search to the CAM read-out data register, SRAM read data register. If the maintenance operation is performed on the CAM, the CPU reads the data register and sends the read CAM and SRAM data to the CPU interface circuit, and hands it over to the CPU through the CPU interface circuit. If the command to operate the CAM comes from the retrieval instruction queue memory FIFO interface circuit, the result of the SRAM retrieval and the sequence number stored in the data packet sequence number register are output to the retrieval result register, and sent to the CAM control circuit through the retrieval result register. Retrieve result queue memory FIFO.

6) The packet sending circuit reads the start address, the termination address, the hand-over identification and the packet sequence number stored in the IPv6 packet memory RAM by the IPv6 data packet related information queue memory FIFO interface circuit, and saves the termination address in the end address register. The retrieval result queue storage FIFO interface circuit reads the retrieval result queue storage FIFO, according to the identification bit and the handover identification bit obtained by the IPv6 data packet-related information queue storage FIFO interface circuit, the state machine control circuit knows that the packet sending circuit processes the data packet The method is either forwarding according to IPv4, or handing over the data packet, or discarding the data packet, or forwarding the data packet according to ordinary IPv6, or forwarding the data packet according to the IPv6 tunnel mode. In addition, if the data packet serial number obtained via the IPv6 data packet-related information queue memory FIFO interface circuit and the retrieval result queue memory FIFO interface circuit are respectively saved to 4-bit packet serial number register A and packet serial number register B, the packet serial number register A And the data in the packet serial number register B is input to the data comparator B, if the result of the comparison is that the two data are not equal, it means that there is an error in the system, and the data comparator B sends an indication signal to the CPU interface circuit, through the CPU interface circuit. The system resets. After reset, initialize the system according to the above method.

IPv6 data packet related information queue memory FIFO interface circuit reads data packet length, packet priority, source port numbering from IPv6 data packet related information queue memory FIFO, and it is respectively stored in data packet length register, packet priority register, source in the port number register. The retrieval result queue memory FIFO interface circuit reads the destination port number, the destination line card number, the next hop IPv6 or IPv4 address, and the tunnel IPv6 destination address, and stores them in the destination port number register, the destination line card number register, and the next hop address respectively. IPv6 register or IPv4 address register, tunnel IPv6 destination address register.

If the data is forwarded according to IPv4, the values output by the packet length register, packet priority register, source line card number register, source port number register, destination port number register, destination line card number register, and next-hop IPv4 register are stored in 3 additional data registers with a bit width of 36 bits. Under the action of the state control machine, the multiplexer B divides into 3 beats to send the data in the 3 additional data register groups with a bit width of 36 bits. These data are added to the IPv4 data packet as the additional data header of the IPv4 data packet. The front of the packet is sent to the upstream FIFO.

Next to the IPv4 additional data header is the IPv4 data packet. Under the action of the state control machine circuit, the 10 adder receives the packet from the input end to store the starting address, adds 10 to the address value, and outputs the result to the address The register A saves, and the multiplexer A selects the data in the address register A to output to the IPv6 packet memory RAM read address register, and the read address register sends the read address to the read address bus of the IPv6 packet memory RAM read port. The IPv6 data packet memory RAM sends the read data to the IP data register with a bit width of 36 bits, and the multiplexer B selects the IP data register with a bit width of 36 bits, so that the first beat data of the IPv4 data packet is followed by Additional data headers for IPv4 are sent to the upstream FIFO.

Under the action of the state control machine circuit, the increment adder reads the value of the IPv6 data packet memory RAM read address register, adds 1 to the address and submits it to the address register C. The multiplexer A selects the data in the address register C, and hands the data to the IPv6 data packet memory RAM to read the address register. Afterwards, the process of the system running is the same as when sending the first beat of the IPv4 data packet.

Each clock cycle, the data comparator A compares the value of the input IPv6 data packet memory RAM read address register with the value of the input packet storage end address register, and if the two are equal, it means that the data of the data packet has all been output. If there are other data in the packet memory circuit, under the action of the state control machine, the packet sending circuit also performs the same processing on subsequent data packets.

If the data is forwarded according to ordinary IPv6, the working process of the packet sending circuit is generally similar to the working process of forwarding IPv4 data packets, only a small part is different. The different parts are:

(1) If the data is forwarded according to ordinary IPv6, then output the packet length register, packet priority register, source line card number register, source port number register, destination port number register, destination line card number register, and next-hop IPv6 register value, stored in six additional data register banks with a width of 36 bits. Under the action of the state control machine, the multiplexer B divides into 6 beats to send the contents of the 36-bit additional data register group with a bit width of 6. These data are added to the IPv6 data packet as the additional data header of the IPv6 data packet. to the front of the next level uplink FIFO.

(2) The address of the first shot data of the IPv6 data packet is sent to the address register B through the packet storage start address, and then sent to the IPv6 data packet memory RAM to read the address register through the multiplexer A, which cannot be increased by 10. The device adds 10 to the operation.

If the data is forwarded according to the IPv6 tunnel, the working process of the packet sending circuit is generally similar to the working process of forwarding the IPv6 data packet, only a small part is different. The different part is: if the data is forwarded according to IPv6, the packet length register, packet priority register, source line card number register, source port number register, destination port number register, destination line card number register, next hop IPv6 register 1. The value output by the tunnel IPv6 destination address register is stored in 10 additional data register groups whose bit width is 36 bits; , comes from the IPv6 protocol encapsulation circuit, and shall be replaced here by the tunnel IPv6 destination address obtained through the CAM look-up table stored in the additional data register set with a bit width of 36 bits.

If the data is not forwarded by IPv4, ordinary IPv6, or IPv6 tunnel, but is still handed over, the working process of the packet sending circuit is generally similar to the working process of forwarding IPv6 data packets, only a small part is different. The difference is:

(1) When the IPv6 data packet is handed over, the additional data of the IPv6 data packet is only one beat, and the additional data only includes the source line card number and the source port number. Other data less than 36 bits are filled with 0.

(2) The data selected by the multiplexer B is sent to the handover data packet register, and then sent to the first handover packet queue memory FIFO through the handover data packet register.

If the data does not carry out IPv4, ordinary IPv6 forwarding, IPv6 tunnel forwarding, it does not need to be handed over, or discarded, under the action of the state control machine circuit, the packet sending circuit no longer performs any operation on the IPv6 data packet memory RAM. Demultiplexer A and demultiplexer B also do nothing.

If there are other data packets following the discarded data packet, the state control machine circuit instructs the IPv6 data packet related information queue memory FIFO interface circuit and the retrieval result queue memory FIFO interface circuit to extract the forwarding information of the next data packet, according to forwarding The identification of information carries out forwarding, handing over, and discarding processing of data packets according to the above-mentioned manner.

7) As long as the 0th handover packet queue memory FIFO or the first handover packet queue memory FIFO is not empty, the handover packet sending circuit can take turns from the non-empty 0th handover packet queue memory FIFO and the first handover packet queue memory FIFO The data packet read from the FIFO of the handover packet queue memory is sent to the SRAM dual-port memory. When the number of bytes of the handover data packet stored in the SRAM dual-port memory reaches a certain threshold, or a data packet is not received within a period of time after receiving a data packet When a new data packet is received, the handover packet sending circuit sends an interrupt signal to the CPU interface circuit, and transmits the start address, the end address and the length of the data to be transmitted of the handover data packet stored in the dual-port memory RAM to the CPU interface circuit , the CPU interface circuit transmits the interrupt signal to the CPU. If the CPU is not busy, it responds to the interrupt request and starts the handover packet data transmission. The CPU interface circuit reads the handover data packet from the SRAM dual-port memory and sends it to The CPU does the processing.

Claims (5)

1. adopt the tunnel repeater system of IPv6 head encapsulation IPv4 bag in the router, it is characterized in that, contain: tunnel treatment circuit, SRAM one-port memory, SRAM dual-ported memory, CAM Content Addressable Memory and a CPU control unit that is integrated on the fpga chip, wherein:

Described tunnel treatment circuit, contain: IP packet input interface circuit, the packet filtering circuit, bag input rank memory FIFO, IPv6 protocol encapsulation circuit, IPv6 bag queue memory FIFO, packet-related information extracts circuit, search instruction queue memory FIFO, the CAM control circuit, result for retrieval queue memory FIFO, IPv6 packet relevant information queue memory FIFO, IPv6 packet memory RAM, the bag transtation mission circuit, CAM maintenance instruction queue memory FIFO, submit bag queue memory FIFO for the 0th, submit bag queue memory FIFO for the 1st, submit the bag transtation mission circuit, and cpu interface circuit, wherein:

IP packet input interface circuit, input receives the ready for data signal and the data bus signal of higher level's physical and datalink layer treatment circuit output, the output read signal is given higher level's physical and datalink layer treatment circuit, the input of described IP packet input interface circuit data output and packet filtering circuit links to each other, the IPv4 of input and output and IPv6 packet header signal and bag tail signal are counted respectively, the tail count output signal is wrapped in packet header send to cpu interface circuit, and receive the reset signal sum counter reset signal of cpu interface circuit input;

The packet filtering circuit, input links to each other with IP packet input interface circuit, also submit bag queue memory FIFO with the 0th respectively, the fast signal of expiring of bag input rank memory FIFO output links to each other, output is submitted the input of bag queue memory FIFO with the 0th respectively, the input of bag input rank memory FIFO links to each other, packet header signal and bag tail signal to input and output are counted, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;

Bag input rank memory FIFO is a fifo queue memory, and data width is 36, and input links to each other with the IP bag output of above-mentioned packet filtering circuit, and read signal is from IPv6 protocol encapsulation circuit, and reset signal is from cpu interface circuit;

IPv6 protocol encapsulation circuit, input links to each other with described bag input rank memory FIFO, output links to each other with IPv6 bag queue memory FIFO, input also receives the fast signal of expiring of IPv6 bag queue memory FIFO output in addition, IPv6 protocol encapsulation circuit is counted the packet header signal and the bag tail signal of input and output, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;

IPv6 bag queue memory FIFO, it is a fifo queue memory, data width is 40, data input pin links to each other with above-mentioned IP v6 protocol encapsulation circuit, reading input signal links to each other with the output of reading that packet-related information extracts circuit, output extracts circuit with packet-related information and links to each other, and reset signal is from cpu interface circuit;

Packet-related information extracts circuit, input links to each other with the output of IPv6 bag queue memory, output links to each other with search instruction queue stores FIFO, IPv6 packet memory RAM, IPv6 packet relevant information queue memory FIFO respectively, packet header signal and bag tail signal to input and output are counted, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;

Search instruction queue memory FIFO, be a fifo queue memory, data width is 100, and data input pin extracts circuit with above-mentioned packet-related information and links to each other, the output of reading of reading input signal and CAM control circuit links to each other, and data output end links to each other with the CAM control circuit;

The CAM control circuit, input respectively with search instruction queue memory FIFO output, CAM maintenance instruction queue memory FIFO output links to each other, the CAM memory read/write control command bus signals and the bi-directional data request bus REQDATA signal of the output of CAM control circuit link to each other with the CAM memory, the CAM control circuit links to each other with the data/address bus of SRAM one-port memory, CAM control circuit input also with the confirmation signal of reading of CAM memory output, search matched signal, searching the output useful signal links to each other, the retrieving information output of CAM control circuit output links to each other with result for retrieval queue memory FIFO, in addition the read signal of CAM control circuit respectively with the input of reading of search instruction queue memory FIFO, CAM maintenance instruction queue memory FIFO reads input and links to each other, CAM control circuit output links to each other with cpu interface circuit, the list item that routing table is preserved sends to cpu interface circuit, the CAM control circuit is counted the information of IPv6 route query times and query hit, these information are sent to cpu interface circuit as query State information, and receive the reset signal sum counter reset signal of cpu interface circuit input;

Result for retrieval queue memory FIFO, be a fifo queue memory, data width is 148, and data input pin links to each other with the output of CAM control circuit, the output of reading of reading input signal and bag transtation mission circuit links to each other, and the input of data output end and bag transtation mission circuit links to each other;

IPv6 packet relevant information queue memory FIFO, be a fifo queue memory, data width is 60, and data input pin extracts circuit with above-mentioned packet-related information and links to each other, the output of reading of reading input signal and bag transtation mission circuit links to each other, and data output end and bag transtation mission circuit link to each other;

CAM maintenance instruction queue memory FIFO, be a fifo queue memory, data width is 90, and data input pin links to each other with cpu interface circuit, the read signal of reading input signal and the output of CAM control circuit links to each other, and data output end links to each other with the data input pin of CAM control circuit;

The bag transtation mission circuit, respectively to result for retrieval queue memory FIFO, IPv6 packet relevant information queue memory FIFO sends read signal, and and result for retrieval queue memory FIFO, the output of IPv6 packet relevant information queue memory FIFO links to each other, the read signal of bag transtation mission circuit output, reading the address links to each other with IPv6 packet memory RAM, data output end and the bag transtation mission circuit of IPv6 packet memory RAM link to each other, the output of bag transtation mission circuit also submits bag queue memory FIFO with the 1st and the outer up FIFO of FPGA sheet links to each other, the bag transtation mission circuit is to the IPv4 of input and output, IPv6 packet header signal and bag tail signal are counted respectively, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;

IPv6 packet memory RAM is the interior read-write memory of the FPGA sheet of a dual-port, there are data to write port and a data output port, data are write inbound port and are linked to each other with the IPv6 data output end that packet-related information extracts circuit, all signals and the bag transtation mission circuit of read port link to each other, IPv6 packet memory RAM data width is 36, and reading-writing port has 14 address wires respectively;

Submit bag queue memory FIFO for the 0th, be a fifo queue memory, data width is 36, and data input pin links to each other with above-mentioned packet filtering circuit, read input signal and link to each other with the output of reading of submitting the bag transtation mission circuit, data output end wraps transtation mission circuit and links to each other with submitting;

Submit bag queue memory FIFO for the 1st, be a fifo queue memory, data width is 36, and data input pin links to each other with the bag transtation mission circuit, read input signal and link to each other with the output of reading of submitting the bag transtation mission circuit, data output end wraps transtation mission circuit and links to each other with submitting;

Submit the bag transtation mission circuit, input and the 0th submit bag queue memory FIFO, submitting bag queue memory FIFO for the 1st links to each other, data output end links to each other with the data input pin of SRAM dual-ported memory, submit the CPU interrupt signal that the bag transtation mission circuit sends, SRAM dual-ported memory data initial address and termination address, wait in the SRAM dual-ported memory that the length signals output that transmits data links to each other with cpu interface circuit, cpu interface circuit is exported to the CPU response signal input of submitting the bag transtation mission circuit, submit the IPv4 of bag transtation mission circuit to input and output, IPv6 packet header signal and bag tail signal are counted respectively, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;

Cpu interface circuit, link to each other with inner each circuit of the tunnel treatment circuit of realizing by FPGA, receive the IPv4 of each circuit input, IPv6 input and output packet header signal and bag tail signal-count, and the query State of CAM control circuit counting, the cpu address bus of the outer CPU control unit of cpu interface circuit and FPGA sheet, data/address bus, read-write control signal links to each other, the interrupt signal of output and the interruption of CPU control unit input link to each other, cpu interface circuit also with the address bus of SRAM dual-ported memory data-out port, data/address bus, read-write control signal links to each other, cpu interface circuit receives the reset signal of CPU control unit input, and send reset signal in the FPGA other each circuit, send reset signal to IP packet input interface circuit, the packet filtering circuit, IPv6 protocol encapsulation circuit, packet-related information extracts circuit, the CAM control circuit, submit the bag transtation mission circuit, the bag transtation mission circuit, cpu interface circuit also links to each other with the data input pin of CAM maintenance instruction queue memory FIFO, receive the routing table list item data of CAM control circuit output, the SRAM dual-ported memory data initial address and the termination address of bag transtation mission circuit output submitted in reception, wait to transmit the length and the interrupt requests information of data in the SRAM dual-ported memory, also send CPU interrupt response index signal to submitting the bag transtation mission circuit;

Described packet filtering circuit is a circuit unit, wherein: input IP bag data register, input links to each other with the output of IP packet input interface circuit; The output of input IP bag data register links to each other with IPv4 packet register, IPv6 packet register respectively; The output of IPv4 packet register links to each other the also output of accepting state controller simultaneously with the input of IPv4 packet delay time register group, IPv4 packet header check and store device, life span register, bag type register, State Control machine respectively; The output of IPv4 packet delay time register group and the input of data selector A link to each other; The input of verification of IPv4 data packet head and maker upgrades register output with IPv4 the output of check and store device, life span respectively and links to each other; The output of life span register links to each other with the input of input that subtracts a subtracter A and State Control machine, the output that subtracts a subtracter A links to each other with the input that life span is upgraded register, and the output that life span is upgraded register links to each other with maker, State Control machine with the verification of IPv4 data packet head respectively; The input of data selector A links to each other with the output of output, the verification of IPv4 data packet head and the maker of IPv4 packet delay time register group and the output of State Control machine respectively again, the output of data selector A with upgrade after IPv4 packet register input link to each other;

The output of IPv6 packet register links to each other with the input of IPv6 packet delay time register group, jumping figure register, next stature register, IPv6 destination address register, State Control machine respectively, the also output of accepting state controller simultaneously; The output of jumping figure register links to each other with the input that subtracts a subtracter B and the State Control machine links to each other, and the output that jumping figure upgrades register also links to each other with the State Control machine; The output that subtracts a subtracter B links to each other with the input that jumping figure upgrades register; The input of data selector B links to each other with the output that IPv6 packet delay time register group, jumping figure are upgraded register, State Control machine respectively, and the output of data selector B links to each other with IPv6 packet register input after the renewal; The input of next stature register links to each other with the output of IPv6 packet register, and output links to each other with the State Control machine; The output of IPv6 destination address register links to each other with the input of comparator, and another input of comparator links to each other with this router IPv6 address register output; The output of comparator links to each other with the input of State Control machine; The output of this router IPv6 address register input and cpu interface circuit links to each other;

The input of data selector C respectively with upgrade after IPv4 packet register, the output of IPv6 packet register after upgrading link to each other, the fast signal of expiring of State Control machine and bag input rank memory FIFO is continuous, the output of data selector C is submitted bag queue memory FIFO with the 0th respectively, bag input rank memory FIFO links to each other, and the packet header signal of while data selector C and bag tail the signal output part also input of sum counter link to each other; Counter receives the counter O reset signal of cpu interface circuit output, and the input that tail signal-count signal sends cpu interface circuit to is wrapped in packet header;

Described IPv6 protocol encapsulation circuit is a circuit unit, wherein: bag input rank memory fifo interface circuit, the data output end of data input pin and bag input rank memory FIFO links to each other, the read signal of output and the input signal of reading of bag input rank memory FIFO link to each other, and the control input/output terminal links to each other with the State Control machine circuit; IPv4 header data register, input and bag input rank memory fifo interface circuit output end and State Control machine circuit output link to each other, an output changes packet header, IPv6 tunnel circuit with IPv4 packet header and links to each other, and another output links to each other with the multi-channel data selector circuit input end; IPv4 load data register, input and bag input rank memory fifo interface circuit output end link to each other, and output links to each other with the multi-channel data selector circuit input end; The IPv6 data register, the output of input and bag input rank memory fifo interface circuit links to each other, and output links to each other with the multi-channel data selector circuit input end; Packet header, IPv6 tunnel data register, input changes IPv6 tunnel packet header circuit with IPv4 packet header and the State Control machine circuit links to each other, and output links to each other with the multi-channel data selector circuit; The output of multi-channel data selector circuit links to each other with the input of IPv6 bag queue memory FIFO; Bag input rank memory fifo interface circuit sends to counter circuit with data packet head signal and the tail signal that receives, the multi-channel data selector circuit also sends the data packet head of output, bag tail signal to counter circuit, the input and output packet header bag tail signal-count of counter circuit output and the state counter value input of cpu interface circuit link to each other, and receive the counter O reset signal of cpu interface circuit input simultaneously;

It is a circuit unit that described packet-related information extracts circuit, form by a series of circuit: IPv6 bag queue memory interface circuit, described data input pin links to each other with IPv6 bag queue memory FIFO, the read signal of output links to each other with the input signal of reading of IPv6 bag queue memory FIFO, the control input/output terminal links to each other with the State Control machine circuit, output with wrap the friendship marker register, the packet priority register, bag source port numbered register, the bag initial address register, bag termination address register, the packet number register, the bag destination address register, Tunnel Identifier register and bag write the RAM circuit and link to each other; The input of IPv6 package informatin transtation mission circuit hands over marker register, packet priority register, bag initial address register, bag source port numbered register, bag termination address register, packet number register to link to each other with described wrapping, control information comes from the State Control machine, output termination IPv6 packet relevant information queue memory FIFO; The input of search instruction transtation mission circuit links to each other with packet number register, bag destination address register, Tunnel Identifier register, and output links to each other with search instruction queue memory FIFO, and the control input end links to each other with the State Control machine; The output that bag writes the RAM circuit links to each other with IPv6 packet memory RAM, and its control input end links to each other with the State Control machine; The input of counter links to each other with the input packet header signal and the input bag tail signal of IPv6 bag queue memory fifo interface circuit respectively, also link to each other with packet header signal and the bag tail signal that bag writes RAM circuit output, also link to each other with the counter O reset signal of cpu interface circuit input simultaneously, the packet header tail signal-count of output links to each other with cpu interface circuit;

Described CAM control circuit is a circuit unit, be made up of a series of circuit: the data input pin of search instruction queue memory fifo interface circuit links to each other with search instruction queue memory FIFO output, the read signal of output and the read signal of search instruction queue memory FIFO link to each other, and output also interconnects with the State Control machine, the control signal of accepting state controller output; CAM writes the input of data register and the output of search instruction queue memory fifo interface circuit and CAM maintenance instruction queue memory fifo interface circuit links to each other, and output links to each other with CAM data/address bus read-write control circuit; The output of the output of the input of CAM operational order transtation mission circuit and search instruction queue memory fifo interface circuit, CAM maintenance instruction queue memory fifo interface circuit links to each other, and output directly links to each other with command line INST, LTIN, SEGSEL, GMASK, CRB and the request gating signal REQSTB of CAM memory; SRAM writes the input and the CAM maintenance instruction queue memory fifo interface circuit output end of data register, and the output of search instruction queue memory fifo interface circuit is continuous, and output links to each other with SRAM data/address bus read-write control circuit input; The output of SRAM data/address bus read-write control circuit links to each other with SRAM read data register, result for retrieval register and SRAM one-port memory, and output links to each other signal input end with state machine; The output of the input of CPU read data register and CAM read data register, the output of SRAM read data register link to each other, and output links to each other with cpu interface circuit; The input of result for retrieval register links to each other with the output of sequence of data packet register, and output links to each other with result for retrieval queue memory FIFO; The input of sequence of data packet register links to each other with the output of search instruction queue memory fifo interface circuit and the output of State Control machine; The input of counter links to each other with the output of result for retrieval register, and also the calculator reset signal with the cpu interface circuit input links to each other, and the query State counting output of its output links to each other with cpu interface circuit;

Described bag transtation mission circuit is a circuit unit, form by a series of circuit: IPv6 packet relevant information queue memory fifo interface circuit, data input pin links to each other with the output of IPv6 packet relevant information queue memory FIFO, the control input and output side links to each other with the state machine control circuit, the read signal of output is read input with IPv6 packet relevant information queue memory FIFO and is linked to each other, and output is stored initial address register with bag respectively, bag storage termination address register, the packet length register, the packet priority register, the source port numbered register, the input of packet number register A links to each other; Result for retrieval queue memory fifo interface circuit, data input pin links to each other with the output of result for retrieval queue memory FIFO, the control input and output side links to each other with the state machine control circuit, and output links to each other with the input of packet number register B, destination interface numbered register, purpose ply-yarn drill numbered register, next-hop IP v6 address register, next-hop IP v4 address register, tunnel IPv6 destination address register respectively; Bit wide is that the input of 36 additional data registers group links to each other with the data output end of packet priority register, packet length register, source port numbered register, source ply-yarn drill numbered register, destination interface numbered register, purpose ply-yarn drill numbered register, next-hop IP v6 address register, next-hop IP v4 address register, tunnel IPv6 destination address register respectively; The input of source ply-yarn drill numbered register is from cpu interface circuit; Increase 10 adders, the output of input and bag storage initial address links to each other, and output links to each other with address register A; The output of the input of address register B and bag storage initial address links to each other; The output that increases 1 adder is read the output of address register with the IPv6 packet memory respectively, the input of address register C links to each other; Multi-channel data selector A, input link to each other with address register A, address register B, address register C respectively, and the control input end links to each other with the output of state machine control circuit, and output links to each other with the input that the IPv6 packet memory is read address register; Data comparator A, the output of input and bag storage termination address register and the output that the IPv6 packet memory is read address register link to each other, and output links to each other with the input of state machine control circuit; Bit wide is 36 an IP data register, and input links to each other with the data output end of IPv6 packet memory RAM, and output links to each other with the input of multi-channel data selector B; Multi-channel data selector B, data input pin is that the output of 36 additional data registers group, the output of IP data register that bit wide is 36 link to each other with bit wide respectively, output with submit packet register, the IPv4 of band additional data or the input of IPv6 packet register and link to each other; The output of submitting the packet register links to each other with the 1st input of submitting bag queue memory FIFO; The output of the IPv4 of band additional data or IPv6 bag register mails to the up FIFO that links to each other with FPGA; Band IPv4 of additional data or IPv6 bag register also send data packet head signal and the bag tail signal that sends to counter respectively, counter also links to each other with the counter O reset signal of cpu interface circuit input, and the packet header bag tail signal-count signal of counter output sends to cpu interface circuit;

Described CAM memory, it is the FPGA chip external memory of system, read-write control command bus signals and request of data bus REQDATA signal are from the CAM control circuit, the address bus signal of output links to each other with read-write with the address bus of SRAM one-port memory respectively with read-write, the reading confirmation signal, search matched signal, search and export useful signal and link to each other with CAM control circuit input of output;

Described SRAM one-port memory is the outer static SRAM memory of FPGA sheet of system, and read-write input signal and address signal are from the output of CAM memory, and the data input/output terminal links to each other with the CAM control circuit;

Described SRAM dual-ported memory, it is the outer static dual-port SRAM memory of FPGA sheet of system, be divided into data and write inbound port and data-out port, the BDB Bi-directional Data Bus that data are write inbound port with submit the bag transtation mission circuit and link to each other, data are write reading writing signal line, the address bus of inbound port and are submitted the output that wraps transtation mission circuit and link to each other, the BDB Bi-directional Data Bus of data-out port links to each other with cpu interface circuit, and the output of the reading writing signal line of data-out port, address bus and cpu interface circuit links to each other.

2. adopt the tunnel repeater system of IPv6 head encapsulation IPv4 bag in the router according to claim 1, it is characterized in that: described CAM is made of two IDT75k62100 chips, and the SRAM one-port memory is made of two IDT71T75602 chips.

3. adopt the tunnel repeater system of IPv6 head encapsulation IPv4 bag in the router according to claim 1, it is characterized in that: FPGA links to each other with the outer CPU control unit of sheet.

4. adopt the tunnel repeater system of IPv6 head encapsulation IPv4 bag in the router according to claim 1, the SRAM dual-ported memory is made of a slice CY7C1300A chip.

5. adopt the tunnel repeater system of IPv6 head encapsulation IPv4 bag in the router according to claim 1, FPGA and peripheral chip adopt same master clock CLK to carry out work, the shared master clock CLK of IDT75k62100 and FPGA, the operating frequency of two IDT71T75602 is CLK/2, the clock source of this CLK/2 and main CLK is identical, is that the CLK master clock obtains through two divided-frequency.

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