CN101673689A - Integrated circuit packaging method and circuit device capable of reducing power supply voltage drop of chip - Google Patents
Integrated circuit packaging method and circuit device capable of reducing power supply voltage drop of chip Download PDFInfo
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- CN101673689A CN101673689A CN200810148804A CN200810148804A CN101673689A CN 101673689 A CN101673689 A CN 101673689A CN 200810148804 A CN200810148804 A CN 200810148804A CN 200810148804 A CN200810148804 A CN 200810148804A CN 101673689 A CN101673689 A CN 101673689A
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Abstract
The invention discloses an integrated circuit packaging method and a circuit device, which can reduce power supply voltage drop of a chip and eliminate the power supply voltage drop so as to improve the system stability and reduce the production cost. The integrated circuit packaging method comprises the following steps: forming a lead wire frame which comprises a chip tray and a plurality of pins; fixing the chip on the chip tray, and coupling a plurality of signal receiving and output ends of the chip to the plurality of pins; forming a power supply transmission unit which is coupled with apower supply; coupling a plurality of power supply receiving ends of a logic gate unit of the chip to the power supply transmission unit; and forming a shell body for covering the chip, the lead wireframe and the power supply transmission unit.
Description
Technical field
The present invention relates to integrated circuit encapsulation, refer to especially a kind ofly a plurality of power delivery unit is set and the power supply receiving terminal of the logic lock unit of chip directly is coupled to the power delivery unit to eliminate integrated circuit packaging method and the integrated circuit related with same device thereof that supply voltage falls.
Background technology
The integrated circuit encapsulation belongs to the back segment procedure for processing of semiconductor industry, mainly is the integrated circuit on the wafer is cut apart, sticked crystalline substance, and adds external pin and coating.And its finished product (packaging body) mainly provides one and draws the interface that connects, and inner electrically signal can see through encapsulating material, and for example pin is connected to system, and provides silicon to avoid being subjected to external force and water, moisture, chemicals to destroy and corrode etc.Common integrated circuit packaged type includes dual in-line package (Dual In-line Package, DIP), the flat encapsulation of plastics square (Plastic Quad Flat Package, PQFP), plastic flat encapsulation (Plastic FlatPackage, PFP), pin grid array encapsulation (Pin Grid Array Package, PGA), ball bar array encapsulation (Ball Grid Array Package, BGA) etc.
The integrated circuit encapsulation is made up of chip, lead frame (Lead Frame) and housing.Please refer to Fig. 1, Fig. 1 shows the cut-away view of existing integrated circuit (IC) apparatus 10, includes chip 102, chip tray (DiePaddle) 104, pin (Finger) 106, gold thread 108 and housing 100.Chip 102 is the core cell of integrated circuit (IC) apparatus 10, is used for carrying out the analog or digital signal and handles.Chip tray 104 is a lead frame with pin 106, and carries chips 102 and welding gold thread 108 make signal be able to smooth transmission.Housing 100 is used for filling die cavity (Cavity), with the protection integrated circuit (IC) apparatus 10, its material can be pottery or plastics, as thermosetting epoxy resin (Epoxy Molding Compound, EMC).Generally speaking, gold thread 108 is about 1nH/mm (every millimeter of nanohenry) and 0.8nH/mm with the inductance value of pin 106, for example in the flat encapsulation of slim square (Low Profile Quad Flat Package) of 256 pins, gold thread 108 is 3mm and 8 ~ 10mm with the length of pin 106, and formed equivalent inductance value then is about 10.2nH.
Before the 0.25um processing procedure, generally all the power grid on the chip 102 (Power Grid) is used as ideal network.In fact, this hypothesis is non-existent on integrated circuit (IC) design, and especially when integrated circuit manufacture process evolved to 0.18um and following super deep-sub-micrometer, the width of wire rod was more and more narrow, causes its resistance value to rise.In this case, all online impedance operators that comprise electric power network become very obvious, cause the decline or the rising of voltage on the power supply and zone network in the integrated circuit, that is magnitude of voltage no longer is to have stablized constant single value, this phenomenon is called supply voltage and falls (IR Drop), and the size that supply voltage falls then depends on the size from power pins to the equivalent resistance the logic lock unit.
The schematic diagram of Fig. 2 display chip 102 internal logic circuits 20, the logic lock unit of G1, G2, G3, G4 presentation logic circuit 20, R11～R18 represents the equivalent resistance of respective path, and IG1, IG2, IG3, IG4 presentation logic lock unit G1, G2, G3, G4 institute consumed current.Logical circuit 20 sees through pin Pad1, Pad2 and receives supply voltage VDD and ground voltage VSS, when switch motion, if logic lock unit G4 running is only arranged, and the electric current of other logic lock unit all is 0, and then the supply voltage of the supply voltage VDD of G4 place, logic lock unit is reduced to: IG4 * (R11+R12+R13+R14); And the supply voltage of the logic lock unit supply voltage VDD of G2 place is reduced to: IG4 * (R11+R12).In other words, the electric current of each logic lock unit all can cause supply voltage in various degree to fall to other logic lock unit.If be connected to the online logic lock unit of metal upset (switch) action is arranged simultaneously, the supply voltage general who has surrendered can be very big so.Yet during some was used, Fan Zhuan action simultaneously was essential, for example frequency network and its buffer that is driven.In addition, to fall may be local or comprehensive to supply voltage.When the logic lock unit of adjacent position some has the logic rotary movement simultaneously, just cause locally supplied power source's voltage drop phenomenon, and the resistance value of a certain specific portion of power grid also can cause locally supplied power source's voltage drop when high especially.
When the supply voltage of chip falls when too high, although the logical simulation display design is correct, functional fault still can take place in logic lock unit, the problem that chip was thoroughly lost efficacy.Usually having the redesign layout type only just can address the above problem.Therefore, the power supply design has become one of key factor of chip design success or not.
Summary of the invention
Technical problem to be solved by this invention provides a kind of integrated circuit packaging method that reduces power supply voltage drop of chip, and it not only can reduce power supply voltage drop of chip, and has reduced production cost.For this reason, the present invention also provides a kind of integrated circuit (IC) apparatus that reduces power supply voltage drop of chip in addition.
In order to solve above technical problem, the invention provides following technical scheme:
At first, the invention provides a kind of integrated circuit packaging method that reduces power supply voltage drop of chip, it includes the formation lead frame, and lead frame comprises chip tray and a plurality of pin; Chip is fixed on the chip tray, and the plurality of signals reception and the output of chip is coupled to this a plurality of pins; Form the power delivery unit, the power delivery unit is coupled to power supply; The power supply receiving terminal of a plurality of logic locks unit of this chip is coupled to this power delivery unit; And the formation housing, in order to coating chip, lead frame and power delivery unit.
In addition, the present invention also provides a kind of integrated circuit (IC) apparatus that supply voltage falls that reduces, and it includes lead frame, comprises chip tray and a plurality of pin; The power delivery unit can be coupled to power supply; Chip is fixed on this chip tray, include plurality of signals reception and output and be coupled to this a plurality of pins, and the power supply receiving terminal of a plurality of logic locks unit is coupled to this power delivery unit; And housing, in order to coating chip, lead frame and power delivery unit.
The present invention adopts integrated circuit packaging method and integrated circuit related with same device thereof that the power supply receiving terminal of logic lock unit directly is coupled to the power delivery unit, the supply voltage that makes each logic lock unit be received can not be subjected to online impedance operator between logic lock unit and change, the elimination supply voltage falls, and then promoted stiffness of system, and reduced production cost.
Description of drawings
Fig. 1 is the cut-away view of existing integrated circuit (IC) apparatus.
Fig. 2 is the schematic diagram of Fig. 1 chips internal logic circuit.
Fig. 3 is embodiment of the invention integrated circuit encapsulation flow chart.
Fig. 4 is the schematic diagram of embodiment of the invention chip internal logical circuit.
Fig. 5 is the cut-away view of embodiment of the invention integrated circuit (IC) apparatus.
Fig. 6 is the cut-away view of embodiment of the invention integrated circuit (IC) apparatus.
Fig. 7 is the birds-eye perspective of the integrated circuit (IC) apparatus of Fig. 6.
Fig. 8 is the cut-away view of embodiment of the invention integrated circuit (IC) apparatus.
Fig. 9 is the birds-eye perspective of the integrated circuit (IC) apparatus of Fig. 8.
Figure 10 is the side perspective of the integrated circuit (IC) apparatus of Fig. 8.
Figure 11 is provided with the schematic diagram of a plurality of power delivery unit for the integrated circuit (IC) apparatus of Fig. 8.
Figure 12 is provided with the schematic diagram of a plurality of power delivery subelements for the integrated circuit (IC) apparatus of Fig. 8.
[primary clustering symbol description]
10,50,60,80 integrated circuit (IC) apparatus
102,502,602,802 chips
104,504,604,804 chip trays
106, Pad1, Pad2,506,606,806 pins
108,508,608,808 gold threads
100,500,600,800 housings
G1, G2, G3, G4, GI1, GI2, GI3, GI4 logic lock unit
R11～R18, RI1～RI4 equivalent resistance
IG1, IG2, IG3, IG4, IGI1, IGI2, IGI3, IGI4 electric current
The VDD supply voltage
The VSS ground voltage
30 integrated circuits encapsulation flow process
300,302,304,306,308,310,312 steps
P1, P2, P3, P4 power supply receiving terminal
42,612,812,816,818,820 power delivery unit
822,824 power delivery subelements
44 power supplys
814 insulation unit
Embodiment
Please refer to Fig. 3, Fig. 3 is the flow chart of embodiment of the invention integrated circuit encapsulation flow process 30, and the supply voltage that can reduce chip falls, and it comprises following steps:
Step 300: beginning.
Step 302: form lead frame, comprise chip tray and a plurality of pin;
Step 304: chip is fixed on the chip tray, and the plurality of signals reception and the output of chip is coupled to a plurality of pins;
Step 306: form the power delivery unit, the power delivery unit can be coupled to power supply;
Step 308: the power supply receiving terminal of a plurality of logic locks unit of chip is coupled to the power delivery unit; And
Step 310: form housing, in order to coating chip, lead frame and power delivery unit.
Step 312: finish
According to integrated circuit encapsulation flow process 30, chip is fixed on the chip tray of lead frame, and the signal of chip is received and output, for example see through gold thread, be coupled to the pin of lead frame, make signal be able to smooth transmission.On the other hand, in step 306, the present invention forms the power delivery unit in addition, is used for transmitting power supply, and the power supply receiving terminal of a plurality of logic locks unit of chip then is coupled to the power delivery unit.In this embodiment, be used for receiving power supply and directly be coupled to the power delivery unit with the power supply receiving terminal that drives each logic lock unit, the supply voltage that makes each logic lock unit be received can not be subjected to the online impedance operator between logic lock unit and change, as shown in Figure 4.In Fig. 4, GI1, GI2, GI3, GI4 represent the logic lock unit of a logical circuit 40, and RI1～RI4 represents the equivalent resistance of respective path, and IGI1, IGI2, IGI3, IGI4 presentation logic lock unit GI1, GI2, GI3, GI4 institute consumed current.The power supply receiving terminal P1 of logic lock unit GI1, GI2, GI3, GI4, P2, P3, P4 are respectively coupled to a power delivery unit 42, in order to receive the power supply that a power supply 44 is exported.As shown in Figure 4, logic lock unit GI1, GI2, GI3, GI4 all independently are coupled to power delivery unit 42, and therefore, the unlatching of arbitrary logic lock unit can not influence the power supply that other logic lock unit is received, thereby the problem that can avoid supply voltage to fall.What pay special attention to is, Fig. 4 is used for illustrating the spirit of integrated circuit encapsulation flow process 30, has omitted signal reception and output, lead frame etc., in the hope of succinctly.
On the other hand, in integrated circuit encapsulation flow process 30, chip tray can be held with being coupled to, and a plurality of earth terminals of chip are respectively coupled to chip tray, to avoid the earthed voltage change of logic lock unit.In addition,, a power pins in a plurality of pins can be set at the power delivery unit, that is the power supply receiving terminal of a plurality of logic locks unit of chip directly is coupled to power pins about the implementation of power delivery unit; Perhaps, be similar to remittance row formula framework, form the power delivery unit with conductive material.
For instance, please refer to Fig. 5, Fig. 5 is the cut-away view of embodiment of the invention integrated circuit (IC) apparatus 50, includes chip 502, chip tray 504, pin 506, gold thread 508 and housing 500.Chip 502 is the core cell of integrated circuit (IC) apparatus 50, is used for carrying out the analog or digital signal and handles.Chip tray 504 is a lead frame with pin 506, and carries chips 502 and welding gold thread 508 make signal be able to smooth transmission, and reach the demand of system.Housing 500 is used for filling die cavity, and with protection integrated circuit (IC) apparatus 50, its material can be pottery or plastics, as thermosetting epoxy resin.In addition, in integrated circuit (IC) apparatus 50, power pins 510 is used for realizing power delivery of the present invention unit, and the power supply receiving terminal of logic lock unit directly is coupled to power pins 510 in the chip 502.
See through integrated circuit (IC) apparatus 50, the power supply receiving terminal of logic lock unit directly is coupled to power pins 510, and therefore, the supply voltage that each logic lock unit is received can not be subjected to online impedance operator between logic lock unit and change, and falls to eliminate supply voltage.In addition, chip tray 504 can be held (not being plotted among Fig. 5) in addition with being coupled to, and chip 502 a plurality of earth terminals are respectively coupled to chip tray 504, to avoid the earthed voltage change of logic lock unit.On the other hand, integrated circuit (IC) apparatus 50 can be provided with other power pins in diverse location in addition, corresponding to identical or different voltage, and suitably insulation, its implementation is identical with power pins 510, does not give unnecessary details at this.
Fig. 6 is embodiment of the invention integrated circuit (IC) apparatus 60 cut-away views, and Fig. 7 is integrated circuit (IC) apparatus 60 birds-eye perspectives.Integrated circuit (IC) apparatus 60 includes chip 602, chip tray 604, pin 606, gold thread 608, housing 600 and power delivery unit 612.Power delivery unit 612 is formed at and is different from chip tray 604 zones in the housing 600, and is extended by power pins 610, and the power supply receiving terminal of logic lock unit directly is coupled to power delivery unit 612 in the chip 602.
See through integrated circuit (IC) apparatus 60, the power supply receiving terminal of logic lock unit directly is coupled to power delivery unit 612, and therefore, the supply voltage that each logic lock unit is received can not be subjected to online impedance operator between logic lock unit and change, and falls to eliminate supply voltage.In addition, chip tray 604 can be held (not being plotted among 6 figure and Fig. 7) in addition with being coupled to, and chip 602 a plurality of earth terminals are respectively coupled to chip tray 604, to avoid the earthed voltage change of logic lock unit.On the other hand, integrated circuit (IC) apparatus 60 can be provided with other power delivery unit in diverse location in addition, corresponding to identical or different voltage, and suitably insulation, its implementation is identical with power delivery unit 612, does not give unnecessary details at this.
Fig. 8 is embodiment of the invention integrated circuit (IC) apparatus 80 cut-away views, and Fig. 9 is integrated circuit (IC) apparatus 80 birds-eye perspectives, and Figure 10 is integrated circuit (IC) apparatus 80 side perspective.Integrated circuit (IC) apparatus 80 includes chip 802, chip tray 804, pin 806, gold thread 808, housing 800 and power delivery unit 812.Power delivery unit 812 is formed at the top of housing 800 chips pallets 804, and power delivery unit 812 and 804 of chip trays be provided with insulation unit 814, is used for isolated power delivery unit 812 and chip tray 804.Power delivery unit 812 sees through gold thread and is coupled to power pins 810, and the power supply receiving terminal of logic lock unit directly is coupled to power delivery unit 812 in the chip 802.
See through integrated circuit (IC) apparatus 80, the power supply receiving terminal of logic lock unit directly is coupled to power delivery unit 812, therefore, the supply voltage that each logic lock unit is received can not be subjected to online impedance operator between logic lock unit and change, fall to eliminate supply voltage, chip tray 804 can be held (not being plotted among Fig. 8, Fig. 9 and Figure 10) in addition with being coupled to, and chip 802 a plurality of earth terminals are respectively coupled to chip tray 804, to avoid the earthed voltage change of logic lock unit.On the other hand, integrated circuit (IC) apparatus 80 can be provided with other power delivery unit in diverse location in addition, corresponding to identical or different voltage, and suitably insulation, shown in Figure 11 and the 12nd figure.In Figure 11, other three limit of chip 802 is provided with power delivery unit 816,818,820, corresponds respectively to different voltages, and adjacent power delivery unit is provided with the insulation unit; And in Figure 12, power delivery unit 812 is divided into power delivery subelement 822,824, and corresponding to different voltages, to be applicable to the running of multivoltage source chip.
In sum, the present invention directly is coupled to the power delivery unit with the power supply receiving terminal of logic lock unit, the supply voltage that makes each logic lock unit be received can not be subjected to online impedance operator between logic lock unit and change, fall to eliminate supply voltage, and then the elevator system stability, and reduce production costs.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. integrated circuit packaging method that can reduce power supply voltage drop of chip is characterized in that it includes:
Form a lead frame, this lead frame comprises a chip tray and a plurality of pin;
This chip is fixed on this chip tray, and the plurality of signals reception and the output of this chip is coupled to this a plurality of pins;
Form a power delivery unit, this power delivery unit can be coupled to a power supply;
The power supply receiving terminal of a plurality of logic locks unit of this chip is coupled to this power delivery unit; And
Form a housing, in order to coat this chip, this lead frame and this power delivery unit.
2. the integrated circuit packaging method that reduces power supply voltage drop of chip as claimed in claim 1 is characterized in that, wherein this chip tray is coupled to a ground end.
3. the integrated circuit packaging method that reduces power supply voltage drop of chip as claimed in claim 2 is characterized in that, its a plurality of earth terminals that comprise in addition this chip are coupled to this chip tray.
4. the described integrated circuit packaging method that reduces power supply voltage drop of chip as claimed in claim 1 is characterized in that, wherein this power delivery unit can be coupled to this power supply through a pin in these a plurality of pins.
5. the described integrated circuit packaging method that reduces power supply voltage drop of chip as claimed in claim 1 is characterized in that wherein this power delivery unit is formed at the zone that is different from this chip tray in this housing.
6. the described integrated circuit packaging method that reduces power supply voltage drop of chip as claimed in claim 1 is characterized in that wherein this power delivery unit comprises a plurality of power delivery subelements, and each power delivery subelement is corresponding to a specific voltage.
7. one kind can be reduced the integrated circuit (IC) apparatus that supply voltage falls, and it is characterized in that it includes:
One lead frame comprises a chip tray and a plurality of pin;
One power delivery unit can be coupled to a power supply;
One chip is fixed on this chip tray, include plurality of signals reception and output and be coupled to this a plurality of pins, and the power supply receiving terminal of a plurality of logic locks unit is coupled to this power delivery unit; And
One housing is in order to coat this chip, this lead frame and this power delivery unit.
8. as claimed in claim 7ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that wherein this chip tray is coupled to a ground end.
9. as claimed in claim 8ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that wherein this chip comprises a plurality of earth terminals in addition, be coupled to this chip tray.
10. as claimed in claim 7ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that wherein this power delivery unit is a pin that is coupled to this power supply in these a plurality of pins.
11. as claimed in claim 7ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that wherein this power delivery unit is to see through that a pin is coupled to this power supply in these a plurality of pins.
12. as claimed in claim 7ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that wherein this power delivery unit is formed at the zone that is different from this chip tray in this housing.
13. as claimed in claim 7ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that wherein this power delivery unit is formed at this chip tray top.
14. as claimed in claim 13ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that it comprises an insulation unit in addition, is located between this power delivery unit and this chip tray.
15. as claimed in claim 7ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that wherein this power delivery unit comprises a plurality of power delivery subelements, each power delivery subelement is corresponding to a specific voltage.
16. as claimed in claim 15ly reduce the integrated circuit (IC) apparatus that supply voltage falls, it is characterized in that it comprises a plurality of insulation unit in addition, be located at respectively in these a plurality of power delivery subelements between adjacent power delivery subelement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810148804A CN101673689A (en) | 2008-09-12 | 2008-09-12 | Integrated circuit packaging method and circuit device capable of reducing power supply voltage drop of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810148804A CN101673689A (en) | 2008-09-12 | 2008-09-12 | Integrated circuit packaging method and circuit device capable of reducing power supply voltage drop of chip |
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| CN101673689A true CN101673689A (en) | 2010-03-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200810148804A Pending CN101673689A (en) | 2008-09-12 | 2008-09-12 | Integrated circuit packaging method and circuit device capable of reducing power supply voltage drop of chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108573957A (en) * | 2017-03-14 | 2018-09-25 | 瑞昱半导体股份有限公司 | Semiconductor package |
| US10446516B2 (en) | 2017-03-08 | 2019-10-15 | Realtek Semiconductor Corporation | Semiconductor package structure |
-
2008
- 2008-09-12 CN CN200810148804A patent/CN101673689A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10446516B2 (en) | 2017-03-08 | 2019-10-15 | Realtek Semiconductor Corporation | Semiconductor package structure |
| CN108573957A (en) * | 2017-03-14 | 2018-09-25 | 瑞昱半导体股份有限公司 | Semiconductor package |
| CN108573957B (en) * | 2017-03-14 | 2020-05-05 | 瑞昱半导体股份有限公司 | Semiconductor packaging structure |
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Application publication date: 20100317 |