CN101667905B - Method and device for switching clock integrated circuit boards - Google Patents
Method and device for switching clock integrated circuit boards Download PDFInfo
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- CN101667905B CN101667905B CN2008101193754A CN200810119375A CN101667905B CN 101667905 B CN101667905 B CN 101667905B CN 2008101193754 A CN2008101193754 A CN 2008101193754A CN 200810119375 A CN200810119375 A CN 200810119375A CN 101667905 B CN101667905 B CN 101667905B
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Abstract
The invention discloses a method and a device for switching clock integrated circuit boards. The method comprises the following steps: a first clock integrated circuit board and a second clock integrated circuit board send heartbeat signals and working state information to each other through a communication interface between the integrated circuit boards; and the first clock integrated circuit board and the second clock integrated circuit board determine whether to initiate active-standby status switching according to the heartbeat signals, the active and standby statuses and the working state information of the two clock integrated circuit boards, and send enabling signals to each other through a two-computer logical connection interface between the first clock integrated circuit board and the second clock integrated circuit board so that the active and standby statues of the first clock integrated circuit board and the second clock integrated circuit board are maintained to be mutually exclusive. The method and the device can be widely applied to clock synchronization devices in need of two-computer mutual control in the field of digital communication, and can efficiently improve the stability and the accuracy of service transmission.
Description
Technical field
The present invention relates to Clock Synchronization Technology, particularly a kind of changing method of clock integrated circuit boards, a kind of clock integrated circuit boards, a kind of clock synchronization device.
Background technology
Be the basis of the intercommunication of various device in the communication network synchronously, if do not have good synchronously, digital information just phenomenons such as error code, slip can occur inevitably in transmittance process, thereby causes the decline of communication quality.According to the difference of business, its influence degree is also different.For example, for voice call, can hear click; Facsimile service can cause information incomplete; The data service packet loss can increase; Image transmits and phenomenons such as smudgy can occur.Therefore in order to ensure quality of service, clock synchronization device is absolutely necessary in communication network reliably.
Clock stable in order to ensure equipment is reliable, and the equipment with synchronizing function generally all carries out Hot Spare to the clock synchronization integrated circuit board, has the two boards card to work simultaneously, and one as the main board card, other one as subsequent use integrated circuit board.After the main board card broke down, the standby plate clamping worked on for the main board card.Take in the process at this, generally use following scheme:
Scheme one: when two clock integrated circuit boards work, two integrated circuit boards send heartbeat signal mutually, and heartbeat signal is lost if subsequent use integrated circuit board is found the main board card; So subsequent use integrated circuit board is upgraded to the main board card; Be equipment output clock, former main board card is clock signal not just, this scheme advantage be realize simple.
But its deficiency is: when the main board card breaks down; The standby plate calorie requirement is judged through software, can know that main board breaks down, and this time is generally all long; Therefore transition can appear in the clock of system's output alternately the time, influence output clock index.And heartbeat signal is to software system design, if active clock integrated circuit board output clock failure monitors through the heartbeat detection mode so that to change fault very inconvenient.
Scheme two: when two clock integrated circuit boards work, mutual communication is sent the information of representing operating state mutually; Comprise in these information whether the output clock has fault etc., when subsequent use integrated circuit board was found the information of main board card output clock failure information or other expression working state abnormal, it was subsequent use to notify the other side to reduce to like this; Subsequent use integrated circuit board is upgraded to main using; Be equipment output clock, former main board card is clock signal not just, and this scheme advantage is to know the other side's operating state.
But its deficiency is: send the mode of work state information mutually, all realize with software, need the time longer, so influence output clock index also transition can appear, in the output clock of system alternately the time.Fortunately the other side's clock status can be known than scheme one, whether fault of main board output clock can be judged.
Scheme three: when two clock integrated circuit boards work; Realize the control of hardware mode through the cross complaint line that connects between two integrated circuit boards, after this plate of main board card breaks down, reduce to subsequent use integrated circuit board; Subsequent use integrated circuit board is upgraded to the main board card; Be equipment output clock, former main board card is clock signal not just, this scheme advantage be switch fast.
But its deficiency is: realize through hardware mode, the other side's state is judged not enough, can't understand the present detailed status of the other side, in the other side's fault or unsettled the time, occur ping-pong easily, can cause and switch back and forth between active and standby.
Therefore, the deficiency that exists of prior art is: the main/stand-by clock integrated circuit board exists when switching that speed is slow, handoff procedure influence output clock, system have problems such as ping-pong.
Summary of the invention
The present invention provides a kind of changing method of clock integrated circuit boards, a kind of clock integrated circuit boards, a kind of clock synchronization device, exists in order to solve in the prior art at the main/stand-by clock integrated circuit board that speed is slow when switching, handoff procedure influence output clock, system have problems such as ping-pong.
A kind of changing method of clock integrated circuit boards is provided in the embodiment of the invention, has comprised the steps:
First clock integrated circuit boards and second clock integrated circuit board send heartbeat signal timely mitriform attitude through the communication interface between the integrated circuit board mutually;
First clock integrated circuit boards and second clock integrated circuit board according to both sides' heartbeat signal, active and standbyly determine whether to initiate active and standbyly to switch with state with the timely mitriform attitude of state, and send enable signal to make first clock integrated circuit boards mutually and the second clock integrated circuit board is active and standby keeps mutual exclusion with state through the two-shipper logic connecting interface between first clock integrated circuit boards and the second clock integrated circuit board.
A kind of clock integrated circuit boards also is provided in the embodiment of the invention, has comprised:
Heartbeat module is used to produce heartbeat signal;
The state information acquisition module is used to obtain the clock integrated circuit boards clock status;
Communication interface modules is used for the heartbeat signal and the clock status of tranmitting data register integrated circuit board, receives the heartbeat signal and the clock status of outside input;
Handover module is used for the heartbeat signal, active and standby with the timely mitriform attitude of state according to clock integrated circuit boards, and the heartbeat signal of outside input and clock status determine whether to initiate active and standbyly to switch with state;
The mutual exclusion module is used for keeping mutual exclusion through external equipment and the active and standby of clock integrated circuit boards that two-shipper logic connecting interface send enable signal to make to link to each other with this interface mutually with state.
A kind of clock synchronization device also is provided in the embodiment of the invention, has comprised first clock integrated circuit boards, second clock integrated circuit board, also comprised:
First heartbeat module links to each other with first clock integrated circuit boards, is used to produce heartbeat signal;
Second heartbeat module links to each other with the second clock integrated circuit board, is used to produce heartbeat signal;
The first state information acquisition module links to each other with first clock integrated circuit boards, is used to obtain the clock integrated circuit boards clock status;
The second state information acquisition module links to each other with the second clock integrated circuit board, is used to obtain the clock integrated circuit boards clock status;
First communication interface modules links to each other with first clock integrated circuit boards, is used to send the heartbeat signal and the clock status of first clock integrated circuit boards, receives the heartbeat signal and the clock status of second clock integrated circuit board;
The second communication interface module links to each other with the second clock integrated circuit board, is used to send the heartbeat signal and the clock status of second clock integrated circuit board, receives the heartbeat signal and the clock status of first clock integrated circuit boards;
First handover module links to each other with first clock integrated circuit boards, is used for according to the heartbeat signal that receives, active and standbyly determines whether to initiate active and standbyly to switch with state with the timely mitriform attitude of state;
Second handover module links to each other with the second clock integrated circuit board, is used for according to the heartbeat signal that receives, active and standbyly determines whether to initiate active and standbyly to switch with state with the timely mitriform attitude of state;
The first mutual exclusion module links to each other with first clock integrated circuit boards, is used for sending enable signal to make second clock integrated circuit board and the active and standby of first clock integrated circuit boards keep mutual exclusion with state mutually through two-shipper logic connecting interface;
The second mutual exclusion module links to each other with the second clock integrated circuit board, is used for sending enable signal to make first clock integrated circuit boards and the active and standby of second clock integrated circuit board keep mutual exclusion with state mutually through two-shipper logic connecting interface.
Beneficial effect of the present invention is following:
In embodiments of the present invention; Owing on clock integrated circuit boards, be provided with communication interface; Therefore can know the other side's heartbeat signal and work state information through communication interface, thereby whether the operating state that can judge both sides there is fault and knows whether both sides' heartbeat is normal; Simultaneously, also on clock integrated circuit boards, be provided with two-shipper logic connecting interface, make clock integrated circuit boards to send enable signal mutually, thereby make the active and standby of clock integrated circuit boards keep mutual exclusion with state through two-shipper logic connecting interface.Promptly; Not only can be accurately according to both sides' heartbeat signal, active and standbyly determine whether to initiate active and standbyly to switch with state with state and work state information; Also utilize two-shipper logic connecting interface to guarantee to switch fast between the clock integrated circuit boards; Solved that present two-shipper switches that medium velocity is slow, handoff procedure influence output clock, system have problems such as ping-pong, simultaneously because according to obtaining heartbeat signal, active and standbyly switching with state and work state information; Therefore can not occur the other side's state is judged deficiency, can't know the situation of the detailed status that the other side is present.
Description of drawings
Fig. 1 is the changing method implementing procedure sketch map of clock integrated circuit boards described in the embodiment of the invention;
Fig. 2 is a clock integrated circuit boards structural representation described in the embodiment of the invention;
Fig. 3 is a clock synchronization device structural representation described in the embodiment of the invention;
The clock synchronization device hardware configuration sketch map of Fig. 4 for realizing described in the embodiment of the invention that the doubleclocking integrated circuit board switches;
Fig. 5 is for detecting the processing implementing procedure sketch map of heartbeat signal when unusual described in the embodiment of the invention;
Fig. 6 is the processing implementing procedure sketch map when detecting the active clock fault described in the embodiment of the invention;
Fig. 7 is the processing implementing procedure sketch map when detecting the standby clock fault described in the embodiment of the invention.
Embodiment
Describe below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 1 is the changing method implementing procedure sketch map of clock integrated circuit boards, and is as shown in the figure, when carrying out the clock integrated circuit boards switching, can comprise the steps:
Concrete, step 102 can be implemented as follows:
First clock integrated circuit boards and second clock integrated circuit board confirm according to work state information whether the other side's clock integrated circuit boards and this plate break down, and after confirming that according to heartbeat signal both sides' heartbeat is whether unusual, carry out by following scheme:
First clock integrated circuit boards and second clock integrated circuit board if this plate is a stand-by state, then initiate active and standbyly to switch with state when this plate fault-free and the other side's clock integrated circuit boards have fault;
First clock integrated circuit boards and second clock integrated circuit board are when this plate fault-free and the other side's clock integrated circuit boards have fault, if this plate is mainly to use state, then forbid initiating active and standbyly switching with state;
When first clock integrated circuit boards and second clock integrated circuit board have fault and the other side's clock integrated circuit boards fault-free at this plate,, then forbid initiating active and standbyly switching with state if this plate is stand-by state;
When first clock integrated circuit boards and second clock integrated circuit board have fault and the other side's clock integrated circuit boards fault-free at this plate,, then initiate active and standbyly to switch with state if this plate is main to use state;
First clock integrated circuit boards and second clock integrated circuit board be in both sides' heartbeat during unusual and this plate fault-free, if this plate is mainly to use state, then forbids initiating active and standbyly switching with state;
First clock integrated circuit boards and second clock integrated circuit board be when unusual and this plate has fault in both sides' heartbeat, if this plate is mainly to use state, then initiates active and standbyly to switch with state;
First clock integrated circuit boards and second clock integrated circuit board be in both sides' heartbeat during unusual and this plate fault-free, if this plate is a stand-by state, then initiates active and standbyly to switch with state.
Further, can also comprise:
First clock integrated circuit boards and second clock integrated circuit board are after initialization is accomplished, and both sides' heartbeat is when unusual, if this plate is mainly to use state, then forbid initiating active and standbyly switching with state.
First clock integrated circuit boards and second clock integrated circuit board after definite this plate fault-free, will forbid initiating active and standby switch to be revised as with state allow to initiate active and standbyly to switch with state.
Based on same inventive concept, the embodiment of the invention also provides a kind of clock integrated circuit boards and a kind of clock synchronization device, and the enforcement in the face of this clock integrated circuit boards and clock synchronizer describes down.
Fig. 2 is the clock integrated circuit boards structural representation, and is as shown in the figure, can comprise on the clock integrated circuit boards:
State information acquisition module 202 is used to obtain the clock integrated circuit boards work state information;
In the enforcement, at first handover module 204 obtains the heartbeat signal that heartbeat module 201 produces; State information acquisition module 202 is obtained the clock integrated circuit boards work state information; Through the heartbeat signal and the work state information of communication interface modules 203 tranmitting data register integrated circuit boards, receive the heartbeat signal and the work state information of outside input; The heartbeat signal of outside input and work state information generally are that other clock integrated circuit boards send.Handover module 204 is according to the heartbeat signal of clock integrated circuit boards, active and standby with state and work state information then, and the heartbeat signal of outside input and work state information determine whether to initiate active and standbyly to switch with state; Simultaneously; Mutual exclusion module 205 keeps mutual exclusion through external equipment and the active and standby of clock integrated circuit boards that two-shipper logic connecting interface send enable signal to make to link to each other with this interface mutually with state; Through this mutual exclusion function; Clock integrated circuit boards just can switch fast, and guarantees ping-pong can not occur, can cause to switch back and forth between active and standby.Simultaneously,, therefore can not occur the other side's state is judged deficiency, can't know the situation of the detailed status that the other side is present owing to obtain heartbeat signal, active and standby in real time with state and work state information.
In the practical implementation; Handover module 204 can confirm whether the heartbeat signal of input and the external equipment and the clock integrated circuit board of work state information break down according to work state information; And after confirming that according to heartbeat signal both sides' heartbeat is whether unusual, handle by following mode:
When clock integrated circuit boards fault-free and said external equipment have fault,, then initiate active and standbyly to switch with state if clock integrated circuit boards is a stand-by state;
When clock integrated circuit boards fault-free and said external equipment have fault,, then forbid initiating active and standbyly switching with state if clock integrated circuit boards is mainly to use state;
When clock integrated circuit boards has fault and said external equipment fault-free,, then forbid initiating active and standbyly switching with state if clock integrated circuit boards is stand-by state;
When clock integrated circuit boards has fault and said external equipment fault-free,, then initiate active and standbyly to switch with state if clock integrated circuit boards is main to use state;
In clock integrated circuit boards and said external equipment heartbeat during unusual and clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if clock integrated circuit boards is mainly to use state;
When unusual and clock integrated circuit boards has fault in clock integrated circuit boards and said external equipment heartbeat,, then initiate active and standbyly to switch with state if clock integrated circuit boards is mainly to use state;
In clock integrated circuit boards and said external equipment heartbeat during unusual and clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if clock integrated circuit boards is a stand-by state.
Handover module further can also be after the clock integrated circuit boards initialization be accomplished, and clock integrated circuit boards is with said external equipment heartbeat when unusual, if clock integrated circuit boards is to lead to use state, then forbids initiating active and standbyly switching with state.
Handover module further can also be used for after definite clock integrated circuit boards fault-free, will forbid initiating active and standby switch to be revised as with state allow to initiate active and standbyly to switch with state.
Fig. 3 is the clock synchronization device structural representation, and is as shown in the figure, can comprise first clock integrated circuit boards 301, second clock integrated circuit board 302 in the clock synchronization device, also comprises:
First heartbeat module 3011 links to each other with first clock integrated circuit boards 301, is used to produce heartbeat signal;
The first state information acquisition module 3012 links to each other with first clock integrated circuit boards 301, is used to obtain the clock integrated circuit boards work state information;
The second state information acquisition module 3022 links to each other with second clock integrated circuit board 302, is used to obtain the clock integrated circuit boards work state information;
First communication interface modules 3013 links to each other with first clock integrated circuit boards 301, is used to send the heartbeat signal and the work state information of first clock integrated circuit boards 301, receives the heartbeat signal and the work state information of second clock integrated circuit board 302;
Second communication interface module 3023 links to each other with second clock integrated circuit board 302, is used to send the heartbeat signal and the work state information of second clock integrated circuit board 302, receives the heartbeat signal and the work state information of first clock integrated circuit boards 301;
The first mutual exclusion module 3015 links to each other with first clock integrated circuit boards 301, is used for sending enable signal to make the second clock integrated circuit board 302 and first the active and standby of clock integrated circuit boards 301 keep mutual exclusion with state mutually through two-shipper logic connecting interface;
The second mutual exclusion module 3025 links to each other with second clock integrated circuit board 302, is used for sending enable signal to make first clock integrated circuit boards 301 keep mutual exclusion with the active and standby of second clock integrated circuit board 302 with state mutually through two-shipper logic connecting interface.
In the enforcement, two clock integrated circuit boards not only obtain heartbeat signal and clock integrated circuit boards work state information on this integrated circuit board, also obtain heartbeat signal and clock integrated circuit boards work state information on the other side's integrated circuit board simultaneously.The heartbeat signal of the other side's integrated circuit board and work state information can obtain through communication interface modules; After obtaining heartbeat signal and clock integrated circuit boards work state information, just can determine whether to initiate active and standbyly to switch with state with state in conjunction with the active and standby of this integrated circuit board; Simultaneously, the mutual exclusion module on this integrated circuit board send enable signal to guarantee to make the active and standby of two clock integrated circuit boards keep mutual exclusion with state through two-shipper logic connecting interface mutually.
First handover module can confirm whether first clock integrated circuit boards and second clock integrated circuit board break down according to work state information, and after confirming that according to heartbeat signal first clock integrated circuit boards and the heartbeat of second clock integrated circuit board be whether unusual, carries out by following mode:
When the first clock integrated circuit boards fault-free and second clock integrated circuit board have fault,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is a stand-by state;
When the first clock integrated circuit boards fault-free and second clock integrated circuit board have fault,, then forbid initiating active and standbyly switching with state if first clock integrated circuit boards is mainly to use state;
When first clock integrated circuit boards has fault and second clock integrated circuit board fault-free,, then forbid initiating active and standbyly switching with state if first clock integrated circuit boards is stand-by state;
When first clock integrated circuit boards has fault and second clock integrated circuit board fault-free,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is main to use state;
In first clock integrated circuit boards and the heartbeat of second clock integrated circuit board during unusual and clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if first clock integrated circuit boards is mainly to use state;
When unusual and clock integrated circuit boards has fault in first clock integrated circuit boards and the heartbeat of second clock integrated circuit board,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is mainly to use state;
In first clock integrated circuit boards and the heartbeat of second clock integrated circuit board during unusual and clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is a stand-by state.
Equally; Second handover module; Also can confirm according to work state information whether the second clock integrated circuit board and first clock integrated circuit boards break down, and after confirming that according to heartbeat signal second clock integrated circuit board and the first clock integrated circuit boards heartbeat be whether unusual, carry out by following mode:
When second clock integrated circuit board fault-free and first clock integrated circuit boards have fault,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is a stand-by state;
When second clock integrated circuit board fault-free and first clock integrated circuit boards have fault,, then forbid initiating active and standbyly switching with state if the second clock integrated circuit board is mainly to use state;
When the second clock integrated circuit board has the fault and the first clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if the second clock integrated circuit board is stand-by state;
When the second clock integrated circuit board has the fault and the first clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is main to use state;
In second clock integrated circuit board and the first clock integrated circuit boards heartbeat during unusual and clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if the second clock integrated circuit board is mainly to use state;
When unusual and clock integrated circuit boards has fault in second clock integrated circuit board and the first clock integrated circuit boards heartbeat,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is mainly to use state;
In second clock integrated circuit board and the first clock integrated circuit boards heartbeat during unusual and clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is a stand-by state.
Lifting an instance below comes the embodiment of such scheme is further explained.
The clock synchronization device hardware configuration sketch map of Fig. 4 for realizing that the doubleclocking integrated circuit board switches, as shown in the figure, the clock synchronization device hardware in the present embodiment can comprise processor 401, logic controller 402.Respectively each module and annexation are explained below.In the description process, be to describe, know easily that another piece clock integrated circuit boards is also by this enforcement with the object that is embodied as of a clock integrated circuit boards.Know that by top in the present embodiment, processor and logic controller will be realized the function of functional modules such as heartbeat module, state information module, communication interface modules, handover module, mutual exclusion module jointly according to characteristics separately.
One, the function of processor realization
The characteristics of processor are: can utilize CPU, software program etc. to carry out signal message and handle, have certain information processing and operational capability; It can be according to the various information Recognition that get access to, the heartbeat signal of judging, analyze clock integrated circuit boards, active and standby with state and work state information, and and then can make and whether initiate active and standby judgements such as switching with state.
Concrete, the function that processor is realized comprises: the function of heartbeat module, state information module, communication interface modules, handover module, wherein:
1, heartbeat module, the generation heartbeat signal;
2, state information acquisition module reads this integrated circuit board work state information;
3, communication interface modules, the heartbeat signal of tranmitting data register integrated circuit board and work state information receive outside heartbeat signal and the work state information of importing;
4, handover module, according to the heartbeat signal of clock integrated circuit boards, active and standby with state and work state information, and the heartbeat signal of outside input and work state information determine whether to initiate active and standbyly to switch with state.
Obviously; The performed function of functional module was through summarizing; Between each functional module, also need various cooperation could the technical solution problems, thereby and the present invention adopt and handles reason that these components and parts realize and also possessed the ability of this Comprehensive Control coordination in the function that has comprised CPU, software program control on it.Therefore, outside above-mentioned functions, it also need be carried out:
5, read and the configuration logic controller;
6, operation BSP (Board Suppout Package, plate level support package), SMSS (SystemMangement Sub-System, system management subsystem), OAMA (Operation and Maintenance layer control program).These three software programs are this area three Control Software commonly used, also can their use be described below.
Two, logic controller
Logic controller also needs certain software program serviceability, can carry out information interaction with processor like this and carry out some instructions that processor assigns cooperating processor work; Simultaneously it also need possess hardware respond fast, because it need keep mutual exclusion with state through external equipment and the active and standby of clock integrated circuit boards that two-shipper logic connecting interface send enable signal to make to link to each other with this interface mutually.In conjunction with These characteristics; The components and parts that can adopt in the enforcement can be used CPLD (Complex Programmable Logic Device; CPLD) or FPGA programmable logic controller (PLC) (Field Programmable Gate Array; Realize that field programmable gate array) function of this module is:
The mutual exclusion module is used for keeping mutual exclusion through another clock integrated circuit boards and the active and standby of clock integrated circuit boards that two-shipper logic connecting interface send enable signal to make to link to each other with this interface mutually with state; Specifically can be subdivided into:
Possess two-shipper cross complaint semiotic function, keep the active and standby mutual exclusion state of using, the two machine communication interface that is connected with processor is arranged simultaneously,, can carry out two-shipper and switch the operation that allows or forbid through the configuration of processor with the other side's clock integrated circuit boards; The two-shipper control module is accomplished following function:
Eliminate the two-shipper master and use phenomenon;
Active and standby vibration is eliminated in the state locking;
The switching command lock-in circuit can only be initiated to switch by mainboard;
Reset switching, manually switch, software switches, main board failure is switched realization;
Plate being forced this plate when not on the throne is main using.
Consider the characteristics that it is possessed on hardware, can also realize on logic controller that function is: detect this plate clock status, comprise the clock of this plate output and the crystal oscillator clock of this plate self; And with the part of this clock information as work state information.So obviously, the state information acquisition module also can get access to this partial information.That is, logic controller is not only wanted the control of receiving processor, also needs to receive the management of cross complaint signal, and can report the current various clock information states of processor.
During practical implementation, can implement by following holding wire:
ACT_T: the active and standby state of using of this plate, to export to side plate, low level is effective.
ACT_R: to the active and standby state of using of side plate, by side plate is imported, low level is effective.
HRST_T: this sheet reset is to the signal of side plate, and low level is effective.
HRST_R: the signal of this plate of offside sheet reset, low level is effective.
LINK: the LINK state indication of this plate UPDATE FE, low level is effective.
The act state indication of ACT:UPDATE FE, low level is effective.
Just comprised two clock integrated circuit boards in the present embodiment, on each clock integrated circuit boards, respectively comprised processor and logic controller, below just the embodiment of the annexation of these four components and parts is described.
Have 3 kinds of interfaces between them, explain as follows:
Direct communication interface between interface 1, two clock integrated circuit boards is sent the information state of two boards card mutually through this port;
Direct two-shipper logic connecting interface between interface 2, two clock integrated circuit boards send the two-shipper enable signal mutually, and enable signal is exactly a two-shipper cross complaint signal;
Interface between interface 3, processor and the logic controller, effect are to read and the configuration logic controller through processor, and logic controller is also given processor through this interface with current various clock information state reporting.
After clock synchronization device hardware configuration relation is described, describe in the face of its concrete working method down.
For the ease of explanation, have among the embodiment:
Main board: clock integrated circuit boards is operated in the main state of using;
Standby plate: clock integrated circuit boards is operated in stand-by state;
DRIVER: the driving of logical circuit and floor processor control;
SMSS: system management layer control program;
OAMS: Operation and Maintenance layer control program.
Then, can implement as follows:
1; After the clock board clamp started completion, the DRIVER subsystem of active clock integrated circuit board plate was provided with initial condition acquiescence switching mark position for forbidding two-shipper circuit in the operation logic control circuit; Make that hardware does not allow to switch, soon the active clock integrated circuit board is made as and forbids switching state;
2, initialization is accomplished, if the SMSS of active clock integrated circuit board detect with the heartbeat of standby clock integrated circuit board unusual after, continue to keep active clock integrated circuit board DRIVER subsystem switching mark position for forbidding;
3, when the SMSS of standby clock integrated circuit board detect with the heartbeat of active clock integrated circuit board normal after, inquiry DRIVER subsystem clock state; According to the result who inquires; To the state of active clock integrated circuit board report standby clock integrated circuit board clock, the active clock integrated circuit board is provided with active clock integrated circuit board DRIVER subsystem switching mark position according to the state of standby clock integrated circuit board report; If the clock status of standby clock integrated circuit board is normal; Then the switching mark position is set to allow to switch, if the clock status of standby clock integrated circuit board is unusual, then switching mark is set to forbid switch;
4, if the active clock integrated circuit board has detected clock failure, logic controller directly carries out the two-shipper switching controls, notifies the DRIVER clock failure simultaneously, and then DRIVER is to the fault warning of SMSS subsystem tranmitting data register;
5, when the hardware detection of active clock integrated circuit board after clock failure is arranged, inspection switching mark position; If forbid switching, then do not switch, switch if allow; Then switch clock integrated circuit boards, after switching is accomplished, send this plate activestandby state by hardware trigger DRIVER to SMSS and change indication; After SMSS received this indication, former active clock integrated circuit board resetted; After former standby clock integrated circuit board was upgraded to active clock integrated circuit board plate, the DRIVER subsystem changed indication to this plate of SMSS activestandby state, after the SMSS subsystem is received this indication, carried out the process that standby plate is upgraded to main board.
6; If the hardware detection of active clock integrated circuit board becomes to clock from fault normally; Then hardware becomes normal notice to the DRIVER tranmitting data register from fault; Then DRIVER, alarms to the fault clearance of OAMS subsystem tranmitting data register after SMSS receives this alarm to SMSS subsystem tranmitting data register fault clearance alarm.
7, if the hardware detection of standby clock integrated circuit board arrives the clock fault, then hardware is notified clock failure to DRIVER; After DRIVER receives clock failure; To the fault warning of SMSS subsystem tranmitting data register, after SMSS receives this alarm, to the fault warning of OAMS subsystem tranmitting data register.Simultaneously; SMSS is when receiving the clock failure alarm; Also need send standby clock integrated circuit board clock status report message to the SMSS of active clock integrated circuit board, SMSS is according to the clock status of standby clock integrated circuit board, and the switching mark that active clock integrated circuit board DRIVER subsystem is set is for forbidding;
8; If the hardware detection of standby clock integrated circuit board becomes to clock from fault normally; Hardware becomes normal notice to the DRIVER tranmitting data register from fault; Then DRIVER, alarms to the fault clearance of OAMS subsystem tranmitting data register after SMSS receives this alarm to SMSS subsystem tranmitting data register fault clearance alarm.Simultaneously; SMSS is when receiving the clock failure cleared alarm; It also will inquire about the state of other clock of this plate, according to the result of inquiry, sends standby clock integrated circuit board clock status report message to the SMSS of active clock integrated circuit board; SMSS is according to the clock status of standby plate, and the switching mark that active clock integrated circuit board plate DRIVER subsystem is set is for forbidding or changeable.
For the clearer clock synchronization device of describing carries out each implementing procedure that the doubleclocking integrated circuit board switches, be divided into several sections below and describe, be divided into: 1, detect the processing of heartbeat signal when unusual; Processing when 2, detecting clock failure.
Fig. 5 detects the processing implementing procedure sketch map of heartbeat signal when unusual, and is as shown in the figure, can comprise the steps:
The SMSS of step 501, standby clock integrated circuit board detects with the heartbeat of active clock integrated circuit board unusual;
The SMSS of step 502, active clock integrated circuit board detects with the heartbeat of standby clock integrated circuit board unusual;
The SMSS of step 503, standby clock integrated circuit board inquires about clock status to DRIVER;
The SMSS of step 504, active clock integrated circuit board is provided with clock integrated circuit boards at DRIVER to be forbidden switching;
The DRIVER of step 505, standby clock integrated circuit board is to SMSS report clock status result;
The SMSS of step 506, standby clock integrated circuit board is to active clock integrated circuit board report standby clock integrated circuit board clock status result;
The SMSS of step 507, active clock integrated circuit board reports the result according to clock status and at DRIVER the clock integrated circuit boards switching mark is set.
Fig. 6 is the processing implementing procedure sketch map when detecting the active clock fault; Be easy-to-read; Abbreviate the standby clock integrated circuit board as standby plate, abbreviate the active clock integrated circuit board as main board, present embodiment has been described the handling process when clock failure appears in this plate of main board discovery; Then as shown in the figure, can comprise the steps:
Step 601, main board DRIVER detect clock failure;
Step 602, main board DRIVER are to the fault warning of standby plate OAMS tranmitting data register;
Step 603, main board are set to allow to switch;
Step 604, standby plate DRIVER send active and standby the switching with state to standby plate SMSS and indicate;
Step 605, standby plate SMSS carry out standby plate and are upgraded to the main board state;
Step 606, main board switch to the standby plate state;
Step 607, main board DRIVER send active and standby the switching with state of this plate to SMSS and indicate;
Step 608, main board SMSS call the driving reset clock integrated circuit boards;
Step 609, that main board DRIVER detects clock is normal;
Step 610, main board DRIVER alarm to the fault clearance of standby plate OAMS tranmitting data register.
Fig. 7 is the processing implementing procedure sketch map when detecting the standby clock fault; Be easy-to-read; Abbreviate the standby clock integrated circuit board as standby plate, abbreviate the active clock integrated circuit board as main board, present embodiment has been described the handling process when clock failure appears in this plate of standby plate discovery; Then as shown in the figure, can comprise the steps:
Step 701, standby plate DRIVER send to SMSS and detect the clock failure alarm;
Step 702, standby plate DRIVER are to the fault warning of standby plate OAMS tranmitting data register;
Step 703, standby plate SMSS are to main board SMSS tranmitting data register status report;
Step 704, main board SMSS are provided with the clock integrated circuit boards switching mark to DRIVER;
Step 705, standby plate DRIVER alarm to the fault clearance of SMSS tranmitting data register;
Step 706, standby plate SMSS report the clock failure cleared alarm to OAMS;
Step 707, standby plate SMSS inquire about clock status to DRIVER;
Step 708, standby plate DRIVER are to SMSS feedback clock state outcome;
Step 709, standby plate SMSS are to main board SMSS tranmitting data register status report;
Step 710, main board SMSS are provided with the clock switching mark at DRIVER.
Visible by above-mentioned enforcement, the embodiment of the invention can guarantee that clock system can reliablely and stablely work, and can be applied in the various occasions that need the two-shipper cross complaint, can tackle various failure conditions; The design of employing combination hardware-software, stability is strong, and switch speed is fast, and does not influence output clock index.The embodiment of the invention needing in the digital communicating field can be widely used in the clock synchronization device of two-shipper cross complaint, can improve the stability and the accuracy of professional transmission efficiently.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1. the changing method of a clock integrated circuit boards is characterized in that, comprises the steps:
First clock integrated circuit boards and second clock integrated circuit board send heartbeat signal timely mitriform attitude through the communication interface between the integrated circuit board mutually;
First clock integrated circuit boards and second clock integrated circuit board according to both sides' heartbeat signal, active and standbyly determine whether to initiate active and standbyly to switch with state with the timely mitriform attitude of state, and send enable signal to make first clock integrated circuit boards mutually and the second clock integrated circuit board is active and standby keeps mutual exclusion with state through the two-shipper logic connecting interface between first clock integrated circuit boards and the second clock integrated circuit board;
Wherein, first clock integrated circuit boards and second clock integrated circuit board according to both sides' heartbeat signal, active and standbyly determine whether to initiate active and standby the switching with the timely mitriform attitude of state and be specially with state:
First clock integrated circuit boards and second clock integrated circuit board confirm according to clock status whether the other side's clock integrated circuit boards and this plate break down, and after confirming that according to heartbeat signal both sides' heartbeat is whether unusual,
First clock integrated circuit boards and second clock integrated circuit board if this plate is a stand-by state, then initiate active and standbyly to switch with state when this plate fault-free and the other side's clock integrated circuit boards have fault;
First clock integrated circuit boards and second clock integrated circuit board are when this plate fault-free and the other side's clock integrated circuit boards have fault, if this plate is mainly to use state, then forbid initiating active and standbyly switching with state;
When first clock integrated circuit boards and second clock integrated circuit board have fault and the other side's clock integrated circuit boards fault-free at this plate,, then forbid initiating active and standbyly switching with state if this plate is stand-by state;
When first clock integrated circuit boards and second clock integrated circuit board have fault and the other side's clock integrated circuit boards fault-free at this plate,, then initiate active and standbyly to switch with state if this plate is main to use state;
First clock integrated circuit boards and second clock integrated circuit board be in both sides' heartbeat during unusual and this plate fault-free, if this plate is mainly to use state, then forbids initiating active and standbyly switching with state;
First clock integrated circuit boards and second clock integrated circuit board be when unusual and this plate has fault in both sides' heartbeat, if this plate is mainly to use state, then initiates active and standbyly to switch with state;
First clock integrated circuit boards and second clock integrated circuit board be in both sides' heartbeat during unusual and this plate fault-free, if this plate is a stand-by state, then initiates active and standbyly to switch with state.
2. the method for claim 1 is characterized in that, further comprises:
First clock integrated circuit boards and second clock integrated circuit board are after initialization is accomplished, and both sides' heartbeat is when unusual, if this plate is mainly to use state, then forbid initiating active and standbyly switching with state.
3. the method for claim 1 is characterized in that, further comprises:
First clock integrated circuit boards and second clock integrated circuit board after definite this plate fault-free, will forbid initiating active and standby switch to be revised as with state allow to initiate active and standbyly to switch with state.
4. a clock integrated circuit boards is characterized in that, comprising:
Heartbeat module is used to produce heartbeat signal;
The state information acquisition module is used to obtain the clock integrated circuit boards clock status;
Communication interface modules is used for the heartbeat signal and the clock status of tranmitting data register integrated circuit board, receives the heartbeat signal and the clock status of outside input;
Handover module is used for confirming according to clock status whether the heartbeat signal of input and the external equipment and the clock integrated circuit board of clock status break down, and according to heartbeat signal confirm both sides' heartbeat whether unusually after,
When clock integrated circuit boards fault-free and said external equipment have fault,, then initiate active and standbyly to switch with state if clock integrated circuit boards is a stand-by state;
When clock integrated circuit boards fault-free and said external equipment have fault,, then forbid initiating active and standbyly switching with state if clock integrated circuit boards is mainly to use state;
When clock integrated circuit boards has fault and said external equipment fault-free,, then forbid initiating active and standbyly switching with state if clock integrated circuit boards is stand-by state;
When clock integrated circuit boards has fault and said external equipment fault-free,, then initiate active and standbyly to switch with state if clock integrated circuit boards is main to use state;
In clock integrated circuit boards and said external equipment heartbeat during unusual and clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if clock integrated circuit boards is mainly to use state;
When unusual and clock integrated circuit boards has fault in clock integrated circuit boards and said external equipment heartbeat,, then initiate active and standbyly to switch with state if clock integrated circuit boards is mainly to use state;
In clock integrated circuit boards and said external equipment heartbeat during unusual and clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if clock integrated circuit boards is a stand-by state;
The mutual exclusion module is used for keeping mutual exclusion through external equipment and the active and standby of clock integrated circuit boards that two-shipper logic connecting interface send enable signal to make to link to each other with this interface mutually with state.
5. clock integrated circuit boards as claimed in claim 4; It is characterized in that said handover module is further used for after the clock integrated circuit boards initialization is accomplished, and clock integrated circuit boards and said external equipment heartbeat are when unusual; If clock integrated circuit boards is main to use state, then forbid initiating active and standbyly switching with state.
6. clock integrated circuit boards as claimed in claim 4 is characterized in that, said handover module is further used for after definite clock integrated circuit boards fault-free, will forbid initiating active and standby switch to be revised as with state allow to initiate active and standbyly to switch with state.
7. a clock synchronization device comprises first clock integrated circuit boards, second clock integrated circuit board, it is characterized in that, also comprises:
First heartbeat module links to each other with first clock integrated circuit boards, is used to produce heartbeat signal;
Second heartbeat module links to each other with the second clock integrated circuit board, is used to produce heartbeat signal;
The first state information acquisition module links to each other with first clock integrated circuit boards, is used to obtain the clock integrated circuit boards clock status;
The second state information acquisition module links to each other with the second clock integrated circuit board, is used to obtain the clock integrated circuit boards clock status;
First communication interface modules links to each other with first clock integrated circuit boards, is used to send the heartbeat signal and the clock status of first clock integrated circuit boards, receives the heartbeat signal and the clock status of second clock integrated circuit board;
The second communication interface module links to each other with the second clock integrated circuit board, is used to send the heartbeat signal and the clock status of second clock integrated circuit board, receives the heartbeat signal and the clock status of first clock integrated circuit boards;
First handover module links to each other with first clock integrated circuit boards, is used for confirming according to clock status whether first clock integrated circuit boards and second clock integrated circuit board break down, and after confirming that according to heartbeat signal first clock integrated circuit boards and the heartbeat of second clock integrated circuit board are whether unusual,
When the first clock integrated circuit boards fault-free and second clock integrated circuit board have fault,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is a stand-by state;
When the first clock integrated circuit boards fault-free and second clock integrated circuit board have fault,, then forbid initiating active and standbyly switching with state if first clock integrated circuit boards is mainly to use state;
When first clock integrated circuit boards has fault and second clock integrated circuit board fault-free,, then forbid initiating active and standbyly switching with state if first clock integrated circuit boards is stand-by state;
When first clock integrated circuit boards has fault and second clock integrated circuit board fault-free,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is main to use state;
In first clock integrated circuit boards and the heartbeat of second clock integrated circuit board during unusual and clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if first clock integrated circuit boards is mainly to use state;
When unusual and clock integrated circuit boards has fault in first clock integrated circuit boards and the heartbeat of second clock integrated circuit board,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is mainly to use state;
In first clock integrated circuit boards and the heartbeat of second clock integrated circuit board during unusual and clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if first clock integrated circuit boards is a stand-by state;
Second handover module links to each other with the second clock integrated circuit board, is used for confirming according to clock status whether the second clock integrated circuit board and first clock integrated circuit boards break down, and after confirming that according to heartbeat signal second clock integrated circuit board and the first clock integrated circuit boards heartbeat are whether unusual,
When second clock integrated circuit board fault-free and first clock integrated circuit boards have fault,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is a stand-by state;
When second clock integrated circuit board fault-free and first clock integrated circuit boards have fault,, then forbid initiating active and standbyly switching with state if the second clock integrated circuit board is mainly to use state;
When the second clock integrated circuit board has the fault and the first clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if the second clock integrated circuit board is stand-by state;
When the second clock integrated circuit board has the fault and the first clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is main to use state;
In second clock integrated circuit board and the first clock integrated circuit boards heartbeat during unusual and clock integrated circuit boards fault-free,, then forbid initiating active and standbyly switching with state if the second clock integrated circuit board is mainly to use state;
When unusual and clock integrated circuit boards has fault in second clock integrated circuit board and the first clock integrated circuit boards heartbeat,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is mainly to use state;
In second clock integrated circuit board and the first clock integrated circuit boards heartbeat during unusual and clock integrated circuit boards fault-free,, then initiate active and standbyly to switch with state if the second clock integrated circuit board is a stand-by state;
The first mutual exclusion module links to each other with first clock integrated circuit boards, is used for sending enable signal to make second clock integrated circuit board and the active and standby of first clock integrated circuit boards keep mutual exclusion with state mutually through two-shipper logic connecting interface;
The second mutual exclusion module links to each other with the second clock integrated circuit board, is used for sending enable signal to make first clock integrated circuit boards and the active and standby of second clock integrated circuit board keep mutual exclusion with state mutually through two-shipper logic connecting interface.
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| CN2008101193754A CN101667905B (en) | 2008-09-04 | 2008-09-04 | Method and device for switching clock integrated circuit boards |
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| CN2008101193754A CN101667905B (en) | 2008-09-04 | 2008-09-04 | Method and device for switching clock integrated circuit boards |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102073562B (en) * | 2010-12-31 | 2014-08-20 | 山石网科通信技术有限公司 | Hardware-based main/standby switch arbitration method |
| CN104506364A (en) * | 2014-12-29 | 2015-04-08 | 迈普通信技术股份有限公司 | Master-slave switching method, main control card and network equipment |
| CN106648995B (en) * | 2016-11-29 | 2019-11-19 | 浙江大华技术股份有限公司 | The first host, hot backup system and method in a kind of hot backup system |
| CN106789246A (en) * | 2016-12-22 | 2017-05-31 | 广西防城港核电有限公司 | The changing method and device of a kind of active/standby server |
| CN106648997A (en) * | 2016-12-23 | 2017-05-10 | 北京航天测控技术有限公司 | Master-salve switching method based on non-real-time operating system |
| CN107992023A (en) * | 2017-11-29 | 2018-05-04 | 中核控制系统工程有限公司 | A kind of high precision analog exports self diagnosis redundancy switching circuit |
| CN109298981A (en) * | 2018-09-27 | 2019-02-01 | 郑州云海信息技术有限公司 | Method of data synchronization, system between a kind of PCIE dual redundant chip |
| CN110597672A (en) * | 2019-09-18 | 2019-12-20 | 恒为科技（上海）股份有限公司 | Method and device for main/standby switching of ATCA switching system |
| CN117555278B (en) * | 2024-01-11 | 2024-03-26 | 国网经济技术研究院有限公司 | Control chip system for zero data loss in flexible direct valve control system and application method thereof |
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