CN109298981A - Method of data synchronization, system between a kind of PCIE dual redundant chip - Google Patents
Method of data synchronization, system between a kind of PCIE dual redundant chip Download PDFInfo
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- CN109298981A CN109298981A CN201811135587.1A CN201811135587A CN109298981A CN 109298981 A CN109298981 A CN 109298981A CN 201811135587 A CN201811135587 A CN 201811135587A CN 109298981 A CN109298981 A CN 109298981A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Abstract
Method of data synchronization between a kind of PCIE dual redundant chip provided herein, comprising: the first chip judges whether the second chip is in place；If so, sending heartbeat to second chip；After second chip is received to the response packet of the heartbeat, data to be synchronized are sent in the form of synchronous transfer to second chip.By first judging the state in place between dual redundant chip, and then the unobstructed synchronization that data to be synchronized are carried out by the way of synchronous transfer is connected in the first chip and the second chip, guarantee that the second chip can be fed back accordingly after the data for receiving the first chip, and then it is synchronous to realize the data between dual redundant chip.The application also provides data synchronous system, a kind of calculating readable storage medium storing program for executing and a kind of storage terminal between a kind of PCIE dual redundant chip, has above-mentioned beneficial effect.
Description
Technical field
This application involves storage apparatus fields, in particular to method of data synchronization between a kind of PCIE dual redundant chip,
System, a kind of calculating readable storage medium storing program for executing and a kind of storage terminal.
Background technique
In storage software, a crucial problem is to guarantee reliability, the integrality of data, and reliability needs software
With the reliability of hardware, but in actual motion physical environment, physical hardware is always uncertain to there is various asks
Topic, in order to guarantee that data are reliable, by the timely monitoring hardware problem of software, if hardware anomalies are made accordingly according to hardware anomalies
Processing, prevent hardware anomalies from leading to loss of data, for the reliability of hardware, be commonly designed dual redundant physical equipment.If
One physical equipment is out of joint, another physical equipment can still guarantee service operation, but double physical links can be frequent
Resource the problem of cannot reading simultaneously occurs, therefore resource needs to share simultaneously, once during resource-sharing one of them
It will be so that source synchronous process interrupt, hereafter can only re-start the synchronization of whole part resource, greatly when physical equipment breaks down
Resource is wasted greatly.Therefore how to realize that the data synchronization efficiency between dual redundant physical equipment is that those skilled in the art need
The technical issues of solution.
Summary of the invention
The purpose of the application is to provide a kind of method of data synchronization between PCIE dual redundant chip, system, a kind of calculating
Readable storage medium storing program for executing and a kind of storage terminal, solve that the data synchronization dependability between existing dual redundant physical equipment is low to ask
Topic.
In order to solve the above technical problems, the application provides the method for data synchronization between a kind of PCIE dual redundant chip, tool
Body technique scheme is as follows:
First chip judges whether the second chip is in place；
If so, sending heartbeat to second chip；
After second chip is received to the response packet of the heartbeat, sent out in the form of synchronous transfer to second chip
Send data to be synchronized.
Wherein, the first chip judge the second chip whether include: in place
First chip sends conn timestamp twice to second chip；
According to the conn timestamp twice, whether time-out does not reply judge whether second chip is in place.
Wherein, first chip and second chip are main control chip.
Wherein, data to be synchronized are sent in the form of synchronous transfer to second chip includes:
Synchronous mark is set；
It is synchronized according to the synchronous mark according to element Resource Properties to be synchronized in the database of first chip
Data.
Wherein, before sending data to be synchronized in the form of synchronous transfer to second chip, further includes:
Storage allocation is requested to memory pool.
Wherein, if first chip and the second chip connection failure, first chip receives described second
The data_bad that chip returns.
The application also provides the data synchronous system between a kind of PCIE dual redundant chip, comprising:
Judgment module, for judging whether the second chip is in place；
Sending module sends heartbeat to second chip if be judged as YES for the judgment module；
Synchronization module, after receiving second chip to the response packet of the heartbeat, to second chip with same
The form of step transmission sends data to be synchronized.
Wherein, the judgment module includes:
Transmission unit sends conn timestamp twice to second chip for first chip；
Judging unit, for whether overtime do not reply to judge that second chip is according to the conn timestamp twice
It is no in place.
The application also provides a kind of computer readable storage medium, is stored thereon with computer program, the computer journey
The step of method as described above is realized when sequence is executed by processor.
The application also provides a kind of storage terminal, including memory and processor, has computer journey in the memory
The step of sequence, the processor realizes method as described above when calling the computer program in the memory.
Method of data synchronization between a kind of PCIE dual redundant chip provided herein, comprising: the first chip judgement
Whether the second chip is in place；If so, sending heartbeat to second chip；Second chip is received to return the heartbeat
After should wrapping, data to be synchronized are sent in the form of synchronous transfer to second chip.
The application passes through the state in place first judged between dual redundant chip, and then connects in the first chip and the second chip
The unobstructed synchronization that data to be synchronized are carried out by the way of synchronous transfer guarantees the second chip in the data for receiving the first chip
After can feed back accordingly, and then it is synchronous to realize the data between dual redundant chip.Even if a certain equipment is same in data
It breaks down during step, it is subsequent because synchronous transfer makes data that can return to related prompt message after being transmitted to opposite equip.
Without repeating the synchronous content transmitted when synchronous, the synchronous efficiency of data is improved.It is bis- superfluous that the application also provides a kind of PCIE
Data synchronous system, a kind of calculating readable storage medium storing program for executing and a kind of storage terminal between remaining chip have above-mentioned beneficial effect,
Details are not described herein again.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
The process of method of data synchronization of the Fig. 1 between a kind of PCIE dual redundant chip provided by the embodiment of the present application
Figure；
Data synchronous system structural representation of the Fig. 2 between a kind of PCIE dual redundant chip provided by the embodiment of the present application
Figure.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is
Some embodiments of the present application, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall in the protection scope of this application.
Referring to FIG. 1, data synchronize side of the Fig. 1 between a kind of PCIE dual redundant chip provided by the embodiment of the present application
The flow chart of method, the method for data synchronization include:
S101: the first chip judges whether the second chip is in place；If so, into S102；
It should be noted that the first chip and the second chip here includes but is not limited to that (PCIE is total by PCIESWITCHTEC
Line interconnecting and switching chip).Especially, it should be noted that the first chip and the second chip are preferably master control core in the application
Piece.Present redundance unit is usually single control storage, i.e., only one includes controller (or in controlling in two storage equipment
The heart), but caused immediate problem is generally difficult to from master from control equipment namely with redundance unit once main control device breaks down
It is synchronous to control equipment progress data, in other words, the synchronous data for obtaining main control device and obtaining.But in the application, it is preferred that two cores
Piece is main control chip, once one of them breaks down in this way, another chip, can be quick due to being similarly main control chip
Instead of original main control chip so that two chips that upper layer device perceives be it is duplicate, not by failure of chip shadow
It rings.
This step generally refers to the first chip and judges whether the second chip is in place, i.e., whether the two keeps being connected to.Here,
For how to judge whether the second chip is not construed as limiting in place, it is preferred that a kind of judgment method is provided below:
First chip sends conn timestamp twice to second chip；It is according to the conn timestamp twice
No equal time-out does not reply judge whether second chip is in place.
First chip sends conn1 timestamp and conn2 timestamp to the second chip.If do not received within the set time
It replys, i.e., two overtime, then it is assumed that opposite equip. is not in place, is in off-line state (offline).If the first chip is usually
As redundance unit, then the first chip is changed to main control device at this time.
If the second chip is replied, conn timestamp is updated, and it is in place to represent the second chip, into S102；
S102: heartbeat is sent to second chip；
It should be noted that heartbeat just can be transmitted only when the second chip is in place, heartbeat is not sent out in place.And heartbeat
Transmission is asynchronous transmission, it can continues to send heartbeat when confiscating and replying.
S103: after receiving second chip to the response packet of the heartbeat, to second chip with synchronous transfer
Form sends data to be synchronized.
It should be noted that the response packet in this step is the second core after the first chip sends request packet (i.e. heartbeat)
The response that piece is made.It is synchronous that data then can have been carried out at this time.Specifically, data synchronization process can be as follows；
Synchronous mark is set；The number of first chip is synchronized according to element Resource Properties according to the synchronous mark
According to the data to be synchronized in library.
It should be noted that the synchronizing process of data is synchronous transmission, i.e., when the first chip sends data to the second chip,
It must could continue to send data after the reply of the second chip, utmostly guarantee data during transmission not in this way
Because failure and other reasons are impaired, the data synchronism between the first chip and the second chip is influenced.
Further, it is preferred that before carrying out data and synchronizing, it is also necessary to which memory pool is requested storage allocation.
It is not construed as limiting herein for how memory distributes, it is to be understood that request the memory of distribution should be according to same
The data volume of step data makees corresponding distribution, and specific allocation criterion, that is, method is not limited thereto.Application is double superfluous by first judgement
State in place between remaining chip, so the first chip and the second chip connect it is unobstructed carried out by the way of synchronous transfer to
The synchronization of synchrodata guarantees that the second chip can be fed back accordingly after the data for receiving the first chip, and then realizes
Data between dual redundant chip are synchronous.Even if a certain equipment breaks down in data synchronization process, because of synchronous transfer
So that data can return to related prompt message after being transmitted to opposite equip., without repeating in synchronous transmitted when subsequent synchronisation
Hold, improves the synchronous efficiency of data.
Based on the above embodiment, as preferred embodiment, if first chip and the second chip connection failure,
Then first chip receives the data_bad that second chip returns.
The present embodiment is intended to illustrate the receiving end of data i.e. the second chip when the first chip and the second chip connection failure
Data_bad can be returned to the first chip.It is, of course, understood that data_bad is only used as the mark of a failure of data synchronization
Will, data sync break or failure when can also have other data return, such as verification crc32, return data_crc_bad,
The number such as Data_bad:ret=bad_error, Data_crc_bad:ret=bad_crc, Data_sync:ret=success
According to being not specifically limited herein.
Furthermore, so it is easy to understand that when the second chip occurs abnormal, the first chip is by step S101 or in data
When failing in synchronizing process, the relevant information of the second chip exception can also be uploaded to upper layer software (applications), to remind user or pipe
Reason person in time overhauls the second chip, guarantees the redundancy of equipment.
The data synchronous system between a kind of PCIE dual redundant chip provided by the embodiments of the present application is introduced below,
Data synchronous system described below can correspond to each other reference with above-described method of data synchronization.
Referring to fig. 2, data synchronous system of the Fig. 2 between a kind of PCIE dual redundant chip provided by the embodiment of the present application
Structural schematic diagram.
The application also provides the data synchronous system between a kind of PCIE dual redundant chip, comprising:
Judgment module 100, for judging whether the second chip is in place；
Sending module 200 sends heartbeat to second chip if be judged as YES for the judgment module；
Synchronization module 300, after receiving second chip to the response packet of the heartbeat, to second chip with
The form of synchronous transfer sends data to be synchronized.
Based on the above embodiment, as preferred embodiment, the judgment module 100 may include:
Transmission unit sends conn timestamp twice to second chip for first chip；
Judging unit, for whether overtime do not reply to judge that second chip is according to the conn timestamp twice
It is no in place.
Based on the above embodiment, as preferred embodiment, the synchronization module 300 may include:
Setting unit, for synchronous mark to be arranged；
Synchronization unit, for synchronizing the number of first chip according to element Resource Properties according to the synchronous mark
According to the data to be synchronized in library.
Based on the above embodiment, as preferred embodiment, can also include:
Request module, for requesting storage allocation to memory pool.
Present invention also provides a kind of computer readable storage mediums, have computer program thereon, the computer program
It is performed the step of method of data synchronization between a kind of PCIE dual redundant chip provided by above-described embodiment may be implemented.
The storage medium may include: USB flash disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory
The various media that can store program code such as device (Random Access Memory, RAM), magnetic or disk.
Present invention also provides a kind of storage terminals, may include memory and processor, have meter in the memory
Calculation machine program may be implemented provided by above-described embodiment when the processor calls the computer program in the memory
A kind of the step of method of data synchronization between PCIE dual redundant chip.Certain storage terminal can also include various networks
Interface, the components such as power supply.
Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For embodiment provide system and
Speech, since it is corresponding with the method that embodiment provides, so being described relatively simple, related place is referring to method part illustration
?.
Specific examples are used herein to illustrate the principle and implementation manner of the present application, and above embodiments are said
It is bright to be merely used to help understand the present processes and its core concept.It should be pointed out that for the ordinary skill of the art
For personnel, under the premise of not departing from the application principle, can also to the application, some improvement and modification can also be carried out, these improvement
It is also fallen into the protection scope of the claim of this application with modification.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
Claims (10)
1. the method for data synchronization between a kind of PCIE dual redundant chip characterized by comprising
First chip judges whether the second chip is in place；
If so, sending heartbeat to second chip；
After second chip is received to the response packet of the heartbeat, to second chip sent in the form of synchronous transfer to
Synchrodata.
2. method of data synchronization according to claim 1, which is characterized in that the first chip judges whether the second chip is in place
Include:
First chip sends conn timestamp twice to second chip；
According to the conn timestamp twice, whether time-out does not reply judge whether second chip is in place.
3. method of data synchronization according to claim 1, which is characterized in that first chip and second chip are equal
For main control chip.
4. method of data synchronization according to claim 1, which is characterized in that second chip with the shape of synchronous transfer
Formula sends data to be synchronized
Synchronous mark is set；
The number to be synchronized in the database of first chip is synchronized according to element Resource Properties according to the synchronous mark
According to.
5. method of data synchronization according to claim 4, which is characterized in that second chip with the shape of synchronous transfer
Before formula sends data to be synchronized, further includes:
Storage allocation is requested to memory pool.
6. method of data synchronization according to claim 1, which is characterized in that if first chip and second chip
Connection failure, then first chip receives the data_bad that second chip returns.
7. the data synchronous system between a kind of PCIE dual redundant chip characterized by comprising
Judgment module, for judging whether the second chip is in place；
Sending module sends heartbeat to second chip if be judged as YES for the judgment module；
Synchronization module is passed after receiving second chip to the response packet of the heartbeat to second chip with synchronous
Defeated form sends data to be synchronized.
8. data synchronous system according to claim 1, which is characterized in that the judgment module includes:
Transmission unit sends conn timestamp twice to second chip for first chip；
Judging unit, for according to the conn timestamp twice whether time-out do not reply judge second chip whether
Position.
9. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the computer program quilt
The step of processor realizes as the method according to claim 1 to 6 when executing.
10. a kind of storage terminal, which is characterized in that including memory and processor, there is computer program in the memory,
The processor realizes the step of as the method according to claim 1 to 6 when calling the computer program in the memory
Suddenly.
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| CN111813707A (en) * | 2020-07-17 | 2020-10-23 | 济南浪潮数据技术有限公司 | Data synchronization method, device, equipment and storage medium |
| CN113868086A (en) * | 2021-09-28 | 2021-12-31 | 东风电子科技股份有限公司 | Method, device, processor and computer readable storage medium for monitoring and recovering dual-chip communication state |
| CN117555278A (en) * | 2024-01-11 | 2024-02-13 | 国网经济技术研究院有限公司 | Control chip system for zero data loss in flexible direct valve control system and application method thereof |
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