KR19990020337A - Transfer data bus redundancy method in exchange - Google Patents

Abstract

The present invention utilizes the advantage of redundancy in the case of a failure of the transfer data bus that is responsible for communication between the device and the processor, and takes advantage of the redundancy, so that if the failure occurs only on one side of the duplicated processor, the present service and the ongoing service may be appropriately responded to. It provides a method of stabilizing by improving the reliability of the call service by enabling continuous execution.

Description

Transfer data bus redundancy method in exchange

The present invention relates to a transfer data bus (TD-BUS) duplication method in an electronic exchange.

The processor controlling the device for each functional block is redundant. Since the processor is redundant when a failure occurs, it is very important in view of the exchange system that the service is performed without interruption of the service in progress or in progress. In addition, the conventional redundancy is caused by the failure of one side of the redundant processor. In this case, the frequency of occurrence of the redundancy on the transfer data bus was high due to many other reasons. It is reasonable to assume that the implementation has not been achieved in the existing redundancy, and that the failure of the cable connected to the conventional device occurs when the operator recognizes the failure and takes action. The service is interrupted, and if the operator of the device is not aware of it, the recovery is not possible.However, in the event of a failure of the conventional transfer data bus, it is impossible to take appropriate measures, and thus the state of various devices may be abnormal. There was a problem that the service was interrupted during the transition and operation, and the system itself was not fully repaired for possible TD bus disconnection and failure in operation of the exchange, but the system itself was in place when the phenomenon occurred. Maintaining the service in progress and the service in progress using minimum resources if possible from the service point of view is very difficult in the existing system, and the operator outputs a fault message when the TD bus connected to the device fails. In this respect, the failure due to the failure of the transfer data bus was not achieved.

Accordingly, an object of the present invention is to provide a service in which duplication occurs in the case of a failure of a transfer data bus that is responsible for communication between a device and a processor. It is to provide a method of stabilizing by improving the reliability of the call service to enable continuous execution of the continued service.

1 is a system diagram used in an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A detailed description of a preferred embodiment of the present invention will now be described with reference to the accompanying drawings. In the following, reference numerals are given to components of each drawing, even though the same components are shown in different drawings. Note that they have the same sign. In describing the present invention, when it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or a chip designer, and the definitions should be made based on the contents throughout the present specification.

1 is a view showing the structure of an exchange system referred to in an embodiment of the present invention.

Reference numeral 100 denotes a Switch Network Sub system. The switch network subsystem 100 includes a network synchronization device (NES) 1, a plurality of central data links (CDL) 2, a space switch 3, and a processor. It consists of an Inter Processor Communication Unit (IPCU) 4 which controls the inter-communication and a plurality of control processors.

Looking at the configuration of the control processors of the switch network subsystem 100, an inter-network processor (INP) (5) for controlling the entire call path system, and controls the number translation and routing (routing) function Number Translation Processor (NTP) (6), Network Synchronization Precessor (NSP) (9) for controlling network synchronizer (1), and switch network in charge of maintenance of switch network. A processor (INMP: Interconnection Network Maintenance Processor) 8, a Space Switch Processor (SSP) 7 for controlling the Space Division Switch 3, and a central control unit for a processor communication control unit in the center of the system. It consists of a link processor (CLIP: Central Link Interface Processor) 10.

Reference numerals 110, 120, and 130 denote access switch sub systems. The access switch subsystem is classified into a subscriber subsystem 110, a trunk line subsystem 120, and a NO.7 signal processing subsystem 130 according to its use.

Each of the access switch subsystems 110, 120, and 130 includes an access switch processor (ASP) 20 for overall control of the corresponding access switch system, and maintenance of the access switch subsystem. An access switch maintenance processor (ASMP) 21, a time division switch and a local data link (TSL) 22, and the time division switch and a local data link 22. Is commonly provided with a time-switched switch control processor 23.

The subscriber access switch subsystem 110 may include an analog subscriber interface (ASI) 24, an analog subscriber interface processor (ASIP) 25 controlling the subscriber module 24, and It consists of a Local Service Processor (LSI) 27 which processes a Dual Tone Multi Frequency (DTMF) signal and various audible signals.

In addition, in the case of the trunk line access switch subsystem 120, a T1 trunk line unit (OTI: Digital T1 Interface) 28 and a T1 trunk line control processor (DTIP: Digital T1 Interface Processor) for controlling the T1 trunk line unit 28 ( 29), an E1 trunk line unit (DCI: Digital CEPT Interface) 30, a trunk line control processor (DCIP: Digital Cept Interface Processor) 31 for controlling the E1 trunk line unit 3, and an R2 signal. A local service unit (LSI) 32 and a signaling device processor (LSP) 33 for controlling the local service unit 32 are included.

In the case of the NO.7 signal access switch subsystem 130, a processor for controlling the NO.7 signal terminal group (STG) 34 and the NO.7 signal terminal group 34 (SMHP: Signaling Message Handling Processor (35).

Reference numeral 140 denotes an operational and maintenance switch subsystem. The operation and maintenance switch subsystem includes an operating and maintenance processor (OMP) 40 that manages operation and maintenance, and a man machine processor (MMP) that is in charge of man-machine communication (MMC) processing 41 A common control maintenance processor (CCMP) 42 and various peripheral devices.

The peripheral devices include a disk (DK) 43, a magnetic tape unit (MT) 44, a printer (PRT) 46, a CRT 45, and a PC 47. And an alarm panel (AP) 48.

And to implement redundancy of transfer data bus

A first step of initiating an operation for fault detection of the transfer data bus;

A second process of controlling the transfer of control of the transfer data bus to the counterpart by transmitting data through the IPCU (4) when there is a possibility of recovery in operation on the counterpart when the counterpart detects a failure of the transfer databus; ,

A third process of checking a state of a counterpart processor when detecting a failure of the transfer data bus and transitioning a state of a device while continuing to control itself if there is no possibility of recovery when the counterpart operates;

The fourth step is to transfer the transfer data bus control to perform the failover of the transfer data bus quickly or on its own.

Therefore, an embodiment of the present invention will be described in detail with reference to FIG.

Detecting the failure or failure of the transfer data bus cable is possible only on the side of the control of the redundant processor, so it detects the failure at the time of the failure and reports the failure through the IPCU (4) to the other side. The processor on the reported side selects the transfer data bus to its side and can continue service if no fault is detected. If a fault occurs in the handed-in side, the device continues to access the device. After a certain time, it transfers control to the transfer data bus to the other side and maintains the service when the other side's fault is restored. Start the task to detect the failure of the transfer data bus, the task is executed at regular intervals through the periodic tasks provided by the operating system, and in the event of a failure in order to continue to maintain the service for more than 40m sec The task checks whether it is the side that it is controlling, and if it is its own side, accesses the device through the transfer data bus and detects the failure. On the side of To do this, it is to set the control bit of its own side by looking at the control bit of the other side. If the value of two bits is equal to 00,11, it is controlled by the processor B. If it is different from 01, 10, A side The processor is responsible for controlling the device. When the two bits are controlled by the other side, the changed value is transmitted to the opposite side. To set the opposite side, the bit of the opposite side is adjusted to change the control of the TD_bus. The device is adapted to select the TD bus by looking at the combination of the two bits. If the processor on the A side is set to 1, the processor on the other side sets its control bit to 1 to make the TD_bus its own control in order to change the TD_bus to its own control. The control of the TD bus changes because of a change in the combination of the two bits. Basically, maintenance of services due to TD_bus interruption or failure is performed through the TD_bus control bit. When the TD_bus is mounted, inconsistency of control bits of the TD_bus does not occur, but In this case, there may be a mismatch between the TD_bus control bits known by the device and the control bits known by the processor. As a simple example, when the A_ side control bit of the TD_bus is set to 0 and the B_ side control bit is set to 1, the control of the device is performed by the A_ side processor. If the TD bus connected to A_ side is disconnected in the above state, the A_ side control bit known to the AB processor is 0, but the state of the bus must be set to 1, or hernia, and the control must be passed to the other side. If the TD bus is selected, the control of the TD bus is skipped as intended. The periodic processor checks the status of the device through the transfer data bus so that the occurrence of a failure can be detected quickly, and the failure of the device When an occurrence is detected, the control of the device is transferred to the counterpart. The transfer data bus control bit is set to 1 before the control is passed through the IPCU 4 to the counterpart. _ If the operation after control of the bus is not done properly, transfer the control of the TD_bus to the other side immediately. The control bit of the bus is set to 1 and the control is transferred. The processor on the side of the transfer of control of the transfer data bus transfers control for a predetermined time since the transfer data bus managed by itself is in an abnormal state. If the service is not carried out with the control of the transfer data bus that was normally performed by checking the status of the data bus, the control of the transfer data bus is transferred to the other side after a certain period of time and the access of the transfer data bus is lost from the other side. If the control of the transfer data bus is not normally performed by both processors, the reason why the control of the transfer data bus is continuously transferred to the opposite side e is as described above. The reason for checking the status of the device through the transfer data bus is to pass the status of the transfer data bus to the opposite side. The reason for checking the status of the device through the transfer data bus is to check the status of the transfer data bus. If the transfer data bus on the other side recovers normally, there is no way to check the normal status on the other side. For this reason, the transfer data bus fails during the service and is a redundant processor. Even if the control of the transfer data bus is not performed properly on the other side, taking measures to divide the control of the device from the control of the transfer data bus even if the control of the transfer data bus It may be appropriate to respond after the operator has taken appropriate measures, as this may result in service disruption, and this function is not implemented.If both sides of the transfer data bus are not operating normally, This is due to the concerns that the operator can judge after the elapse of the transfer data bus, and that the maintenance of the service is not possible in the event of control failure on both devices. Since control to the failed control is performed through ipc (4), the control of the transfer data bus can be fatal in case of communication failure of ipc (4). Wait for the recognition signal and pass control The processor implements a structure in which the recognition signal is discarded after controlling the transfer data bus, and the processor of the controller that has passed the control implements control of the transfer data bus again when it does not receive the recognition signal for a predetermined time. If (4) does not operate normally or the recognition signal is lost due to instantaneous failure, the processors of both sides can control the transfer data bus at the same time. For events occurring in the state, check the control bit of the transfer data bus to check whether the control of the transfer data bus is regained or not to control the transfer data bus. To prevent you from controlling Since the transfer data bus can be connected to multiple devices together, the transfer data bus, which is normally accessed only by one device, in the case of the transfer data bus that spans multiple devices when the transfer data bus is detected, is normal. To be determined.

As described above, in case of a failure of the transfer data bus that is responsible for communication between the device and the processor, the processor implemented with redundancy takes advantage of redundancy and appropriately responds when the failure occurs only on one side of the redundant processor. It is possible to continuously perform the on-going service and on-going service, thereby improving the reliability of the call service and contributing to stabilization.

Claims (1)

In the redundancy method of the exchange system A first step of initiating an operation for fault detection of the transfer data bus; A second process of controlling the transfer of control of the transfer data bus to the counterpart by transmitting data through the IPCU (4) when there is a possibility of recovery in operation on the counterpart when the counterpart detects a failure of the transfer databus; , A third process of checking a state of a counterpart processor when detecting a failure of the transfer data bus and transitioning a state of a device while continuing to control itself if there is no possibility of recovery when the counterpart operates; 4. A transfer data bus redundancy method according to claim 4, wherein the transfer data bus control is carried out by a fourth process of transferring the transfer data bus control to perform the recovery of the transfer data bus quickly or by itself.