CN101667152A - Computer system and method for monitoring bus of same - Google Patents
Computer system and method for monitoring bus of same Download PDFInfo
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- CN101667152A CN101667152A CN200910093958A CN200910093958A CN101667152A CN 101667152 A CN101667152 A CN 101667152A CN 200910093958 A CN200910093958 A CN 200910093958A CN 200910093958 A CN200910093958 A CN 200910093958A CN 101667152 A CN101667152 A CN 101667152A
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Abstract
The invention relates to a computer system and a method for monitoring a bus of the computer system. The system comprises a master device, a slave device, a back plate bus and a bus timer, wherein themaster device is connected with the slave device by the back plate bus. The back plate bus comprises an address latch enabling signal line and a bus error signal line, wherein the address latch enabling signal line is used for transmitting an address latch enabling signal, and the bus error signal line is used for transmitting a bus error signal. The computer system also comprises a bus monitoring unit, wherein the bus monitoring unit is connected with the address latch enabling signal line and the bus error signal line and used for starting the bus timer to time when receiving the bus address latch enabling signal by the address latch enabling signal line and for transmitting the bus error signal by the bus error signal line when the bus timer is overtime.
Description
Technical field
The present invention relates to field of computer technology, relate in particular to the method for monitoring bus of a kind of computer system and computer system.
Background technology
Computer system is widely used in fields such as IT, telecommunications, Industry Control, communications and transportation, Aero-Space.Core bus in the computer system is used to realize the connection of dissimilar equipment, is one group of transmission line that the signal transmission is provided for a plurality of functional parts.Computer system in different application field and application scenario, the form of its core bus are also different.
Along with computer technology, development of internet technology, core bus has experienced parallel buss such as VME, ISA/PCI, reaches the interconnected development of point-to-point such as PCI-E.And,,, the reliability of computer system is had higher requirement as the development of each art such as Industry Control, communications and transportation, Aero-Space along with security fields.Accordingly, the reliability of core bus is also had higher requirement.
In the prior art, computer system adopts standard module integrated circuit board (VersaModule Eurocard, VME) connection of bus realization equipment of European industrial circle.The VME bus combines the electrical standard of the Versa of company of Motorola (Motorola) bus and the mechanical form factor of the Eurocard standard set up in Europe, is a kind of versabus that adopts open architecture.The computer system that adopts the VME bus is widely used in fields such as Industry Control, military systems, Aero-Space, communications and transportation and medical treatment through years of development.
The computer system that adopts the VME bus be the VME system function structure as shown in Figure 1, the VME bus adopts asynchronous transmission mechanism, the address wire width is 16,24,32,40 or 64, the data line width is 8,16,24,32,64.The VME system mainly is made up of signal wire, backplane interface logic and functional module.The VME bus comprises four big classes: data transmission bus, data transmission arbitration bus, Priority Interrupt Bus and versabus.Data transmission bus is a high-speed asynchronous panel data transfer bus, can transmit data and address signal.The data transmission arbitration bus is for guaranteeing that having only a module to take data transmission bus sets in the specific time, and the requester and the moderator that are operated on the data transmission arbitration bus will be responsible for coordinating the instruction that each module is sent.Priority Interrupt Bus is to handle the bus of each module interrupt request.Various interrupt request have been divided into 7 grades in the VME system.According to the height of grade, various interrupt request are carried out interruption of work to signal wire successively.Versabus is responsible for system to groundworks such as the control of clock, initialization, error-detecting.Versabus is made of two clock lines, a system reset line, a thrashing line, an AC inefficacy line and a serial data line.
In realizing process of the present invention, the inventor finds that there is following shortcoming at least in prior art: the VME bus signal line needs 82 at least in the computer system, and quantity is very big, has increased the volume of system; And VME bus interface complexity adopts logic chip to finish the cost height.
Summary of the invention
The embodiment of the invention proposes the method for monitoring bus of a kind of computer system and computer system, to reduce the volume of computer system, lowers the cost of computer system.
The embodiment of the invention provides a kind of computer system, comprises main equipment, slave unit, core bus and bus timer, and described main equipment is connected by described core bus with slave unit; Wherein, described core bus comprises:
The address latch enable signal line is used for the transport address latch enable signal;
The bus error signal line is used for the transfer bus rub-out signal;
Described computer system also comprises:
The monitoring bus unit links to each other with described address latch enable signal line and bus error signal line, is used for starting described bus timer timing when receiving the bus address latch enable signal by described address latch enable signal line; When described bus timer is overtime, send bus error signal by described bus error signal line.
The embodiment of the invention also provides a kind of method for monitoring bus of computer system, comprising:
When receiving the bus address latch enable signal, start the bus timer timing;
When described bus timer is overtime, send bus error signal.
The foregoing description starts the timer timing according to address latch enable signal, and under the situation of timer expiry, send bus error signal, make computer system adopt the simple local bus of transmission mechanism (Local Bus), the bus data transmission that just can realize, thereby significantly reduced bus number, reduce volume, reduced cost.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is the functional frame composition of VME system in the prior art;
The structural representation of a kind of computer system that Fig. 2 provides for the embodiment of the invention;
The structural representation of the another kind of computer system that Fig. 3 provides for the embodiment of the invention;
Fig. 4 is a kind of bus system cell schematics in the computer system shown in Figure 3;
Fig. 5 is the another kind of bus system cell schematics in the computer system shown in Figure 3;
Fig. 6 is the state flow chart of bus in the computer system shown in Figure 3;
Fig. 7 is the workflow diagram of monitoring bus unit 31 among Fig. 3;
Sequential chart when Fig. 8 exists equipment to make a mistake in the read cycle for 33 initiations of main equipment in the computer system shown in Figure 3;
Sequential chart when existing equipment to make a mistake in the write cycle time of Fig. 9 for 33 initiations of main equipment in the computer system shown in Figure 3;
The write cycle time sequential chart that Figure 10 makes a mistake for master-slave equipment in the computer system shown in Figure 3;
The read cycle sequential chart that Figure 11 makes a mistake for master-slave equipment in the computer system shown in Figure 3;
The structural representation of another computer system that Figure 12 provides for the embodiment of the invention;
Figure 13 is the process flow diagram of system shown in Figure 12 work;
A kind of application synoptic diagram of the computer system that Figure 14 provides for the embodiment of the invention;
Figure 15 uses synoptic diagram for the another kind of the computer system that the embodiment of the invention provides;
The process flow diagram of the method for monitoring bus of a kind of computer system that Figure 16 provides for the embodiment of the invention.
Embodiment
The structural representation of a kind of computer system that Fig. 2 provides for the embodiment of the invention.This computer system comprises main equipment 21, slave unit 22, core bus 23, bus timer 24 and the monitoring bus unit 25 that is positioned on the backboard 20.Described main equipment 21 is connected by described core bus 23 with slave unit 22.Described core bus 23 can comprise: address latch enable signal line 231, bus error signal line 232.Address latch enable signal line 231 is used for transport address latch enable signal (ALE).Bus error signal line 232 is used for transfer bus rub-out signal (BERR#).Monitoring bus unit 25 links to each other with described address latch enable signal line 231 and bus error signal line 232, is used for starting described bus timer 24 timing when receiving ALE by described address latch enable signal line 231; When described bus timer 24 is overtime, send BERR# by described bus error signal line 232.
Described monitoring bus unit 25 can be positioned on main equipment 21, slave unit 22 or the backboard 20.
Described core bus 23 also can comprise: address date (AD) signal wire, read-write (R/W) signal wire, bus enable (EN_BUS) signal wire.
Described core bus 23 also can comprise: bus acknowledge signal line 233.Bus acknowledge signal line 233 links to each other with described monitoring bus unit 25, and the answer signal that is used to transmit the read-write that described slave unit 22 initiates at described main equipment 21 is bus acknowledge signal (DTACK#).At this moment, described monitoring bus unit 25 stops described bus timer 24 timing when receiving DACK# by described bus acknowledge signal line 233.
The computer system that the embodiment of the invention provides also can comprise: core bus driver 26.Core bus driver 26 is arranged on described main equipment 21 and the described slave unit 22, is used for being output as the AD signal of high resistant when receiving BERR# by described bus error signal line 232.
The computer system that the embodiment of the invention provides also can comprise: sequential monitoring unit 27.Sequential monitoring unit 27 is positioned at described main equipment 21 or slave unit 22, be used to monitor the time sequence status of described main equipment 21 or slave unit 22, and when the time sequence status of described main equipment 21 or slave unit 22 is unusual, close closed bus and enable (EN_BUS#), or the AD signal of closing described main equipment 21 or slave unit 22 is exported, or the bus timing generator 28 of reset described main equipment 21 or slave unit 22, or the described monitoring bus unit 25 that resets.
Described core bus can be at least two covers.The described core bus that is at least two covers adopts identical clock.Can be n (n 〉=2) cover as core bus, the clock that this n cover core bus adopts is identical.
In the present embodiment, core bus adopts address latch enable signal line, bus error signal line and bus acknowledge signal line, the bus data that makes computer system adopt the simple local bus of transmission mechanism (Local Bus) just can realize transmits, thereby significantly reduced bus number, reduce volume, reduced cost.And computer system is monitored bus by the monitoring bus unit, has effectively suppressed bus deadlock, level that bus error causes and has drawn dead phenomenon.
The structural representation of the another kind of computer system that Fig. 3 provides for the embodiment of the invention.In the present embodiment, computer system comprises monitoring bus unit 31, bus timer 32, main equipment 33, first slave unit 34, second slave unit 35 and core bus 36.Main equipment 33 is provided with sequential monitoring unit 331, bus timing generator 332 and core bus driver 333.First slave unit 34 is provided with sequential monitoring unit 341, bus timing generator 342 and core bus driver 343.Second slave unit 35 is provided with sequential monitoring unit 351, bus timing generator 352 and core bus driver 353.The electrical specification specification of core bus 36 meets low-voltag transistor-transilog level (LVTTL) specification.Core bus 36 comprises local bus, the bus of shaking hands, interrupt request singal IRQ[3:0] # line, backboard groove position indicator signal GM[4:0] line, power-fail signal wire and additional RS-485 universal serial bus.The signal of local bus comprises: data/address signal AD[15:0], address latch enable signal ALE, bus enable signal EN_BUS#, read-write R/W#.As two covers during core buss, local bus also comprises and is used for clock signal synchronous CLK.The signal of the bus of shaking hands comprises: device responds answer signal DTACK# and error of transmission indicator signal BERR#.The signal definition of each line specifically sees table 1 for details in the core bus 36.
Table 1
| Signal | Definition | Describe in detail |
| AD[15:0] | Data/address signal | The address/data transmission channel of bus is in address phase place indication address, data phase designation data |
| ALE | Address latch enable signal | During high level, the address is passed through; The low level address latch |
| EN_BUS# | The bus enable signal | Enable the signal of whole bus valid function |
| R/W# | Read-write | During high level, main equipment reads the slave unit data, and during low level, main equipment writes data to slave unit |
| GM[4:0] | Groove position signal | Base address by these signal deciding veneer on the throne; Wherein GM4 is the slot number check bit. |
| IRQ[3:0] # | Look-at-me | The trigger request signals such as incident that slave unit request main equipment communicates with |
| DTACK# | Bus acknowledge signal | Slave unit is made corresponding response indication after main equipment is initiated read-write |
| BERR# | Bus error signal | After main equipment was initiated read-write, main equipment or slave unit can't be made the mistake indication that corresponding response produces because of slave unit |
| SYSRESET# | Systematic reset signal | Main equipment is to the reset signal of the slave unit of total system |
| DCFAIL# | The power-fail signal | Being used for indication input power supply falls or power down |
| SYSCLK | Clock signal of system | The system bus synchronous clock |
| RS-485+ | Difference string row communication positive signal | Difference string row communication positive signal |
| RS-485- | Difference string row communication negative signal | Difference string row communication negative signal |
Wherein, # represents that low level is effective.
Bus system unit in the computer system shown in Figure 3 such as Fig. 4, shown in Figure 5.The bus system unit comprises each master-slave equipment and the mutual backplane interface logic of core bus, and functional module, data processing equipment and the data input-output apparatus on each master-slave equipment backplane interface logical and core bus interaction results handled.
Fig. 6 is the state flow chart of bus in the computer system shown in Figure 3.Core bus 36 is by bus error treatment mechanism independently, and such as logic state machine testbus state independently, control bus isolating device simultaneously makes that slave unit occurs isolating core bus when wrong, prevents that the core bus level from being drawn extremely.Below in conjunction with Fig. 3 and Fig. 6 this fault processing mechanism is described.
Behind the computer system starting, main equipment 33 makes EN_BUS# effective, indicates first slave unit 34, second slave unit 35 to start working; Make ALE effective, start working in indication monitoring bus unit 31, the AD signal wire OPADD in the core bus 36.
When bus operation was initiated in monitoring bus unit 31, bus timer began counting.If bus operation is normally finished, then bus timer 32 counting is not to setting value such as N=64 clock period (CLOCK) and unlikely timer overflows, when bus operation is finished, trigger independently bus timer 32 termination countings, and the counting of zero clearing bus timer 32.If bus operation is because of causing state machine work overtime unusually, bus timer 32 timing are to setting value such as N=64 clock period (CLOCK) and overflow, then monitoring bus unit 31 triggering bus error signal BERR# are effective, stop this bus operation, main equipment and slave unit output signal AD all export three-state, discharge bus, and the reset bus state machine.At this moment, computer system is overflowed by bus timer 32 and is discharged core bus 36.
When with core bus 36 independently sequential monitoring unit 331, sequential monitoring unit 341 or sequential monitoring unit 351 sequential state machine that detects monitoring bus unit 31 hinder for some reason and can't overturn, in the time of also can't resetting or fix a breakdown, sequential monitoring unit 331, sequential monitoring unit 341 or sequential monitoring unit 351 close closed bus and enable, and isolate bus output.As adopting the invalid mode of enable signal of control 74LVT16245 to close the closed bus enable signal, corresponding bus timing generator 332, bus timing generator 342 or bus timing generator 352 and monitoring bus unit 31 simultaneously reset.
The workflow of monitoring bus unit 31 as shown in Figure 7.Fig. 7 is the workflow diagram of monitoring bus unit 31 among Fig. 3.Whether monitoring EN_BUS# effective for monitoring bus unit 31, when detect EN_BUS# invalid after, bus is not overturn, and is in idle condition; When detect EN_BUS# effectively after, state machine begins turning.And whether the sequential of sequential monitoring unit monitoring core bus 36 state machines in the monitoring bus unit 31 is normal.When state machine was undesired, it is incorrect that main equipment 33 monitors sequential upset by the sequential monitoring unit, is bus state machine when undesired, closes closed bus and enable, and isolates bus output, and reset bus state machine and monitoring bus unit 31.
Adopt asynchronous transmission mechanism to realize under the situation of signal transmission at core bus 36, when first slave unit 34 takes place unusual, busy such as first slave unit 34, can't handle these bus cycles, perhaps first slave unit 34 can not be worked, self has isolated core bus 36 by 74HC16245, in the time of can't responding core bus 36, main equipment 33 carries out timeout treatment, the indication of output time-out error, when second slave unit 35 is received the time-out error indication, make corresponding reaction, guarantee core bus 36 normal runnings.
Sequential when existing equipment to make a mistake in the read cycle that main equipment 33 is initiated as shown in Figure 8.Main equipment 33 is a low level by the clock MASTER_CLK driving EN_BUS# of self, reaches ALE and is changed to high level, and the R/W# signal is put high level, AD[15:0] the OPADD signal, start bus timer 32 timing simultaneously.After three clock period, it is low level that main equipment 33 drives ale signal, termination address output simultaneously.First slave unit 34 and second slave unit 35 drive the address signal that sampling receives by the clock SLAVE_CLK of self, and judge whether addressing oneself, be then when main equipment 33 drives ale signals and is low level, the data of appropriate address unit be put on the AD signal wire of bus.Equipment can't be replied because of certain reason if be addressed, causing DTACK# is high level, then monitoring bus unit 31 is because DTACK# keeps high level to cause bus timer 32 countings to surpass for 64 cycles and overflows always, carry out the bus error handling processing, driving the BERR# signal is low level, after two clock period, drive the BERR# signal to high level, and driving EN_BUS# is a high level.
Sequential when existing equipment to make a mistake in the write cycle time that main equipment 33 is initiated as shown in Figure 9.Main equipment 33 drives the EN_BUS# low level by the clock MASTER_CLK of self, and ALE puts high level, and to drive the R/W# signal be low level, AD[15:0] the OPADD signal, start bus timer 32 timing simultaneously.After three clocks, main equipment 33 drives the ale signal low level, termination address output simultaneously.First slave unit 34 and second slave unit 35 drive the address signal that sampling receives by the clock SLAVE_CLK of self, and judge whether addressing oneself.Be then when ALE is low level, data are put on the bus AD signal wire.Equipment can't be replied because of certain reason if be addressed, causing DTACK# is high level, then monitoring bus unit 31 causes bus timer 32 to overflow because DTACK# keeps high level always, carry out the bus error handling processing, driving the BERR# signal is low level, then driving the R/W# signal is high level, drives the BERR# signal afterwards to high level, and driving EN_BUS# is a high level.
In the present embodiment, computer system adopts the simple local bus of transmission mechanism, and by increasing a spot of handshake line, additional signal lines such as IRQ[3:0] # etc., and hardware has been realized simple, reliable, stable bus transfer mechanism and Timing Processing error mechanism.And independently bus error is exported ternary treatment mechanism, reliable guarantees to have prevented to draw extremely because of the bus level that this plate can't response bus causes.In addition,, make the bus number of computer system reduce owing to adopted local bus and the bus of shaking hands in the computer system, guaranteed identical and fully independently the dual channel system bus can on the connector of 96 pins, realize.
The structural representation of another computer system that Figure 12 provides for the embodiment of the invention.In the present embodiment, computer system has adopted two cover buses, and promptly all there is a cover bus separately in each system, is the model of typical fail-safe control system.Be provided with in first cover system 121 in first bus, 123, the second cover systems 122 and be provided with second bus 124.The module that each of first cover system 121 has a security function all needs to compare the consistent just output of result, inconsistent output, the while output error warning information of then blocking with the result of the corresponding function of second cover system 122.Realize the on all four core bus of two covers on a backboard, i.e. first bus 123 and second bus 124 make things convenient for and have realized the function of corresponding peace fail-safe system effectively.
Figure 13 is the process flow diagram of system shown in Figure 12 work.External information is input to the IO unit of two cover systems on the veneer respectively, finish comparison after, overlap the controller that bus independently is transported to two cover systems by two of a backboard and handle; If the employing method of synchronization, then data sync is input in two cover systems.Carry out in the time of the controller deal with data of two cover systems in veneer synchronously with relatively, the comparative result unanimity just continues calculation process; Comparative result is inconsistent, then return back to a correct step to rerun.If the employing method of synchronization, the then processing of data and relatively adopt the method for synchronization to finish.The end product that computing obtains, overlapping independently by two of same backboard, bus is transported to the cover of two in veneer IO system.The result that two cover IO system dockings are received compares, as a result unanimity, then output execution simultaneously; The result is inconsistent, then blocks output, and produces warning information.
In the present embodiment, computer system adopt two cover systems and independently two the cover buses carry out data transmission and processing, improved the reliability of data transmission and processing, can be applicable to the high fields of safety requirements such as Industry Control, Aero-Space.And a system also can adopt many cover buses further to improve reliability, is convenient to the fail-safe technology and realizes.
The computer system that the foregoing description provides may be used on control fields such as industry, on the core bus of the control machine frame that message transmission rate is not too high.The computer system application that present embodiment provides is when industrial control system, and the controller machine frame as shown in figure 14.A kind of application synoptic diagram of the computer system that Figure 14 provides for the embodiment of the invention.The computer system application that present embodiment provides is when the safety product dual bus, and as shown in figure 15, Figure 15 uses synoptic diagram for the another kind of the computer system that the embodiment of the invention provides.
The process flow diagram of the method for monitoring bus of a kind of computer system that Figure 16 provides for the embodiment of the invention.This method comprises:
Above-mentioned steps 161, step 162 can be carried out by the computer system that said system embodiment provides.
In the above-mentioned steps 161, when the bus address latch enable signal is effective, the monitoring bus unit starting bus timer timing in the computer system.
In the above-mentioned steps 162, the monitoring bus unit arrives setting value at bus timer, and bus operation is when remaining unfulfilled, timer expiry then, the monitoring bus unit sends BERR#, to stop this bus operation, discharge bus, specifically see the explanation among the said system embodiment for details.
The technical scheme that present embodiment provides discharges bus by send BERR# under the situation of timer expiry, has effectively suppressed computer system dorsulum bus level and has been drawn dead phenomenon.
In the method for monitoring bus of the computer system that the embodiment of the invention provides, when described bus timer is overtime, can also carry out following at least a operation: stop described bus timer timing; Controlling this plate AD bus-out signal is high resistant.Wherein, the monitoring bus unit in the computer system that the timing of terminated bus timer can be provided by said system embodiment is carried out, and controlling this plate AD bus-out signal is that high resistant can be carried out by each master-slave equipment, specifically see the explanation among the said system embodiment for details.
The method for monitoring bus of the computer system that the embodiment of the invention provides also can comprise: when DTACK# is effective, stop the bus timer timing.Monitoring bus unit in the computer system that this action can be provided by said system embodiment is carried out, and specifically sees the explanation among the said system embodiment for details.
The method for monitoring bus of the computer system that the embodiment of the invention provides also can comprise: the time sequence status of monitoring main equipment or slave unit, when the time sequence status of described main equipment or slave unit is unusual, close the closed bus enable signal, or the AD signal of closing described main equipment or slave unit is exported, or reset bus timing sequencer, or reset bus monitoring unit, sequential monitoring unit in the computer system that this action can be provided by said system embodiment is carried out, and specifically sees the explanation among the said system embodiment for details.
The technical scheme that the foregoing description provides has effectively suppressed bus deadlock, level that bus error causes by the monitoring bus unit and has drawn dead phenomenon, and when having guaranteed the components of system as directed fault, the normal part of equipment can be made the fail-safe measure.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of programmed instruction, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (11)
1, a kind of computer system comprises main equipment, slave unit, core bus and bus timer, and described main equipment is connected by described core bus with slave unit; It is characterized in that described core bus comprises:
The address latch enable signal line is used for the transport address latch enable signal;
The bus error signal line is used for the transfer bus rub-out signal;
Described computer system also comprises:
The monitoring bus unit links to each other with described address latch enable signal line and bus error signal line, is used for starting described bus timer timing when receiving the bus address latch enable signal by described address latch enable signal line; When described bus timer is overtime, send bus error signal by described bus error signal line.
2, computer system according to claim 1 is characterized in that, described monitoring bus unit is positioned on main equipment, slave unit or the backboard.
3, computer system according to claim 1 is characterized in that, also comprises:
The core bus driver is arranged on described main equipment and the described slave unit, is used for being output as the address data signal of high resistant when receiving bus error signal by described bus error signal line.
4, computer system according to claim 1 is characterized in that, also comprises:
The bus acknowledge signal line links to each other with described monitoring bus unit, is used to transmit the answer signal of described slave unit at the read-write of described main equipment initiation;
Described monitoring bus unit is used for stopping described bus timer timing when receiving bus acknowledge signal by described bus acknowledge signal line.
5, according to each described computer system among the claim 1-4, it is characterized in that described core bus also comprises: address data signal line, reading writing signal line, bus enable signal line.
6, computer system according to claim 5 is characterized in that, also comprises:
The sequential monitoring unit, be positioned at described main equipment or slave unit, be used to monitor the time sequence status of described main equipment or slave unit, and when the time sequence status of described main equipment or slave unit is unusual, close the closed bus enable signal, or close the address data signal output of described main equipment or slave unit, or the bus timing generator of reset described main equipment or slave unit, or the described monitoring bus unit that resets.
7, computer system according to claim 1 is characterized in that, described core bus is at least two covers; The described core bus that is at least two covers adopts identical clock.
8, a kind of method for monitoring bus of computer system is characterized in that, comprising:
When receiving the bus address latch enable signal, start the bus timer timing;
When described bus timer is overtime, send bus error signal.
9, the method for monitoring bus of computer system according to claim 8 is characterized in that, when described bus timer is overtime, also carries out following at least a operation: stop described bus timer timing; Controlling this plate AD bus-out signal is high resistant.
10, according to Claim 8 or the method for monitoring bus of 9 described computer systems, it is characterized in that, also comprise: when bus acknowledge signal is effective, stop the bus timer timing.
11, according to Claim 8 or the method for monitoring bus of 9 described computer systems, it is characterized in that, also comprise: the time sequence status of monitoring main equipment or slave unit, when the time sequence status of described main equipment or slave unit is unusual, close the closed bus enable signal, or close the address data signal output of described main equipment or slave unit, or the reset bus timing sequencer, or the reset bus monitoring unit.
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