CN113722251B - Two-wire SPI communication system and method for functional safety monitoring - Google Patents
Two-wire SPI communication system and method for functional safety monitoring Download PDFInfo
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- CN113722251B CN113722251B CN202010453451.6A CN202010453451A CN113722251B CN 113722251 B CN113722251 B CN 113722251B CN 202010453451 A CN202010453451 A CN 202010453451A CN 113722251 B CN113722251 B CN 113722251B
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- 238000004891 communication Methods 0.000 title claims abstract description 20
- 238000012544 monitoring process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 11
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 238000012545 processing Methods 0.000 claims description 14
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0038—Details of emergency protective circuit arrangements concerning the connection of the detecting means, e.g. for reducing their number
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
A two-wire SPI communication system for functional security monitoring, comprising: a master mode SPI controller, a high voltage isolation chip, a level shifter circuit, and a slave mode SPI controller connected by a CLK signal line and an MTSR signal line, and a DMA controller, a Ram buffer, a CRC controller, an interrupt controller, and a timer, wherein: the DMA controller, the Ram buffer area and the CRC controller are sequentially connected with the slave mode SPI controller, the slave mode SPI controller receives an expected data bit of an MTSR pin, then generates an Rx DMA request and transmits the Rx DMA request to the DMA controller, the DMA controller transmits the Rx DMA request to the Ram buffer area, the CRC controller calculates the CRC value in the Ram buffer area and compares the CRC value with the expected value, the interrupt controller is respectively connected with the slave mode SPI controller and the DMA controller, and the timer is connected with a CS pin of the slave mode SPI controller. The invention adopts two SPI communication lines, which not only can reduce the hardware wiring quantity and simplify the isolator selection to reduce the cost, but also can realize the data synchronization, monitor the communication fault and complete the data disassembly.
Description
Technical Field
The invention relates to a technology in the field of communication, in particular to a double-wire SPI communication system and method for functional safety monitoring.
Background
The motor controller for the vehicle has a complex structure, but can be divided into two parts: the controller and the driver are isolated by high voltage. In order to realize the protection and monitoring required by the functional safety specification, after the fault occurs, on one hand, the driver executes the protection action to enable the driver to quickly enter a safety state; on the other hand, the controller is required to feed back necessary information. In the prior art, a CPLD/FPGA is adopted as a control core of a driver end, communication with an MCU of the controller end is realized by using multiple SPIs, 4 or 3 signal wires are used for SPI communication, the problem of large hardware wiring quantity exists, and an isolator between the controller and the driver adopts a bidirectional transmission structure, so that the model selection is difficult and the cost is high.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention provides a double-wire SPI communication system and method for functional safety monitoring, which takes MCU at a controller end as SPI slave equipment and CPLD/FPGA at a driver end as master equipment, and adopts two signal wires: CLK, MTSR implement communication interactions.
The invention is realized by the following technical scheme:
the invention relates to a two-wire SPI communication system for functional safety monitoring, comprising: a master mode SPI controller, a high voltage isolation chip, a level shifter circuit, and a slave mode SPI controller connected by a CLK signal line and an MTSR signal line, and a DMA controller, a Ram buffer, a CRC controller, an interrupt controller, and a timer, wherein: the DMA controller, the Ram buffer area and the CRC controller are sequentially connected with the slave mode SPI controller, the slave mode SPI controller receives an expected data bit of an MTSR pin, then generates an Rx DMA request and transmits the Rx DMA request to the DMA controller, the DMA controller transmits the Rx DMA request to the Ram buffer area, the CRC controller calculates the CRC value in the Ram buffer area and compares the CRC value with the expected value, the interrupt controller is respectively connected with the slave mode SPI controller and the DMA controller to process an Err interrupt and a DMA interrupt, and the timer is connected with a CS pin of the slave mode SPI controller to enable the pin to output a pulse with a specific width according to a timing value and is used for controlling the closing time of the slave mode SPI controller.
The DMA interrupt processing mode is as follows: judging the value detected by the cycle counter, and when the value is an unexpected value, sending a sequence fault identification position; when the data is the expected value, checking by using a CRC controller, reading the CRC value from a result register of the CRC controller, comparing, and when the comparison result is correct, disassembling the data and storing the data into a global variable; and when the comparison result is wrong, identifying the CRC fault position.
The SPI Err interrupt processing mode is as follows: when the fault is judged to be the baud rate fault, the counter is increased by 1; when the value of the counter exceeds the threshold, setting the timing value of the timer to invalidate the CS pin for a long time and then to be effective; when the value of the counter does not exceed the threshold, setting the timing value of the timer to invalidate the CS pin for a short time and then to be effective; and finally resetting the internal state machine of the slave mode SPI controller.
The invention relates to a double-wire SPI communication method for functional safety monitoring based on the system, wherein a main mode SPI controller transmits data frames through a CLK signal wire and an MTSR. Since the master and slave SPI controllers do not necessarily start to operate at the same time, there is a time difference between the reception and transmission of the initial stage data. If the slave mode SPI controller starts to receive data after the master mode SPI controller first transmits several data bits in the data frame, the slave mode SPI controller will generate a baud rate failure and enter the SPI Err interrupt when the data frame transmission is completed. In SPI Err interrupt processing, the counter value of the timer is set to enable the CS pin to be pulled high so that the slave mode SPI controller stops working and resets an internal state machine in the period of time, and therefore follow-up data is received correctly, and synchronous communication of the master SPI and the slave SPI is achieved.
Technical effects
Compared with the prior art, the invention adopts two SPI communication lines, which not only can reduce the hardware wiring quantity and simplify the isolator selection to reduce the cost, but also can realize data synchronization, monitor communication faults and complete data disassembly, thereby effectively meeting the condition monitoring of the driver by the controller required by the functional safety standard.
Drawings
FIG. 1 is a schematic illustration of the present invention;
FIG. 2 is a schematic diagram of the processing of a DMA interrupt and an SPI Err interrupt;
FIG. 3 is a diagram of a data frame format;
FIG. 4 is a SPI timing diagram;
FIG. 5 is a schematic diagram of a transmission mode of a data frame;
FIG. 6 is a waveform diagram generated after detection of a baud rate failure from a mode SPI controller;
FIG. 7 is a waveform diagram of the correct receipt of data from the mode SPI controller;
in the figure: slave mode SPI controller 101, DMA controller 102, ram buffer 103, CRC controller 104, interrupt controller 105, timer 106, level shifter 107, high voltage isolation chip 108, and master mode SPI controller 109.
Detailed Description
The embodiment relates to a 32-bit dual-line SPI communication system for functional safety monitoring, as shown in FIG. 1, specifically comprising: a master mode SPI controller 109, a high voltage isolation chip 108, a level conversion circuit 107, and a slave mode SPI controller 101, and a DMA controller 102, a Ram buffer 103, a CRC controller 104, an interrupt controller 105, and a timer 106, which are connected through a CLK signal line and an MTSR signal line, wherein: the DMA controller 102, the Ram buffer 103 and the CRC controller 104 are sequentially connected to the slave mode SPI controller 101, the slave mode SPI controller 101 receives the MTSR pin to 32 bits of data, generates an Rx DMA request and transmits the Rx DMA request to the DMA controller 102, the DMA controller 102 transmits the Rx DMA request to the Ram buffer 103, the CRC controller 104 calculates a CRC value in the Ram buffer 103 and compares the CRC value with an expected value, the interrupt controller 105 is connected to the slave mode SPI controller 101 and the DMA controller 102 to process the SPI Err interrupt and the DMA interrupt, respectively, the timer 106 is connected to the CS pin of the slave mode SPI controller 101, and the slave mode SPI controller 101 operates when the CS pin is at a low level.
The configuration of the slave mode SPI controller 101 includes: the clock frequency is 500KHz; the data receiving edge is a falling edge; enabling a baud rate fault detection function; enabling the Rx Dma function; enabling SPI Err interrupt.
The configuration of the DMA controller 102 includes: the data source address is a shift register address of the slave mode SPI controller 101; the data target address is the first address of the Ram buffer 103; the data width is 32 bits; the number of data transfers after the DMA trigger is one, that is, once data transfer is performed every time 32 bits of data are received from the mode SPI controller 101.
The CRC controller 104 is SAE J1850CRC8, and the abnormal threshold value is OxFF.
The level conversion circuit 107 is used for signal matching between the master mode SPI controller 109 and the slave mode SPI controller 101, and the level conversion chip adopts a unidirectional transmission chip.
The high-voltage isolation chip 108 realizes high-voltage and low-voltage electrical isolation between the master mode SPI controller 109 and the slave mode SPI controller 101, and is a unidirectional transmission chip.
The Ram buffer 103 has byte alignment characteristics.
As shown in fig. 2, the specific way of DMA interrupt processing is as follows: judging the value detected by the cycle counter, and when the value is an unexpected value, indicating that the frame is lost during transmission, sending the sequence fault identification position and exiting; when the data frame is the expected value, checking by using the CRC controller 104, specifically filling the data frame into an input register of the CRC controller 104, reading the CRC value from a result register of the CRC controller 104, comparing, and when the comparison result is correct, disassembling the data and storing the data into a global variable; and when the comparison result is wrong, identifying the CRC fault position.
The specific mode of SPI Err interrupt processing is as follows: when judging that the fault is not the baud rate fault, switching to other fault processing flows; when the fault is judged to be the baud rate fault, the counter is increased by 1; when the value of the counter does not exceed the threshold, the timing value of the timer 106 is set to 1.6us; when the value of the counter exceeds the threshold, the timing value of the timer 106 is set to be 1ms, and the CS pin of the slave mode SPI controller 101 is pulled up to stop working for a period of time and then is recovered; finally, the internal state machine and buffer of slave mode SPI controller 101 are reset.
As shown in fig. 3, the information data structure of the master mode SPI controller 109 is: the cycle counter occupies the upper four bits, the last twelve bits being the actual data bits and the last eight being the first sixteen bits of the CRC.
The relationship between the clock signal edge of the slave mode SPI controller 101 and the data is as shown in fig. 4, and the slave mode SPI controller 101 reads the data on the falling edge of the clock signal.
The transmission mode of the data frame is shown in fig. 5, wherein: the upper four bits of the data frame are the cycle counter, on one hand, the cycle counter is used for monitoring the data flow, and the count value is increased by 1 every data frame; on the other hand, for identification of data information, each count value represents a corresponding physical quantity.
There is a 100us interval between the data frames to complete the DMA interrupt processing or SPI Err interrupt processing.
As shown in fig. 6 and 7, is an SPI signal waveform in which: ch1 is the clock CLK waveform; ch2 is a data MTSR waveform; ch3 is a GPIO port waveform, the pin is pulled high when entering DMA interrupt processing, and the pin is pulled low when exiting; ch4 is a chip select waveform from the mode SPI controller 101, and is controlled by the output pin of the timer 106.
As shown in fig. 6, the waveform after the baud rate failure is detected from the mode SPI controller 101. The master mode SPI controller 109 transmits data, and after a delay of several clocks, the slave mode SPI controller 101 starts to operate and receives data, which causes a baud rate failure.
The SPI Err interrupt process sets the count value of timer 106, pulls the CS pin high by 1.6us, stops the slave mode SPI controller 101 during this period, resets the internal state machine, and then receives the following data to achieve synchronization of master mode SPI controller 109 and slave mode SPI controller 101.
As shown in fig. 7, the waveform of data is received from the mode SPI controller 101, and the pulse signal of Ch3 describes an Rx Dma request generated after the reception of data from the mode SPI controller 101, and performs fault detection and data disassembly in the Dma interrupt process.
The foregoing embodiments may be partially modified in numerous ways by those skilled in the art without departing from the principles and spirit of the invention, the scope of which is defined in the claims and not by the foregoing embodiments, and all such implementations are within the scope of the invention.
Claims (2)
1. A two-wire SPI communication system for functional security monitoring, comprising: a master mode SPI controller, a high voltage isolation chip, a level shifter circuit, and a slave mode SPI controller connected by a CLK signal line and an MTSR signal line, and a DMA controller, a Ram buffer, a CRC controller, an interrupt controller, and a timer, wherein: the DMA controller, the Ram buffer area and the CRC controller are sequentially connected with the slave mode SPI controller, the slave mode SPI controller receives an expected data bit of an MTSR pin, then generates an Rx DMA request and transmits the Rx DMA request to the DMA controller, the DMA controller transmits the Rx DMA request to the Ram buffer area, the CRC controller calculates a CRC value in the Ram buffer area and compares the CRC value with the expected value, the interrupt controller is respectively connected with the slave mode SPI controller and the DMA controller to process SPIerr interrupt and DMA interrupt, the timer is connected with a CS pin of the slave mode SPI controller to enable the pin to output a pulse with a specific width according to a timing value, and the slave mode SPI controller is controlled to be turned off for a long time by the pulse;
the DMA interrupt processing mode is as follows: judging the value detected by the cycle counter, and when the value is an unexpected value, sending a sequence fault identification position; when the data is the expected value, checking by using a CRC controller, reading the CRC value from a result register of the CRC controller, comparing, and when the comparison result is correct, disassembling the data and storing the data into a global variable; identifying a CRC fault position when the comparison result is wrong;
the processing mode of the SPIERR interrupt is as follows: when the fault is judged to be the baud rate fault, the counter is increased by 1; when the value of the counter exceeds the threshold, setting the timing value of the timer to invalidate the CS pin and then to be effective; when the value of the counter does not exceed the threshold, setting the timing value of the timer to invalidate the CS pin and then to be effective; and finally resetting the internal state machine of the slave mode SPI controller.
2. The two-wire SPI communication method for functional safety monitoring of the system of claim 1, wherein the master mode SPI controller transmits data frames through the CLK signal line and the MTSR, receives data from the mode SPI controller after a time delay due to the fact that the master and slave SPI controllers do not start to operate at the same time, generates a baud rate failure, and sets a counter value of a timer to raise a CS pin to cause the slave mode SPI controller to operate and reset an internal state machine during an interrupt processing period in the SPIErr interrupt processing, thereby correctly receiving subsequent data, and realizing master and slave SPI synchronous communication.
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