CN101662448B - Wireless communication method of high-speed sampling low-accuracy quantification impulse ultra-wideband - Google Patents
Wireless communication method of high-speed sampling low-accuracy quantification impulse ultra-wideband Download PDFInfo
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Abstract
The invention provides a wireless communication method of high-speed sampling low-accuracy quantification impulse ultra-wideband, aiming at the requirements of wireless communication with high speed, low cost, low power consumption and short distance. The method comprises the following steps: adopting a digital technology at a transmitting terminal to generate a base band narrow pulse sequence; carrying out modulation; transmitting the base band narrow pulse sequence after being amplified and filtered; directly carrying out high speed sampling and low-accuracy quantification on a received signal after being filtered and amplified by the receiving terminal; carrying out digital signal processing, such as synchronization and channel estimation, coherent detection and channel decoding and the like on the quantified data; and recovering transmitting information. Compared with the current carrier wave system UWB wireless communication technology, the method does not need complex radio frequency treatments such as quadrature modulation/demodulation and frequency spectrum shifting and the like, greatly reduces accuracy of quantization of the analog-digital conversion, and greatly reduces cost and power consumption. Compared with the current pulse system UWB wireless communication technology, the method in the invention greatly increases data transmission speed, and improves stability, reliability and integratability.
Description
Technical field
The present invention is a kind of method that realizes pulse system high speed super broad band radio communication, belongs to short-distance wireless communication and information dissemination technology field.
Background technology
As one of the core technology of ubiquitous radio communication in future, ultra broadband (UWB) wireless communication technology has obtained paying close attention to widely in recent years, and its research and development make remarkable progress.
The UWB technology generally can be divided into pulse system and two kinds of basic implementations of carrier wave system.Pulse system UWB has advantages such as system configuration is simple, cost is low, low in energy consumption through base band pulse sequence transmission information, is applied to fields such as low-speed wireless communication, range finding, detection at present more; The carrier wave system UWB adopts technology such as ripe modulation continuous carrier and OFDM (OFDM), and spectrum utilization efficiency is high, frequency spectrum resource uses flexibly.At present, at high speed UWB wireless communication field, the development of carrier wave system UWB is very fast, has formulated the technical standard that is the basis with many band OFDM schemes in the world, and has released many money experiment chips and experimental system.But the radio system of carrier wave system UWB scheme is complicated, and radio frequency chip realizes that difficulty is big, cost is high, and the AD conversion unit power consumption is big, makes the cost of present carrier wave system UWB chipset and power consumption further to reduce, and does not reach the demand in market.Present pulse system UWB technology generally adopts methods such as peak value detection, energy measuring, simulation coherent detection at receiving terminal, its performance receives the restriction of simulation process, generally can only realize radio communication and functions such as detection, location than low rate.
Summary of the invention
Technical problem: the objective of the invention is to propose a kind of high-speed sampling low-accuracy quantification impulse ultra-wideband wireless communications method; Realize pulse system high speed UWB radio communication; Solve the problem that existing pulse system UWB technology can only realize low-speed wireless communication, overcome problems such as the complexity height that carrier wave system UWB system exists, cost height simultaneously.
Technical scheme: the high-speed sampling low-accuracy quantification impulse ultra-wideband wireless communications method that the present invention proposes is the elementary cell of physical layer data transmission with the frame, produces the base band pulse sequence at transmitting terminal with digital method; With sending data this base band pulse sequence is modulated, and amplify and bandpass filtering, signal controlling is in the 4.2-4.8GHz frequency band after the filtering; Arrive aerial via antenna transmission; At receiving terminal, after carrying out filtering to received signal, amplifying, directly carry out high-speed sampling and low-accuracy quantification; Signal is transformed into numeric field; And design be applicable to high-speed sampling, low-accuracy quantification signal synchronously, channel estimating and related detecting method, the signal that is transformed into numeric field is handled, recover the information of transmission.
Said transmitting terminal is connected and composed by channel encoder, framer, digit pulse generation and modulator, transmitting terminal amplifier, transmitting terminal band pass filter and transmitting antenna successively; Receiving terminal is connected and composed by reception antenna, receiving terminal band pass filter, low noise amplifier, A-D converter, digital detector and channel decoder successively.
Channel encoder adding redundant information in the input data is encoded among Fig. 1, to improve the reliability of transmission; Framer is the dateout stream packets of channel encoder, and in every group of data, adds leading character, frame head information etc. and form frames, make receiving terminal can be correctly, effectively receive, frame is the elementary cell that physical layer data transmits; Digit pulse generation and modulator produce uniform base band burst pulse sequence; As the carrier of message transmission, and, the burst pulse sequence is modulated according to the bit stream that framer is exported; Promptly change polarity, amplitude or the position of pulse in the sequence, make the burst pulse sequence carry information; After the amplifier amplification of digital pulse sequence process transmitting terminal and transmitting terminal band-pass filter of digit pulse generation and modulator output, send in the air via transmitting antenna; At receiving terminal, reception antenna after receiving terminal band-pass filter and low noise amplifier amplification, is converted into digital signal by A-D converter from the signal of aerial reception; A-D converter is sampled, is quantized and encode signal, among the present invention, adopt the high-speed sampling of number GHz frequency, but the sample value that only each sampling is obtained is carried out the low-accuracy quantification of a bit or dibit precision; Digital detector utilizes the digital signal of A-D converter output, carries out frame detector, synchronously and channel estimating, coherent detection scheduling algorithm, recovers the message bit stream in the frame; After the output channel decoder for decoding of digital detector, obtain dateout.
As the frame of physical layer data transmission elementary cell, form by leading character, synchronization pattern, frame head part and data division, as shown in Figure 2.Wherein the pulse spacing of the leading character pulse train of partly sending is T1, and the pulse spacing of the pulse train that other part is sent is T2; The value of T1 is greater than the length of the energy main part of wireless channel impulse response, and the value of T2 to guarantee that sufficiently high pulse repetition frequency is arranged, obtains high message transmission rate less than T1.Therefore, leading character partly is big pulse spacing section, and other part is the small-pulse effect spacer segment.Can adopt modes such as pulse polarity modulation, pulse amplitude modulation and pulse position modulation that information is modulated on the pulse train.The pulse polarity modulation is represented symbol " 1 " or " 0 " with different pulse polarity; Pulse amplitude modulation is represented symbol " 1 " or " 0 " with the different pulse amplitude; Pulse position modulation is used with respect to the diverse location of uniform pulse sequence and is represented symbol " 1 " or " 0 ".In the statement below the present invention, adopt the pulse polarity modulation, and arrange positive pulse and represent symbol " 1 ", negative pulse is represented symbol " 0 ".But the method that the present invention proposes is equally applicable to other various pulse modulation modes.Leading character is made up of two parts pulse train, the S11={+ of first ,-,+,-... ,+}, wherein+with-represent that respectively positive pulse and negative pulse, its pulse number are N11, and N11 is an odd number; Second portion S12={-,+,-... ,+}, its pulse number is N12; Synchronization pattern is that a length is the selected pseudorandom positive negative pulse stuffing sequence of N2; Information such as frame head part transmission frame length, channel coding rate; The data message of data division for sending.In the statement of the present invention, synchronization pattern, frame head part and each burst transmissions one bit information of data division, but adopt the spread spectrum mode are applicable to the method that the present invention proposes too by the method for a plurality of burst transmissions one bit informations.
Described digit pulse adopt staggered clock signal with or regulate the clock signal duty cycle method and produce, Fig. 3 has provided and has adopted staggered clock signal and the digit pulse generation of method generation pulse and the realization schematic diagram of modulator.Fig. 4 has provided and has adopted adjusting clock signal duty cycle method to produce the digit pulse generation of pulse and the realization schematic diagram of modulator.In staggered clock signal and method; Clock generator produces high frequency clock signal; Clock distributor is a two-way with this signal replication, and delayer and delayer carry out the time-delay of different time to this two-way clock signal respectively, the two paths of signals after the time-delay with door carry out with.In the ideal case, if the time difference of two-way time-delay is the odd of half pulse period length, be output as zero with door; In other cases, with the door output pulse train identical with the clock cycle, its duty ratio changed with the time difference of two-way time-delay, through regulating the time difference, can access the pulse train of pulse duration in the subnanosecond level.With the pulse train input stopping direct current device of door output, its DC component of filtering.The output pulse sequence of stopping direct current device is a differential signal, and its positive and negative terminal is input selector simultaneously, and selector is selected the output of one of positive and negative terminal according to the input data, when being " 1 " such as data symbol, selects anode output, promptly exports positive pulse; When data symbol is " 0 ", select negative terminal output, promptly export negative pulse, so just realized the pulse polarity modulation of pulse sequence.In regulating the clock signal duty cycle method; The clock duty cycle adjuster is directly regulated the duty ratio of the clock sequence of clock generator generation, when duty ratio is very little, promptly obtains digital pulse sequence; This pulse train is differential signal; With the same among Fig. 3, behind stopping direct current device and selector, the pulse train after the output modulation.Among the present invention, digit pulse generation and modulator can use one of method of Fig. 3 and Fig. 4 to realize, after its output process transmitting terminal amplifier amplification and the transmitting terminal band-pass filter, can be met the UWB pulse train of spectrum criterion requirement.
At receiving terminal, A-D converter adopts the mode of high-speed sampling, low-accuracy quantification.Being suitable for quantified precision of the present invention is a bit or dibit.In the statement of the method for reseptance below the present invention, adopt a bit quantization precision, but the method for reseptance that the present invention proposes is equally applicable to the dibit quantified precision.As shown in Figure 5, when adopting a bit quantization, comparator compares incoming signal level and preset threshold level, output high level signal when being higher than threshold level, output low level signal when being lower than threshold level; The output of comparator is divided into n branch road through serial-parallel converter, samples, to reduce the requirement to each branch road sampling rate.Sampling clock input phase shifter, phase shifter output are with the input clock same frequency but the n road sampling clock and a circuit-switched data of out of phase read clock, and generally speaking, the phase difference between the sampling clock of the adjacent legs of output is 2 π/n.Sampler is sampled to its input signal at the edge of its input sample clock, and reads the edge of clock in data, and the numerical value that reads is transferred to subsequent conditioning circuit simultaneously.The clock edge that sampling and data read can be rising edge or trailing edge, also can adopt rising edge and trailing edge simultaneously.
The digital signal of A-D converter output is carried out a series of digital processings by digital detector, comprises that frame detects, synchronous and channel estimating and coherent detection etc., recovers the message bit stream in the frame.
Digital detector is made up of storage switch, sequence correlator, switch, threshold detector, channel estimator, correlation detector and bit synchronizer, and is as shown in Figure 6.The storage switch has data-storing and data flow handoff functionality, and the parallel data that receives through inner memory array, is at first exported to sequence correlator; Sequence correlator is according to the sequence S11 in the known leading character; With the sample value of each of receiving in the T1 interpulse period, multiply by the symbol of respective pulses among the sequence S11 after, the correspondence position in pulse adds up; Accumulation length is the length N 11 of sequence S11, and is as shown in Figure 7.Among Fig. 7, fs is a sample frequency, so T1 * fs is the interior sample number of each T1 interpulse period.Be a First Input First Output in the frame of broken lines, have N11 capable, T1 * fs sample value of every row storage has the line display of grid shade that this line data multiply by-1, and the line display of no grid shade keeps this line data constant.Input data formation process from then on multiply by-1 at the row that the grid shade is arranged, and in formation, adds up by row then, obtains T1 * fs accumulated value that constantly changes, and exports to subsequent module.The output of sequence correlator via switch, is at first exported to threshold detector; Threshold detector compares the accumulation result of sequence correlator output with preset threshold value, when detecting above thresholding, send control information and give switch and channel estimator; The data flow of sequence correlator output is switched to channel estimator, and start channel estimator, channel estimator is in the input data of its preseting length; Maximizing as the reference point of channel impulse response, and is starting point with Nb sample value of reference point rollback; Export T1 * fs sample value, the result as channel estimating exports to correlation detector.Simultaneously; The storage switch also will be exported in the peaked discovery position of channel estimating, and the storage switch is according to this position; Calculate the starting position of synchronization pattern in its memory array; And will be from then on the data that begin of position export to correlation detector and handle, data that correlation detector will receive from the storage switch and the channel estimation results that receives from channel estimator carry out related operation, obtain the estimation to the data symbol that each transmitted pulse transmitted; Bit synchronizer is searched for known synchronization pattern in the output of correlation detector, confirm the starting position of data division in the frame, accomplishes bit synchronous; If in preset time, do not find synchronization pattern, think that then this frame takes defeat, restart reception to a new frame.
Beneficial effect: the pulse system high speed UWB wireless communications method that the present invention proposes, can realize high-speed radiocommunication with lower system cost and power consumption.Compare with present carrier wave system UWB wireless communication technology, the method that the present invention proposes need not quadrature modulation/separate and is in harmonious proportion complicated radio frequency processing such as frequency spectrum shift, and the quantified precision of analog to digital conversion also reduces greatly, makes cost, power consumption reduce significantly; Compare with present pulse system UWB wireless communication technology, the method that the present invention proposes has adopted advanced digital received treatment technology, the 100Mbps that can message transmission rate be improved from hundreds of kbps, but and improved stability, reliability and integration.The present invention has great importance to the development of UWB technology and the progress of short-distance wireless communication technology.
Description of drawings
Fig. 1 is an entire system structured flowchart of the present invention.
Fig. 2 is a frame assumption diagram of the present invention.
Fig. 3 is for adopting and the digit pulse generation of method and the realization schematic diagram of modulator 3.
Fig. 4 regulates the digit pulse generation of duty ratio method and the realization schematic diagram of modulator 3 for employing.
Fig. 5 is the realization schematic diagram of the A-D converter 10 of a bit quantization precision.
Fig. 6 is digital detector 11 block diagrams.
Fig. 7 is sequence correlator 1102 functional schematics.
Embodiment
Provide a kind of embodiment of the present invention below, realize that the highest instantaneous transmission speed reaches the wireless communication system of 110Mbps.
The entire system structured flowchart is as shown in Figure 1.Channel encoder 1 adding redundant information in the input data is encoded among the figure, to improve the reliability of transmission; Framer 2 is the dateout stream packets of channel encoder 1, and in every group of data, adds leading character, frame head information etc. and form frames, make receiving terminal can be correctly, effectively receive, frame is the elementary cell that physical layer data transmits; Digit pulse generation and modulator 3 produce uniform base band burst pulse sequence; As the carrier of message transmission, and, the burst pulse sequence is modulated according to the bit stream that framer 2 is exported; Promptly change polarity, amplitude or the position of pulse in the sequence, make the burst pulse sequence carry information; After amplifier 4 amplifications of digital pulse sequence process transmitting terminal and 5 filtering of transmitting terminal band pass filter of digit pulse generation and modulator 3 outputs, send in the air via transmitting antenna 6; At receiving terminal, reception antenna 7 after 8 filtering of receiving terminal band pass filter and low noise amplifier 9 amplifications, is converted into digital signal by A-D converter 10 from the signal of aerial reception; 10 pairs of signals of A-D converter are sampled, are quantized and encode, and among the present invention, adopt the high-speed sampling of number GHz frequency, but the sample value that only each sampling is obtained are carried out the low-accuracy quantification of a bit or dibit precision; Digital detector 11 utilizes the digital signal of A-D converter 10 output, carries out frame detector, synchronously and channel estimating, coherent detection scheduling algorithm, recovers the message bit stream in the frame; After output channel decoder 12 decodings of digital detector 11, obtain dateout.
Channel encoder 1 adopts low-density checksum (LDPC) code coder, and the code rate of its support is 5/6,3/4,2/3 and 1/2, and the code block length behind the coding is 2304 bits.
Frame structure is as shown in Figure 2.One frame is made up of leading character, synchronization pattern, frame head part and data division, and wherein the pulse spacing of the leading character pulse train of partly sending is T1, T1=60.6ns, and the pulse spacing of the pulse train of other part transmission is T2, T2=7.58ns.The value of T1 is greater than the length of the energy main part of wireless channel impulse response, and the value of T2 to guarantee that sufficiently high pulse repetition frequency is arranged, obtains high message transmission rate less than T1.Therefore, leading character partly is big pulse spacing section, and other part is the small-pulse effect spacer segment.Adopt the pulse polarity modulation that information is modulated on the pulse train.The pulse polarity modulation is represented symbol " 1 " or " 0 " with different pulse polarity.
Leading character is made up of two parts pulse train, the S11={+ of first ,-,+,-... ,+}, wherein+with-represent that respectively positive pulse and negative pulse, its pulse number are N11, N11=1023; Second portion S12={-,+,-... ,+}, its pulse number is N12, N12=10.Synchronization pattern is that a length is the selected pseudorandom positive negative pulse stuffing sequence of N2=16.Information such as frame head part transmission frame length, channel coding rate.The frame head part is made up of physical layer frame head, medium access control (MAC) layer frame head and frame head verification sequence (HCS).Wherein physical layer frame head length degree is 24 bits, has comprised information such as code rate, data division length and scrambler initial value; Mac layer frame head length degree is 80 bits, has comprised information such as frame control, destination address, source address, frame sequential control and access control; The HCS partial-length is 16 bits, and transmission is carried out the verification sequence that Cyclic Redundancy Check produces to physical layer frame head and mac frame head.The data message of data division for sending.Data division is made up of load and the Frame Check Sequence (FCS) of transmission, the variable-length of payload segment wherein, and the coded sequence of correspondence 5/6,3/4,2/3 and 1/2, its maximum length is distinguished 2876,2396,2156,1916 and 1436 bytes; The FCS partial-length is 32 bits, and transmission is carried out the verification sequence that CRC produces to payload segment.Synchronization pattern, frame head part and each burst transmissions one bit information of data division.
At transmitting terminal, the generation of digit pulse can be adopted accomplished in many ways.Fig. 3 has provided and has adopted staggered clock signal and method to produce the digit pulse generation of pulse and the realization schematic diagram of modulator 3.Fig. 4 has provided and has adopted adjusting clock signal duty cycle method to produce the digit pulse generation of pulse and the realization schematic diagram of modulator 3.Among Fig. 3, clock generator 31 produces high frequency clock signals, and clock distributor 32 is a two-way with this signal replication, and delayer 33 carries out the time-delay of different time to this two-way clock signal respectively with delayer 34, the two paths of signals after the time-delay with door 35 carry out with.In the ideal case, if the time difference of two-way time-delay is the odd of half pulse period length, be output as zero with door 35; In other cases, with the door 35 outputs pulse train identical with the clock cycle, its duty ratio changed with the time difference of two-way time-delay, through regulating the time difference, can access the pulse train of pulse duration in the subnanosecond level.With the pulse train input stopping direct current device 36 of door 35 outputs, its DC component of filtering.The output pulse sequence of stopping direct current device 36 is a differential signal, and its positive and negative terminal is input selector 37 simultaneously, and selector 37 is selected the output of one of positive and negative terminal according to the input data, when being " 1 " such as data symbol, selects anode output, promptly exports positive pulse; When data symbol is " 0 ", select negative terminal output, promptly export negative pulse, so just realized the pulse polarity modulation of pulse sequence.In Fig. 4; Clock duty cycle adjuster 38 is directly regulated the duty ratio of the clock sequence of clock generator 31 generations, when duty ratio is very little, has promptly obtained pulse train; This pulse train is differential signal; With the same among Fig. 3, behind stopping direct current device 36 and selector 37, the pulse train after the output modulation.Among the present invention, digit pulse generation and modulator 3 can use one of method of Fig. 3 and Fig. 4 to realize, after its output process transmitting terminal amplifier 4 amplifications and 5 filtering of transmitting terminal band pass filter, can be met the UWB pulse train of spectrum criterion requirement.The passband frequency range of transmitting terminal band pass filter 5 is 4.2-4.8GHz.
At receiving terminal, the passband frequency range of receiving terminal band pass filter 8 is 4.2-4.8GHz.The signal that reception antenna 7 receives amplifies through receiving terminal band pass filter 8 filtering and low noise amplifier 9, and 10 pairs of analog signals of A-D converter are carried out high-speed sampling and low-accuracy quantification then.Adopt a bit quantization precision.The A-D converter 10 of one bit quantization precision can adopt principle as shown in Figure 5 to realize.Among Fig. 5, the threshold level of comparator 1001 is a zero level.Comparator 1001 compares incoming signal level and preset threshold level, output high level signal when being higher than threshold level, output low level signal when being lower than threshold level.The output of comparator 1001 is divided into n=16 branch road through serial-parallel converter 1002, samples, and to reduce the requirement to each branch road sampling rate, the sampling clock frequency is 264MHz, and therefore, total sampling rate is 4224MHz.Sampling clock input phase shifter 1003, phase shifter 1003 outputs are with the input clock same frequency but the n road sampling clock and a circuit-switched data of out of phase read clock, and the phase difference between the sampling clock of the adjacent legs of output is π/8.Sampler 1004_1 to 1004_n samples to its input signal at the edge of its input sample clock, and reads the edge of clock in data, and the numerical value that reads is transferred to subsequent conditioning circuit simultaneously.The clock edge that sampling and data read can be rising edge or trailing edge, also can adopt rising edge and trailing edge simultaneously.
The digital signal of A-D converter 10 outputs is carried out a series of digital processings by digital detector 11, comprises that frame detects, synchronous and channel estimating and coherent detection etc., recovers the message bit stream in the frame.
The digital detector block diagram is as shown in Figure 6.Storage switch 1101 has data-storing and data flow handoff functionality among Fig. 6, and the parallel data that receives through inner memory array, is at first exported to sequence correlator 1102.Sequence correlator 1102 is according to the sequence S11 in the known leading character, with the sample value of each of receiving in the T1 interpulse period, multiply by the symbol of respective pulses among the sequence S11 after, the correspondence position in pulse adds up, accumulation length is N11, and is as shown in Figure 7.Among Fig. 7, fs is a sample frequency, fs=4224MHz.Therefore T1 * fs=256 is the interior sample number of each T1 interpulse period.Be a First Input First Output in the frame of broken lines, have N11 capable, 256 sample values of every row storage have the line display of grid shade that this line data multiply by-1, and the line display of no grid shade keeps this line data constant.Input data formation process from then on multiply by-1 at the row that the grid shade is arranged, and in formation, adds up by row then, obtains 256 accumulated values that constantly change, and exports to subsequent module.The output of sequence correlator 1102 via switch 1103, is at first exported to threshold detector 1104.Threshold detector 1104 compares the accumulation result of sequence correlator 1102 outputs with preset threshold value, this preset thresholding is 100.When detecting above thresholding, to send control information and give switch 1103 and channel estimator 1105, the data flow that sequence correlator 1102 is exported switches to channel estimator 1105, and starts channel estimator 1105.Channel estimator 1105 is in preseting length is 1023 input data, and maximizing is as the reference point of channel impulse response; And be starting point with Nb=5 sample value of reference point rollback; Export 256 sample values,, export to correlation detector 1106 as the result of channel estimating.Simultaneously, storage switch 1101 also will be exported in the peaked discovery position of channel estimating.Storage switch 1101 calculates the starting position of synchronization pattern in its memory array according to this position, and will be from then on the data that begin of position export to correlation detector 1106 and handle.Correlation detector 1106 will carry out related operation from the data of storage switch 1101 receptions and the channel estimation results that receives from channel estimator 1105, obtain the estimation to the data symbol that each transmitted pulse transmitted.Bit synchronizer 1107 is searched for known synchronization pattern in the output of correlation detector 1106.If search synchronization pattern, then according to the position of synchronization pattern, confirm the starting position of data division in the frame, accomplish bit synchronous; If in preset time, do not find synchronization pattern, think that then this frame takes defeat, restart reception to a new frame.
Channel decoder 12 adopts the ldpc decoder with the corresponding parameter of transmitting terminal.
Claims (4)
1. a high-speed sampling low-accuracy quantification impulse ultra-wideband wireless communications method is characterized in that this method is the elementary cell of physical layer data transmission with the frame, produces the base band pulse sequence at transmitting terminal with digital method; With sending data this base band pulse sequence is modulated, and amplify and bandpass filtering, signal controlling is in the 4.2-4.8GHz frequency band after the filtering; Arrive aerial via antenna transmission; At receiving terminal, after the transmitting terminal antenna transmission that receives carried out filtering and amplify to aerial signal, directly carry out high-speed sampling and low-accuracy quantification; Signal is transformed into numeric field; And design is applicable to synchronous, the channel estimating and the related detecting method of high-speed sampling and low-accuracy quantification signal, and the signal that is transformed into numeric field is handled, and recovers the information of transmission;
Said transmitting terminal is connected and composed by channel encoder (1), framer (2), digit pulse generation and modulator (3), transmitting terminal amplifier (4), transmitting terminal band pass filter (5) and transmitting antenna (6) successively; Receiving terminal is connected and composed by reception antenna (7), receiving terminal band pass filter (8), low noise amplifier (9), A-D converter (10), digital detector (11) and channel decoder (12) successively;
Said A-D converter (10) adopts the mode of high-speed sampling, low-accuracy quantification; When adopting a bit quantization, comparator (1001) compares incoming signal level and preset threshold level, output high level signal when being higher than threshold level, output low level signal when being lower than threshold level; The output of comparator (1001) is divided into n branch road through serial-parallel converter (1002); Sample; Sampling clock input phase shifter (1003), phase shifter (1003) output are with the input clock same frequency but the n road sampling clock and a circuit-switched data of out of phase read clock; Sampler (1004_1～1004_n) its input signal is sampled at the edge of its input sample clock, and read the edge of clock in data, the numerical value that reads is transferred to subsequent conditioning circuit simultaneously.
2. high-speed sampling low-accuracy quantification impulse ultra-wideband wireless communications method as claimed in claim 1; It is characterized in that frame as physical layer data transmission elementary cell; Form by leading character, synchronization pattern, frame head part and data division; Wherein the pulse spacing of the leading character pulse train of partly sending is T1, and the pulse spacing of the pulse train that other part is sent is T2; The value of T1 is greater than the length of the energy main part of wireless channel impulse response, and the value of T2 is less than T1; Leading character is made up of two parts pulse train, the S11={+ of first ,-,+,-... ,+}, wherein+with one represent positive pulse and negative pulse respectively, its pulse number is an odd number; Second portion S12={-,+,-... ,+}; Its pulse number is N12, and N12=10, synchronization pattern are that a length is the selected pseudorandom positive negative pulse stuffing sequence of N2=16.
3. high-speed sampling low-accuracy quantification impulse ultra-wideband wireless communications method as claimed in claim 1; It is characterized in that described digital method produce the base band pulse sequence adopt staggered clock signal with or regulate the generation of clock signal duty cycle method; In staggered clock signal and method; Clock generator (31) produces high frequency clock signal; Clock distributor (32) is a two-way with this signal replication, and delayer carries out the time-delay of different time to this two-way clock signal respectively with another delayer, the two paths of signals after the time-delay with door (35) carry out with; In regulating the clock signal duty cycle method, clock duty cycle adjuster (38) is directly regulated the duty ratio of the clock sequence of clock generator (31) generation, when duty ratio is very little, promptly obtains digital pulse sequence.
4. high-speed sampling low-accuracy quantification impulse ultra-wideband wireless communications method as claimed in claim 1 is characterized in that digital detector (11) is made up of storage switch (1101), sequence correlator (1102), switch (1103), threshold detector (1104), channel estimator (1105), correlation detector (1106) and bit synchronizer (1107); Storage switch (1101) has data-storing and data flow handoff functionality, and the parallel data that receives through inner memory array, is at first exported to sequence correlator (1102); Sequence correlator (1102) is according to the sequence S11 in the known leading character, with the sample value of each of receiving in the T1 interpulse period, multiply by the symbol of respective pulses among the sequence S11 after; Correspondence position in pulse adds up, and accumulation length is the length of sequence S11, the output of sequence correlator (1102); Via switch (1103), at first export to threshold detector (1104), threshold detector (1104) compares the accumulation result of sequence correlator (1102) output with preset threshold value; When detecting above thresholding, to send control information and give switch (1103) and channel estimator (1105), the data flow that sequence correlator (1102) is exported switches to channel estimator (1105); And start channel estimator (1105), channel estimator (1105) in the input data of its preseting length, maximizing; As the reference point of channel impulse response, and be starting point, export T1 * fs sample value with Nb sample value of reference point rollback; Result as channel estimating; Export to correlation detector (1106), simultaneously, the peaked discovery position of channel estimating; Also will export to storage switch (1101); Storage switch (1101) calculates the starting position of synchronization pattern in its memory array according to this position, and will be from then on the data that begin of position export to correlation detector (1106) and handle; Correlation detector (1106) will carry out related operation from the data of storage switch (1101) reception and the channel estimation results that receives from channel estimator (1105), obtain the estimation to the data symbol that each transmitted pulse transmitted; Bit synchronizer (1107) is searched for known synchronization pattern in the output of correlation detector (1106), confirm the starting position of data division in the frame; Wherein fs is a sample frequency, and pulse number is N, and b is a sequence number.
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| WO2011035493A1 (en) * | 2009-09-28 | 2011-03-31 | 东南大学 | High-speed sampling and low-precision quantification pulse ultra-wideband wireless communication method |
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